cpm2.c 8.3 KB

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  1. /*
  2. * General Purpose functions for the global management of the
  3. * 8260 Communication Processor Module.
  4. * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
  5. * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
  6. * 2.3.99 Updates
  7. *
  8. * 2006 (c) MontaVista Software, Inc.
  9. * Vitaly Bordug <vbordug@ru.mvista.com>
  10. * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
  11. *
  12. * This file is licensed under the terms of the GNU General Public License
  13. * version 2. This program is licensed "as is" without any warranty of any
  14. * kind, whether express or implied.
  15. */
  16. /*
  17. *
  18. * In addition to the individual control of the communication
  19. * channels, there are a few functions that globally affect the
  20. * communication processor.
  21. *
  22. * Buffer descriptors must be allocated from the dual ported memory
  23. * space. The allocator for that is here. When the communication
  24. * process is reset, we reclaim the memory available. There is
  25. * currently no deallocator for this memory.
  26. */
  27. #include <linux/errno.h>
  28. #include <linux/sched.h>
  29. #include <linux/kernel.h>
  30. #include <linux/param.h>
  31. #include <linux/string.h>
  32. #include <linux/mm.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/module.h>
  35. #include <linux/of.h>
  36. #include <asm/io.h>
  37. #include <asm/irq.h>
  38. #include <asm/mpc8260.h>
  39. #include <asm/page.h>
  40. #include <asm/cpm2.h>
  41. #include <asm/rheap.h>
  42. #include <asm/fs_pd.h>
  43. #include <sysdev/fsl_soc.h>
  44. cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
  45. /* We allocate this here because it is used almost exclusively for
  46. * the communication processor devices.
  47. */
  48. cpm2_map_t __iomem *cpm2_immr;
  49. EXPORT_SYMBOL(cpm2_immr);
  50. #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
  51. of space for CPM as it is larger
  52. than on PQ2 */
  53. void __init cpm2_reset(void)
  54. {
  55. #ifdef CONFIG_PPC_85xx
  56. cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
  57. #else
  58. cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
  59. #endif
  60. /* Tell everyone where the comm processor resides.
  61. */
  62. cpmp = &cpm2_immr->im_cpm;
  63. #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
  64. /* Reset the CPM.
  65. */
  66. cpm_command(CPM_CR_RST, 0);
  67. #endif
  68. }
  69. static DEFINE_SPINLOCK(cmd_lock);
  70. #define MAX_CR_CMD_LOOPS 10000
  71. int cpm_command(u32 command, u8 opcode)
  72. {
  73. int i, ret;
  74. unsigned long flags;
  75. spin_lock_irqsave(&cmd_lock, flags);
  76. ret = 0;
  77. out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
  78. for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
  79. if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
  80. goto out;
  81. printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
  82. ret = -EIO;
  83. out:
  84. spin_unlock_irqrestore(&cmd_lock, flags);
  85. return ret;
  86. }
  87. EXPORT_SYMBOL(cpm_command);
  88. /* Set a baud rate generator. This needs lots of work. There are
  89. * eight BRGs, which can be connected to the CPM channels or output
  90. * as clocks. The BRGs are in two different block of internal
  91. * memory mapped space.
  92. * The baud rate clock is the system clock divided by something.
  93. * It was set up long ago during the initial boot phase and is
  94. * is given to us.
  95. * Baud rate clocks are zero-based in the driver code (as that maps
  96. * to port numbers). Documentation uses 1-based numbering.
  97. */
  98. void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
  99. {
  100. u32 __iomem *bp;
  101. u32 val;
  102. /* This is good enough to get SMCs running.....
  103. */
  104. if (brg < 4) {
  105. bp = cpm2_map_size(im_brgc1, 16);
  106. } else {
  107. bp = cpm2_map_size(im_brgc5, 16);
  108. brg -= 4;
  109. }
  110. bp += brg;
  111. /* Round the clock divider to the nearest integer. */
  112. val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
  113. if (div16)
  114. val |= CPM_BRG_DIV16;
  115. out_be32(bp, val);
  116. cpm2_unmap(bp);
  117. }
  118. EXPORT_SYMBOL(__cpm2_setbrg);
  119. int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
  120. {
  121. int ret = 0;
  122. int shift;
  123. int i, bits = 0;
  124. cpmux_t __iomem *im_cpmux;
  125. u32 __iomem *reg;
  126. u32 mask = 7;
  127. u8 clk_map[][3] = {
  128. {CPM_CLK_FCC1, CPM_BRG5, 0},
  129. {CPM_CLK_FCC1, CPM_BRG6, 1},
  130. {CPM_CLK_FCC1, CPM_BRG7, 2},
  131. {CPM_CLK_FCC1, CPM_BRG8, 3},
  132. {CPM_CLK_FCC1, CPM_CLK9, 4},
  133. {CPM_CLK_FCC1, CPM_CLK10, 5},
  134. {CPM_CLK_FCC1, CPM_CLK11, 6},
  135. {CPM_CLK_FCC1, CPM_CLK12, 7},
  136. {CPM_CLK_FCC2, CPM_BRG5, 0},
  137. {CPM_CLK_FCC2, CPM_BRG6, 1},
  138. {CPM_CLK_FCC2, CPM_BRG7, 2},
  139. {CPM_CLK_FCC2, CPM_BRG8, 3},
  140. {CPM_CLK_FCC2, CPM_CLK13, 4},
  141. {CPM_CLK_FCC2, CPM_CLK14, 5},
  142. {CPM_CLK_FCC2, CPM_CLK15, 6},
  143. {CPM_CLK_FCC2, CPM_CLK16, 7},
  144. {CPM_CLK_FCC3, CPM_BRG5, 0},
  145. {CPM_CLK_FCC3, CPM_BRG6, 1},
  146. {CPM_CLK_FCC3, CPM_BRG7, 2},
  147. {CPM_CLK_FCC3, CPM_BRG8, 3},
  148. {CPM_CLK_FCC3, CPM_CLK13, 4},
  149. {CPM_CLK_FCC3, CPM_CLK14, 5},
  150. {CPM_CLK_FCC3, CPM_CLK15, 6},
  151. {CPM_CLK_FCC3, CPM_CLK16, 7},
  152. {CPM_CLK_SCC1, CPM_BRG1, 0},
  153. {CPM_CLK_SCC1, CPM_BRG2, 1},
  154. {CPM_CLK_SCC1, CPM_BRG3, 2},
  155. {CPM_CLK_SCC1, CPM_BRG4, 3},
  156. {CPM_CLK_SCC1, CPM_CLK11, 4},
  157. {CPM_CLK_SCC1, CPM_CLK12, 5},
  158. {CPM_CLK_SCC1, CPM_CLK3, 6},
  159. {CPM_CLK_SCC1, CPM_CLK4, 7},
  160. {CPM_CLK_SCC2, CPM_BRG1, 0},
  161. {CPM_CLK_SCC2, CPM_BRG2, 1},
  162. {CPM_CLK_SCC2, CPM_BRG3, 2},
  163. {CPM_CLK_SCC2, CPM_BRG4, 3},
  164. {CPM_CLK_SCC2, CPM_CLK11, 4},
  165. {CPM_CLK_SCC2, CPM_CLK12, 5},
  166. {CPM_CLK_SCC2, CPM_CLK3, 6},
  167. {CPM_CLK_SCC2, CPM_CLK4, 7},
  168. {CPM_CLK_SCC3, CPM_BRG1, 0},
  169. {CPM_CLK_SCC3, CPM_BRG2, 1},
  170. {CPM_CLK_SCC3, CPM_BRG3, 2},
  171. {CPM_CLK_SCC3, CPM_BRG4, 3},
  172. {CPM_CLK_SCC3, CPM_CLK5, 4},
  173. {CPM_CLK_SCC3, CPM_CLK6, 5},
  174. {CPM_CLK_SCC3, CPM_CLK7, 6},
  175. {CPM_CLK_SCC3, CPM_CLK8, 7},
  176. {CPM_CLK_SCC4, CPM_BRG1, 0},
  177. {CPM_CLK_SCC4, CPM_BRG2, 1},
  178. {CPM_CLK_SCC4, CPM_BRG3, 2},
  179. {CPM_CLK_SCC4, CPM_BRG4, 3},
  180. {CPM_CLK_SCC4, CPM_CLK5, 4},
  181. {CPM_CLK_SCC4, CPM_CLK6, 5},
  182. {CPM_CLK_SCC4, CPM_CLK7, 6},
  183. {CPM_CLK_SCC4, CPM_CLK8, 7},
  184. };
  185. im_cpmux = cpm2_map(im_cpmux);
  186. switch (target) {
  187. case CPM_CLK_SCC1:
  188. reg = &im_cpmux->cmx_scr;
  189. shift = 24;
  190. break;
  191. case CPM_CLK_SCC2:
  192. reg = &im_cpmux->cmx_scr;
  193. shift = 16;
  194. break;
  195. case CPM_CLK_SCC3:
  196. reg = &im_cpmux->cmx_scr;
  197. shift = 8;
  198. break;
  199. case CPM_CLK_SCC4:
  200. reg = &im_cpmux->cmx_scr;
  201. shift = 0;
  202. break;
  203. case CPM_CLK_FCC1:
  204. reg = &im_cpmux->cmx_fcr;
  205. shift = 24;
  206. break;
  207. case CPM_CLK_FCC2:
  208. reg = &im_cpmux->cmx_fcr;
  209. shift = 16;
  210. break;
  211. case CPM_CLK_FCC3:
  212. reg = &im_cpmux->cmx_fcr;
  213. shift = 8;
  214. break;
  215. default:
  216. printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
  217. return -EINVAL;
  218. }
  219. for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
  220. if (clk_map[i][0] == target && clk_map[i][1] == clock) {
  221. bits = clk_map[i][2];
  222. break;
  223. }
  224. }
  225. if (i == ARRAY_SIZE(clk_map))
  226. ret = -EINVAL;
  227. bits <<= shift;
  228. mask <<= shift;
  229. if (mode == CPM_CLK_RTX) {
  230. bits |= bits << 3;
  231. mask |= mask << 3;
  232. } else if (mode == CPM_CLK_RX) {
  233. bits <<= 3;
  234. mask <<= 3;
  235. }
  236. out_be32(reg, (in_be32(reg) & ~mask) | bits);
  237. cpm2_unmap(im_cpmux);
  238. return ret;
  239. }
  240. int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
  241. {
  242. int ret = 0;
  243. int shift;
  244. int i, bits = 0;
  245. cpmux_t __iomem *im_cpmux;
  246. u8 __iomem *reg;
  247. u8 mask = 3;
  248. u8 clk_map[][3] = {
  249. {CPM_CLK_SMC1, CPM_BRG1, 0},
  250. {CPM_CLK_SMC1, CPM_BRG7, 1},
  251. {CPM_CLK_SMC1, CPM_CLK7, 2},
  252. {CPM_CLK_SMC1, CPM_CLK9, 3},
  253. {CPM_CLK_SMC2, CPM_BRG2, 0},
  254. {CPM_CLK_SMC2, CPM_BRG8, 1},
  255. {CPM_CLK_SMC2, CPM_CLK4, 2},
  256. {CPM_CLK_SMC2, CPM_CLK15, 3},
  257. };
  258. im_cpmux = cpm2_map(im_cpmux);
  259. switch (target) {
  260. case CPM_CLK_SMC1:
  261. reg = &im_cpmux->cmx_smr;
  262. mask = 3;
  263. shift = 4;
  264. break;
  265. case CPM_CLK_SMC2:
  266. reg = &im_cpmux->cmx_smr;
  267. mask = 3;
  268. shift = 0;
  269. break;
  270. default:
  271. printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
  272. return -EINVAL;
  273. }
  274. for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
  275. if (clk_map[i][0] == target && clk_map[i][1] == clock) {
  276. bits = clk_map[i][2];
  277. break;
  278. }
  279. }
  280. if (i == ARRAY_SIZE(clk_map))
  281. ret = -EINVAL;
  282. bits <<= shift;
  283. mask <<= shift;
  284. out_8(reg, (in_8(reg) & ~mask) | bits);
  285. cpm2_unmap(im_cpmux);
  286. return ret;
  287. }
  288. struct cpm2_ioports {
  289. u32 dir, par, sor, odr, dat;
  290. u32 res[3];
  291. };
  292. void cpm2_set_pin(int port, int pin, int flags)
  293. {
  294. struct cpm2_ioports __iomem *iop =
  295. (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
  296. pin = 1 << (31 - pin);
  297. if (flags & CPM_PIN_OUTPUT)
  298. setbits32(&iop[port].dir, pin);
  299. else
  300. clrbits32(&iop[port].dir, pin);
  301. if (!(flags & CPM_PIN_GPIO))
  302. setbits32(&iop[port].par, pin);
  303. else
  304. clrbits32(&iop[port].par, pin);
  305. if (flags & CPM_PIN_SECONDARY)
  306. setbits32(&iop[port].sor, pin);
  307. else
  308. clrbits32(&iop[port].sor, pin);
  309. if (flags & CPM_PIN_OPENDRAIN)
  310. setbits32(&iop[port].odr, pin);
  311. else
  312. clrbits32(&iop[port].odr, pin);
  313. }