booke_emulate.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright IBM Corp. 2008
  5. * Copyright 2011 Freescale Semiconductor, Inc.
  6. *
  7. * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  8. */
  9. #include <linux/kvm_host.h>
  10. #include <asm/disassemble.h>
  11. #include "booke.h"
  12. #define OP_19_XOP_RFI 50
  13. #define OP_19_XOP_RFCI 51
  14. #define OP_19_XOP_RFDI 39
  15. #define OP_31_XOP_MFMSR 83
  16. #define OP_31_XOP_WRTEE 131
  17. #define OP_31_XOP_MTMSR 146
  18. #define OP_31_XOP_WRTEEI 163
  19. static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
  20. {
  21. vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
  22. kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
  23. }
  24. static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
  25. {
  26. vcpu->arch.regs.nip = vcpu->arch.dsrr0;
  27. kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
  28. }
  29. static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
  30. {
  31. vcpu->arch.regs.nip = vcpu->arch.csrr0;
  32. kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
  33. }
  34. int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
  35. unsigned int inst, int *advance)
  36. {
  37. int emulated = EMULATE_DONE;
  38. int rs = get_rs(inst);
  39. int rt = get_rt(inst);
  40. switch (get_op(inst)) {
  41. case 19:
  42. switch (get_xop(inst)) {
  43. case OP_19_XOP_RFI:
  44. kvmppc_emul_rfi(vcpu);
  45. kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
  46. *advance = 0;
  47. break;
  48. case OP_19_XOP_RFCI:
  49. kvmppc_emul_rfci(vcpu);
  50. kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
  51. *advance = 0;
  52. break;
  53. case OP_19_XOP_RFDI:
  54. kvmppc_emul_rfdi(vcpu);
  55. kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
  56. *advance = 0;
  57. break;
  58. default:
  59. emulated = EMULATE_FAIL;
  60. break;
  61. }
  62. break;
  63. case 31:
  64. switch (get_xop(inst)) {
  65. case OP_31_XOP_MFMSR:
  66. kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
  67. kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
  68. break;
  69. case OP_31_XOP_MTMSR:
  70. kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
  71. kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
  72. break;
  73. case OP_31_XOP_WRTEE:
  74. vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
  75. | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
  76. kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
  77. break;
  78. case OP_31_XOP_WRTEEI:
  79. vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
  80. | (inst & MSR_EE);
  81. kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
  82. break;
  83. default:
  84. emulated = EMULATE_FAIL;
  85. }
  86. break;
  87. default:
  88. emulated = EMULATE_FAIL;
  89. }
  90. return emulated;
  91. }
  92. /*
  93. * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
  94. * Their backing store is in real registers, and these functions
  95. * will return the wrong result if called for them in another context
  96. * (such as debugging).
  97. */
  98. int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
  99. {
  100. int emulated = EMULATE_DONE;
  101. bool debug_inst = false;
  102. switch (sprn) {
  103. case SPRN_DEAR:
  104. vcpu->arch.shared->dar = spr_val;
  105. break;
  106. case SPRN_ESR:
  107. vcpu->arch.shared->esr = spr_val;
  108. break;
  109. case SPRN_CSRR0:
  110. vcpu->arch.csrr0 = spr_val;
  111. break;
  112. case SPRN_CSRR1:
  113. vcpu->arch.csrr1 = spr_val;
  114. break;
  115. case SPRN_DSRR0:
  116. vcpu->arch.dsrr0 = spr_val;
  117. break;
  118. case SPRN_DSRR1:
  119. vcpu->arch.dsrr1 = spr_val;
  120. break;
  121. case SPRN_IAC1:
  122. /*
  123. * If userspace is debugging guest then guest
  124. * can not access debug registers.
  125. */
  126. if (vcpu->guest_debug)
  127. break;
  128. debug_inst = true;
  129. vcpu->arch.dbg_reg.iac1 = spr_val;
  130. break;
  131. case SPRN_IAC2:
  132. /*
  133. * If userspace is debugging guest then guest
  134. * can not access debug registers.
  135. */
  136. if (vcpu->guest_debug)
  137. break;
  138. debug_inst = true;
  139. vcpu->arch.dbg_reg.iac2 = spr_val;
  140. break;
  141. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  142. case SPRN_IAC3:
  143. /*
  144. * If userspace is debugging guest then guest
  145. * can not access debug registers.
  146. */
  147. if (vcpu->guest_debug)
  148. break;
  149. debug_inst = true;
  150. vcpu->arch.dbg_reg.iac3 = spr_val;
  151. break;
  152. case SPRN_IAC4:
  153. /*
  154. * If userspace is debugging guest then guest
  155. * can not access debug registers.
  156. */
  157. if (vcpu->guest_debug)
  158. break;
  159. debug_inst = true;
  160. vcpu->arch.dbg_reg.iac4 = spr_val;
  161. break;
  162. #endif
  163. case SPRN_DAC1:
  164. /*
  165. * If userspace is debugging guest then guest
  166. * can not access debug registers.
  167. */
  168. if (vcpu->guest_debug)
  169. break;
  170. debug_inst = true;
  171. vcpu->arch.dbg_reg.dac1 = spr_val;
  172. break;
  173. case SPRN_DAC2:
  174. /*
  175. * If userspace is debugging guest then guest
  176. * can not access debug registers.
  177. */
  178. if (vcpu->guest_debug)
  179. break;
  180. debug_inst = true;
  181. vcpu->arch.dbg_reg.dac2 = spr_val;
  182. break;
  183. case SPRN_DBCR0:
  184. /*
  185. * If userspace is debugging guest then guest
  186. * can not access debug registers.
  187. */
  188. if (vcpu->guest_debug)
  189. break;
  190. debug_inst = true;
  191. spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
  192. DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4 |
  193. DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
  194. vcpu->arch.dbg_reg.dbcr0 = spr_val;
  195. break;
  196. case SPRN_DBCR1:
  197. /*
  198. * If userspace is debugging guest then guest
  199. * can not access debug registers.
  200. */
  201. if (vcpu->guest_debug)
  202. break;
  203. debug_inst = true;
  204. vcpu->arch.dbg_reg.dbcr1 = spr_val;
  205. break;
  206. case SPRN_DBCR2:
  207. /*
  208. * If userspace is debugging guest then guest
  209. * can not access debug registers.
  210. */
  211. if (vcpu->guest_debug)
  212. break;
  213. debug_inst = true;
  214. vcpu->arch.dbg_reg.dbcr2 = spr_val;
  215. break;
  216. case SPRN_DBSR:
  217. /*
  218. * If userspace is debugging guest then guest
  219. * can not access debug registers.
  220. */
  221. if (vcpu->guest_debug)
  222. break;
  223. vcpu->arch.dbsr &= ~spr_val;
  224. if (!(vcpu->arch.dbsr & ~DBSR_IDE))
  225. kvmppc_core_dequeue_debug(vcpu);
  226. break;
  227. case SPRN_TSR:
  228. kvmppc_clr_tsr_bits(vcpu, spr_val);
  229. break;
  230. case SPRN_TCR:
  231. /*
  232. * WRC is a 2-bit field that is supposed to preserve its
  233. * value once written to non-zero.
  234. */
  235. if (vcpu->arch.tcr & TCR_WRC_MASK) {
  236. spr_val &= ~TCR_WRC_MASK;
  237. spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
  238. }
  239. kvmppc_set_tcr(vcpu, spr_val);
  240. break;
  241. case SPRN_DECAR:
  242. vcpu->arch.decar = spr_val;
  243. break;
  244. /*
  245. * Note: SPRG4-7 are user-readable.
  246. * These values are loaded into the real SPRGs when resuming the
  247. * guest (PR-mode only).
  248. */
  249. case SPRN_SPRG4:
  250. kvmppc_set_sprg4(vcpu, spr_val);
  251. break;
  252. case SPRN_SPRG5:
  253. kvmppc_set_sprg5(vcpu, spr_val);
  254. break;
  255. case SPRN_SPRG6:
  256. kvmppc_set_sprg6(vcpu, spr_val);
  257. break;
  258. case SPRN_SPRG7:
  259. kvmppc_set_sprg7(vcpu, spr_val);
  260. break;
  261. case SPRN_IVPR:
  262. vcpu->arch.ivpr = spr_val;
  263. #ifdef CONFIG_KVM_BOOKE_HV
  264. mtspr(SPRN_GIVPR, spr_val);
  265. #endif
  266. break;
  267. case SPRN_IVOR0:
  268. vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
  269. break;
  270. case SPRN_IVOR1:
  271. vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
  272. break;
  273. case SPRN_IVOR2:
  274. vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
  275. #ifdef CONFIG_KVM_BOOKE_HV
  276. mtspr(SPRN_GIVOR2, spr_val);
  277. #endif
  278. break;
  279. case SPRN_IVOR3:
  280. vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
  281. break;
  282. case SPRN_IVOR4:
  283. vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
  284. break;
  285. case SPRN_IVOR5:
  286. vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
  287. break;
  288. case SPRN_IVOR6:
  289. vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
  290. break;
  291. case SPRN_IVOR7:
  292. vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
  293. break;
  294. case SPRN_IVOR8:
  295. vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
  296. #ifdef CONFIG_KVM_BOOKE_HV
  297. mtspr(SPRN_GIVOR8, spr_val);
  298. #endif
  299. break;
  300. case SPRN_IVOR9:
  301. vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
  302. break;
  303. case SPRN_IVOR10:
  304. vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
  305. break;
  306. case SPRN_IVOR11:
  307. vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
  308. break;
  309. case SPRN_IVOR12:
  310. vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
  311. break;
  312. case SPRN_IVOR13:
  313. vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
  314. break;
  315. case SPRN_IVOR14:
  316. vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
  317. break;
  318. case SPRN_IVOR15:
  319. vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
  320. break;
  321. case SPRN_MCSR:
  322. vcpu->arch.mcsr &= ~spr_val;
  323. break;
  324. #if defined(CONFIG_64BIT)
  325. case SPRN_EPCR:
  326. kvmppc_set_epcr(vcpu, spr_val);
  327. #ifdef CONFIG_KVM_BOOKE_HV
  328. mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
  329. #endif
  330. break;
  331. #endif
  332. default:
  333. emulated = EMULATE_FAIL;
  334. }
  335. if (debug_inst) {
  336. current->thread.debug = vcpu->arch.dbg_reg;
  337. switch_booke_debug_regs(&vcpu->arch.dbg_reg);
  338. }
  339. return emulated;
  340. }
  341. int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
  342. {
  343. int emulated = EMULATE_DONE;
  344. switch (sprn) {
  345. case SPRN_IVPR:
  346. *spr_val = vcpu->arch.ivpr;
  347. break;
  348. case SPRN_DEAR:
  349. *spr_val = vcpu->arch.shared->dar;
  350. break;
  351. case SPRN_ESR:
  352. *spr_val = vcpu->arch.shared->esr;
  353. break;
  354. case SPRN_EPR:
  355. *spr_val = vcpu->arch.epr;
  356. break;
  357. case SPRN_CSRR0:
  358. *spr_val = vcpu->arch.csrr0;
  359. break;
  360. case SPRN_CSRR1:
  361. *spr_val = vcpu->arch.csrr1;
  362. break;
  363. case SPRN_DSRR0:
  364. *spr_val = vcpu->arch.dsrr0;
  365. break;
  366. case SPRN_DSRR1:
  367. *spr_val = vcpu->arch.dsrr1;
  368. break;
  369. case SPRN_IAC1:
  370. *spr_val = vcpu->arch.dbg_reg.iac1;
  371. break;
  372. case SPRN_IAC2:
  373. *spr_val = vcpu->arch.dbg_reg.iac2;
  374. break;
  375. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  376. case SPRN_IAC3:
  377. *spr_val = vcpu->arch.dbg_reg.iac3;
  378. break;
  379. case SPRN_IAC4:
  380. *spr_val = vcpu->arch.dbg_reg.iac4;
  381. break;
  382. #endif
  383. case SPRN_DAC1:
  384. *spr_val = vcpu->arch.dbg_reg.dac1;
  385. break;
  386. case SPRN_DAC2:
  387. *spr_val = vcpu->arch.dbg_reg.dac2;
  388. break;
  389. case SPRN_DBCR0:
  390. *spr_val = vcpu->arch.dbg_reg.dbcr0;
  391. if (vcpu->guest_debug)
  392. *spr_val = *spr_val | DBCR0_EDM;
  393. break;
  394. case SPRN_DBCR1:
  395. *spr_val = vcpu->arch.dbg_reg.dbcr1;
  396. break;
  397. case SPRN_DBCR2:
  398. *spr_val = vcpu->arch.dbg_reg.dbcr2;
  399. break;
  400. case SPRN_DBSR:
  401. *spr_val = vcpu->arch.dbsr;
  402. break;
  403. case SPRN_TSR:
  404. *spr_val = vcpu->arch.tsr;
  405. break;
  406. case SPRN_TCR:
  407. *spr_val = vcpu->arch.tcr;
  408. break;
  409. case SPRN_IVOR0:
  410. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
  411. break;
  412. case SPRN_IVOR1:
  413. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
  414. break;
  415. case SPRN_IVOR2:
  416. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
  417. break;
  418. case SPRN_IVOR3:
  419. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
  420. break;
  421. case SPRN_IVOR4:
  422. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
  423. break;
  424. case SPRN_IVOR5:
  425. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
  426. break;
  427. case SPRN_IVOR6:
  428. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
  429. break;
  430. case SPRN_IVOR7:
  431. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
  432. break;
  433. case SPRN_IVOR8:
  434. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
  435. break;
  436. case SPRN_IVOR9:
  437. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
  438. break;
  439. case SPRN_IVOR10:
  440. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
  441. break;
  442. case SPRN_IVOR11:
  443. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
  444. break;
  445. case SPRN_IVOR12:
  446. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
  447. break;
  448. case SPRN_IVOR13:
  449. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
  450. break;
  451. case SPRN_IVOR14:
  452. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
  453. break;
  454. case SPRN_IVOR15:
  455. *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
  456. break;
  457. case SPRN_MCSR:
  458. *spr_val = vcpu->arch.mcsr;
  459. break;
  460. #if defined(CONFIG_64BIT)
  461. case SPRN_EPCR:
  462. *spr_val = vcpu->arch.epcr;
  463. break;
  464. #endif
  465. default:
  466. emulated = EMULATE_FAIL;
  467. }
  468. return emulated;
  469. }