book3s_pr.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved.
  4. *
  5. * Authors:
  6. * Alexander Graf <agraf@suse.de>
  7. * Kevin Wolf <mail@kevin-wolf.de>
  8. * Paul Mackerras <paulus@samba.org>
  9. *
  10. * Description:
  11. * Functions relating to running KVM on Book 3S processors where
  12. * we don't have access to hypervisor mode, and we run the guest
  13. * in problem state (user mode).
  14. *
  15. * This file is derived from arch/powerpc/kvm/44x.c,
  16. * by Hollis Blanchard <hollisb@us.ibm.com>.
  17. */
  18. #include <linux/kvm_host.h>
  19. #include <linux/export.h>
  20. #include <linux/err.h>
  21. #include <linux/slab.h>
  22. #include <asm/reg.h>
  23. #include <asm/cputable.h>
  24. #include <asm/cacheflush.h>
  25. #include <linux/uaccess.h>
  26. #include <asm/io.h>
  27. #include <asm/kvm_ppc.h>
  28. #include <asm/kvm_book3s.h>
  29. #include <asm/mmu_context.h>
  30. #include <asm/switch_to.h>
  31. #include <asm/firmware.h>
  32. #include <asm/setup.h>
  33. #include <linux/gfp.h>
  34. #include <linux/sched.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/highmem.h>
  37. #include <linux/module.h>
  38. #include <linux/miscdevice.h>
  39. #include <asm/asm-prototypes.h>
  40. #include <asm/tm.h>
  41. #include "book3s.h"
  42. #define CREATE_TRACE_POINTS
  43. #include "trace_pr.h"
  44. /* #define EXIT_DEBUG */
  45. /* #define DEBUG_EXT */
  46. static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
  47. ulong msr);
  48. #ifdef CONFIG_PPC_BOOK3S_64
  49. static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac);
  50. #endif
  51. /* Some compatibility defines */
  52. #ifdef CONFIG_PPC_BOOK3S_32
  53. #define MSR_USER32 MSR_USER
  54. #define MSR_USER64 MSR_USER
  55. #define HW_PAGE_SIZE PAGE_SIZE
  56. #define HPTE_R_M _PAGE_COHERENT
  57. #endif
  58. static bool kvmppc_is_split_real(struct kvm_vcpu *vcpu)
  59. {
  60. ulong msr = kvmppc_get_msr(vcpu);
  61. return (msr & (MSR_IR|MSR_DR)) == MSR_DR;
  62. }
  63. static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu)
  64. {
  65. ulong msr = kvmppc_get_msr(vcpu);
  66. ulong pc = kvmppc_get_pc(vcpu);
  67. /* We are in DR only split real mode */
  68. if ((msr & (MSR_IR|MSR_DR)) != MSR_DR)
  69. return;
  70. /* We have not fixed up the guest already */
  71. if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK)
  72. return;
  73. /* The code is in fixupable address space */
  74. if (pc & SPLIT_HACK_MASK)
  75. return;
  76. vcpu->arch.hflags |= BOOK3S_HFLAG_SPLIT_HACK;
  77. kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS);
  78. }
  79. static void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu)
  80. {
  81. if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) {
  82. ulong pc = kvmppc_get_pc(vcpu);
  83. ulong lr = kvmppc_get_lr(vcpu);
  84. if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)
  85. kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK);
  86. if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)
  87. kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK);
  88. vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK;
  89. }
  90. }
  91. static void kvmppc_inject_interrupt_pr(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags)
  92. {
  93. unsigned long msr, pc, new_msr, new_pc;
  94. kvmppc_unfixup_split_real(vcpu);
  95. msr = kvmppc_get_msr(vcpu);
  96. pc = kvmppc_get_pc(vcpu);
  97. new_msr = vcpu->arch.intr_msr;
  98. new_pc = to_book3s(vcpu)->hior + vec;
  99. #ifdef CONFIG_PPC_BOOK3S_64
  100. /* If transactional, change to suspend mode on IRQ delivery */
  101. if (MSR_TM_TRANSACTIONAL(msr))
  102. new_msr |= MSR_TS_S;
  103. else
  104. new_msr |= msr & MSR_TS_MASK;
  105. #endif
  106. kvmppc_set_srr0(vcpu, pc);
  107. kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags);
  108. kvmppc_set_pc(vcpu, new_pc);
  109. kvmppc_set_msr(vcpu, new_msr);
  110. }
  111. static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu)
  112. {
  113. #ifdef CONFIG_PPC_BOOK3S_64
  114. struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
  115. memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb));
  116. svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max;
  117. svcpu->in_use = 0;
  118. svcpu_put(svcpu);
  119. #endif
  120. /* Disable AIL if supported */
  121. if (cpu_has_feature(CPU_FTR_HVMODE) &&
  122. cpu_has_feature(CPU_FTR_ARCH_207S))
  123. mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_AIL);
  124. vcpu->cpu = smp_processor_id();
  125. #ifdef CONFIG_PPC_BOOK3S_32
  126. current->thread.kvm_shadow_vcpu = vcpu->arch.shadow_vcpu;
  127. #endif
  128. if (kvmppc_is_split_real(vcpu))
  129. kvmppc_fixup_split_real(vcpu);
  130. kvmppc_restore_tm_pr(vcpu);
  131. }
  132. static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu)
  133. {
  134. #ifdef CONFIG_PPC_BOOK3S_64
  135. struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
  136. if (svcpu->in_use) {
  137. kvmppc_copy_from_svcpu(vcpu);
  138. }
  139. memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb));
  140. to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max;
  141. svcpu_put(svcpu);
  142. #endif
  143. if (kvmppc_is_split_real(vcpu))
  144. kvmppc_unfixup_split_real(vcpu);
  145. kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
  146. kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
  147. kvmppc_save_tm_pr(vcpu);
  148. /* Enable AIL if supported */
  149. if (cpu_has_feature(CPU_FTR_HVMODE) &&
  150. cpu_has_feature(CPU_FTR_ARCH_207S))
  151. mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_AIL_3);
  152. vcpu->cpu = -1;
  153. }
  154. /* Copy data needed by real-mode code from vcpu to shadow vcpu */
  155. void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu)
  156. {
  157. struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
  158. svcpu->gpr[0] = vcpu->arch.regs.gpr[0];
  159. svcpu->gpr[1] = vcpu->arch.regs.gpr[1];
  160. svcpu->gpr[2] = vcpu->arch.regs.gpr[2];
  161. svcpu->gpr[3] = vcpu->arch.regs.gpr[3];
  162. svcpu->gpr[4] = vcpu->arch.regs.gpr[4];
  163. svcpu->gpr[5] = vcpu->arch.regs.gpr[5];
  164. svcpu->gpr[6] = vcpu->arch.regs.gpr[6];
  165. svcpu->gpr[7] = vcpu->arch.regs.gpr[7];
  166. svcpu->gpr[8] = vcpu->arch.regs.gpr[8];
  167. svcpu->gpr[9] = vcpu->arch.regs.gpr[9];
  168. svcpu->gpr[10] = vcpu->arch.regs.gpr[10];
  169. svcpu->gpr[11] = vcpu->arch.regs.gpr[11];
  170. svcpu->gpr[12] = vcpu->arch.regs.gpr[12];
  171. svcpu->gpr[13] = vcpu->arch.regs.gpr[13];
  172. svcpu->cr = vcpu->arch.regs.ccr;
  173. svcpu->xer = vcpu->arch.regs.xer;
  174. svcpu->ctr = vcpu->arch.regs.ctr;
  175. svcpu->lr = vcpu->arch.regs.link;
  176. svcpu->pc = vcpu->arch.regs.nip;
  177. #ifdef CONFIG_PPC_BOOK3S_64
  178. svcpu->shadow_fscr = vcpu->arch.shadow_fscr;
  179. #endif
  180. /*
  181. * Now also save the current time base value. We use this
  182. * to find the guest purr and spurr value.
  183. */
  184. vcpu->arch.entry_tb = get_tb();
  185. vcpu->arch.entry_vtb = get_vtb();
  186. if (cpu_has_feature(CPU_FTR_ARCH_207S))
  187. vcpu->arch.entry_ic = mfspr(SPRN_IC);
  188. svcpu->in_use = true;
  189. svcpu_put(svcpu);
  190. }
  191. static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
  192. {
  193. ulong guest_msr = kvmppc_get_msr(vcpu);
  194. ulong smsr = guest_msr;
  195. /* Guest MSR values */
  196. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  197. smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE |
  198. MSR_TM | MSR_TS_MASK;
  199. #else
  200. smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE;
  201. #endif
  202. /* Process MSR values */
  203. smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE;
  204. /* External providers the guest reserved */
  205. smsr |= (guest_msr & vcpu->arch.guest_owned_ext);
  206. /* 64-bit Process MSR values */
  207. #ifdef CONFIG_PPC_BOOK3S_64
  208. smsr |= MSR_ISF | MSR_HV;
  209. #endif
  210. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  211. /*
  212. * in guest privileged state, we want to fail all TM transactions.
  213. * So disable MSR TM bit so that all tbegin. will be able to be
  214. * trapped into host.
  215. */
  216. if (!(guest_msr & MSR_PR))
  217. smsr &= ~MSR_TM;
  218. #endif
  219. vcpu->arch.shadow_msr = smsr;
  220. }
  221. /* Copy data touched by real-mode code from shadow vcpu back to vcpu */
  222. void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu)
  223. {
  224. struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
  225. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  226. ulong old_msr;
  227. #endif
  228. /*
  229. * Maybe we were already preempted and synced the svcpu from
  230. * our preempt notifiers. Don't bother touching this svcpu then.
  231. */
  232. if (!svcpu->in_use)
  233. goto out;
  234. vcpu->arch.regs.gpr[0] = svcpu->gpr[0];
  235. vcpu->arch.regs.gpr[1] = svcpu->gpr[1];
  236. vcpu->arch.regs.gpr[2] = svcpu->gpr[2];
  237. vcpu->arch.regs.gpr[3] = svcpu->gpr[3];
  238. vcpu->arch.regs.gpr[4] = svcpu->gpr[4];
  239. vcpu->arch.regs.gpr[5] = svcpu->gpr[5];
  240. vcpu->arch.regs.gpr[6] = svcpu->gpr[6];
  241. vcpu->arch.regs.gpr[7] = svcpu->gpr[7];
  242. vcpu->arch.regs.gpr[8] = svcpu->gpr[8];
  243. vcpu->arch.regs.gpr[9] = svcpu->gpr[9];
  244. vcpu->arch.regs.gpr[10] = svcpu->gpr[10];
  245. vcpu->arch.regs.gpr[11] = svcpu->gpr[11];
  246. vcpu->arch.regs.gpr[12] = svcpu->gpr[12];
  247. vcpu->arch.regs.gpr[13] = svcpu->gpr[13];
  248. vcpu->arch.regs.ccr = svcpu->cr;
  249. vcpu->arch.regs.xer = svcpu->xer;
  250. vcpu->arch.regs.ctr = svcpu->ctr;
  251. vcpu->arch.regs.link = svcpu->lr;
  252. vcpu->arch.regs.nip = svcpu->pc;
  253. vcpu->arch.shadow_srr1 = svcpu->shadow_srr1;
  254. vcpu->arch.fault_dar = svcpu->fault_dar;
  255. vcpu->arch.fault_dsisr = svcpu->fault_dsisr;
  256. vcpu->arch.last_inst = svcpu->last_inst;
  257. #ifdef CONFIG_PPC_BOOK3S_64
  258. vcpu->arch.shadow_fscr = svcpu->shadow_fscr;
  259. #endif
  260. /*
  261. * Update purr and spurr using time base on exit.
  262. */
  263. vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
  264. vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
  265. to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb;
  266. if (cpu_has_feature(CPU_FTR_ARCH_207S))
  267. vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic;
  268. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  269. /*
  270. * Unlike other MSR bits, MSR[TS]bits can be changed at guest without
  271. * notifying host:
  272. * modified by unprivileged instructions like "tbegin"/"tend"/
  273. * "tresume"/"tsuspend" in PR KVM guest.
  274. *
  275. * It is necessary to sync here to calculate a correct shadow_msr.
  276. *
  277. * privileged guest's tbegin will be failed at present. So we
  278. * only take care of problem state guest.
  279. */
  280. old_msr = kvmppc_get_msr(vcpu);
  281. if (unlikely((old_msr & MSR_PR) &&
  282. (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) !=
  283. (old_msr & (MSR_TS_MASK)))) {
  284. old_msr &= ~(MSR_TS_MASK);
  285. old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK));
  286. kvmppc_set_msr_fast(vcpu, old_msr);
  287. kvmppc_recalc_shadow_msr(vcpu);
  288. }
  289. #endif
  290. svcpu->in_use = false;
  291. out:
  292. svcpu_put(svcpu);
  293. }
  294. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  295. void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu)
  296. {
  297. tm_enable();
  298. vcpu->arch.tfhar = mfspr(SPRN_TFHAR);
  299. vcpu->arch.texasr = mfspr(SPRN_TEXASR);
  300. vcpu->arch.tfiar = mfspr(SPRN_TFIAR);
  301. tm_disable();
  302. }
  303. void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu)
  304. {
  305. tm_enable();
  306. mtspr(SPRN_TFHAR, vcpu->arch.tfhar);
  307. mtspr(SPRN_TEXASR, vcpu->arch.texasr);
  308. mtspr(SPRN_TFIAR, vcpu->arch.tfiar);
  309. tm_disable();
  310. }
  311. /* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at
  312. * hardware.
  313. */
  314. static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu)
  315. {
  316. ulong exit_nr;
  317. ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) &
  318. (MSR_FP | MSR_VEC | MSR_VSX);
  319. if (!ext_diff)
  320. return;
  321. if (ext_diff == MSR_FP)
  322. exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL;
  323. else if (ext_diff == MSR_VEC)
  324. exit_nr = BOOK3S_INTERRUPT_ALTIVEC;
  325. else
  326. exit_nr = BOOK3S_INTERRUPT_VSX;
  327. kvmppc_handle_ext(vcpu, exit_nr, ext_diff);
  328. }
  329. void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu)
  330. {
  331. if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) {
  332. kvmppc_save_tm_sprs(vcpu);
  333. return;
  334. }
  335. kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
  336. kvmppc_giveup_ext(vcpu, MSR_VSX);
  337. preempt_disable();
  338. _kvmppc_save_tm_pr(vcpu, mfmsr());
  339. preempt_enable();
  340. }
  341. void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu)
  342. {
  343. if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) {
  344. kvmppc_restore_tm_sprs(vcpu);
  345. if (kvmppc_get_msr(vcpu) & MSR_TM) {
  346. kvmppc_handle_lost_math_exts(vcpu);
  347. if (vcpu->arch.fscr & FSCR_TAR)
  348. kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
  349. }
  350. return;
  351. }
  352. preempt_disable();
  353. _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu));
  354. preempt_enable();
  355. if (kvmppc_get_msr(vcpu) & MSR_TM) {
  356. kvmppc_handle_lost_math_exts(vcpu);
  357. if (vcpu->arch.fscr & FSCR_TAR)
  358. kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
  359. }
  360. }
  361. #endif
  362. static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu)
  363. {
  364. int r = 1; /* Indicate we want to get back into the guest */
  365. /* We misuse TLB_FLUSH to indicate that we want to clear
  366. all shadow cache entries */
  367. if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
  368. kvmppc_mmu_pte_flush(vcpu, 0, 0);
  369. return r;
  370. }
  371. /************* MMU Notifiers *************/
  372. static void do_kvm_unmap_hva(struct kvm *kvm, unsigned long start,
  373. unsigned long end)
  374. {
  375. long i;
  376. struct kvm_vcpu *vcpu;
  377. struct kvm_memslots *slots;
  378. struct kvm_memory_slot *memslot;
  379. slots = kvm_memslots(kvm);
  380. kvm_for_each_memslot(memslot, slots) {
  381. unsigned long hva_start, hva_end;
  382. gfn_t gfn, gfn_end;
  383. hva_start = max(start, memslot->userspace_addr);
  384. hva_end = min(end, memslot->userspace_addr +
  385. (memslot->npages << PAGE_SHIFT));
  386. if (hva_start >= hva_end)
  387. continue;
  388. /*
  389. * {gfn(page) | page intersects with [hva_start, hva_end)} =
  390. * {gfn, gfn+1, ..., gfn_end-1}.
  391. */
  392. gfn = hva_to_gfn_memslot(hva_start, memslot);
  393. gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
  394. kvm_for_each_vcpu(i, vcpu, kvm)
  395. kvmppc_mmu_pte_pflush(vcpu, gfn << PAGE_SHIFT,
  396. gfn_end << PAGE_SHIFT);
  397. }
  398. }
  399. static int kvm_unmap_hva_range_pr(struct kvm *kvm, unsigned long start,
  400. unsigned long end)
  401. {
  402. do_kvm_unmap_hva(kvm, start, end);
  403. return 0;
  404. }
  405. static int kvm_age_hva_pr(struct kvm *kvm, unsigned long start,
  406. unsigned long end)
  407. {
  408. /* XXX could be more clever ;) */
  409. return 0;
  410. }
  411. static int kvm_test_age_hva_pr(struct kvm *kvm, unsigned long hva)
  412. {
  413. /* XXX could be more clever ;) */
  414. return 0;
  415. }
  416. static void kvm_set_spte_hva_pr(struct kvm *kvm, unsigned long hva, pte_t pte)
  417. {
  418. /* The page will get remapped properly on its next fault */
  419. do_kvm_unmap_hva(kvm, hva, hva + PAGE_SIZE);
  420. }
  421. /*****************************************/
  422. static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr)
  423. {
  424. ulong old_msr;
  425. /* For PAPR guest, make sure MSR reflects guest mode */
  426. if (vcpu->arch.papr_enabled)
  427. msr = (msr & ~MSR_HV) | MSR_ME;
  428. #ifdef EXIT_DEBUG
  429. printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr);
  430. #endif
  431. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  432. /* We should never target guest MSR to TS=10 && PR=0,
  433. * since we always fail transaction for guest privilege
  434. * state.
  435. */
  436. if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr))
  437. kvmppc_emulate_tabort(vcpu,
  438. TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT);
  439. #endif
  440. old_msr = kvmppc_get_msr(vcpu);
  441. msr &= to_book3s(vcpu)->msr_mask;
  442. kvmppc_set_msr_fast(vcpu, msr);
  443. kvmppc_recalc_shadow_msr(vcpu);
  444. if (msr & MSR_POW) {
  445. if (!vcpu->arch.pending_exceptions) {
  446. kvm_vcpu_block(vcpu);
  447. kvm_clear_request(KVM_REQ_UNHALT, vcpu);
  448. vcpu->stat.halt_wakeup++;
  449. /* Unset POW bit after we woke up */
  450. msr &= ~MSR_POW;
  451. kvmppc_set_msr_fast(vcpu, msr);
  452. }
  453. }
  454. if (kvmppc_is_split_real(vcpu))
  455. kvmppc_fixup_split_real(vcpu);
  456. else
  457. kvmppc_unfixup_split_real(vcpu);
  458. if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) !=
  459. (old_msr & (MSR_PR|MSR_IR|MSR_DR))) {
  460. kvmppc_mmu_flush_segments(vcpu);
  461. kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
  462. /* Preload magic page segment when in kernel mode */
  463. if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) {
  464. struct kvm_vcpu_arch *a = &vcpu->arch;
  465. if (msr & MSR_DR)
  466. kvmppc_mmu_map_segment(vcpu, a->magic_page_ea);
  467. else
  468. kvmppc_mmu_map_segment(vcpu, a->magic_page_pa);
  469. }
  470. }
  471. /*
  472. * When switching from 32 to 64-bit, we may have a stale 32-bit
  473. * magic page around, we need to flush it. Typically 32-bit magic
  474. * page will be instantiated when calling into RTAS. Note: We
  475. * assume that such transition only happens while in kernel mode,
  476. * ie, we never transition from user 32-bit to kernel 64-bit with
  477. * a 32-bit magic page around.
  478. */
  479. if (vcpu->arch.magic_page_pa &&
  480. !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) {
  481. /* going from RTAS to normal kernel code */
  482. kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa,
  483. ~0xFFFUL);
  484. }
  485. /* Preload FPU if it's enabled */
  486. if (kvmppc_get_msr(vcpu) & MSR_FP)
  487. kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
  488. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  489. if (kvmppc_get_msr(vcpu) & MSR_TM)
  490. kvmppc_handle_lost_math_exts(vcpu);
  491. #endif
  492. }
  493. static void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr)
  494. {
  495. u32 host_pvr;
  496. vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB;
  497. vcpu->arch.pvr = pvr;
  498. #ifdef CONFIG_PPC_BOOK3S_64
  499. if ((pvr >= 0x330000) && (pvr < 0x70330000)) {
  500. kvmppc_mmu_book3s_64_init(vcpu);
  501. if (!to_book3s(vcpu)->hior_explicit)
  502. to_book3s(vcpu)->hior = 0xfff00000;
  503. to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL;
  504. vcpu->arch.cpu_type = KVM_CPU_3S_64;
  505. } else
  506. #endif
  507. {
  508. kvmppc_mmu_book3s_32_init(vcpu);
  509. if (!to_book3s(vcpu)->hior_explicit)
  510. to_book3s(vcpu)->hior = 0;
  511. to_book3s(vcpu)->msr_mask = 0xffffffffULL;
  512. vcpu->arch.cpu_type = KVM_CPU_3S_32;
  513. }
  514. kvmppc_sanity_check(vcpu);
  515. /* If we are in hypervisor level on 970, we can tell the CPU to
  516. * treat DCBZ as 32 bytes store */
  517. vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32;
  518. if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) &&
  519. !strcmp(cur_cpu_spec->platform, "ppc970"))
  520. vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
  521. /* Cell performs badly if MSR_FEx are set. So let's hope nobody
  522. really needs them in a VM on Cell and force disable them. */
  523. if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be"))
  524. to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1);
  525. /*
  526. * If they're asking for POWER6 or later, set the flag
  527. * indicating that we can do multiple large page sizes
  528. * and 1TB segments.
  529. * Also set the flag that indicates that tlbie has the large
  530. * page bit in the RB operand instead of the instruction.
  531. */
  532. switch (PVR_VER(pvr)) {
  533. case PVR_POWER6:
  534. case PVR_POWER7:
  535. case PVR_POWER7p:
  536. case PVR_POWER8:
  537. case PVR_POWER8E:
  538. case PVR_POWER8NVL:
  539. case PVR_POWER9:
  540. vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE |
  541. BOOK3S_HFLAG_NEW_TLBIE;
  542. break;
  543. }
  544. #ifdef CONFIG_PPC_BOOK3S_32
  545. /* 32 bit Book3S always has 32 byte dcbz */
  546. vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
  547. #endif
  548. /* On some CPUs we can execute paired single operations natively */
  549. asm ( "mfpvr %0" : "=r"(host_pvr));
  550. switch (host_pvr) {
  551. case 0x00080200: /* lonestar 2.0 */
  552. case 0x00088202: /* lonestar 2.2 */
  553. case 0x70000100: /* gekko 1.0 */
  554. case 0x00080100: /* gekko 2.0 */
  555. case 0x00083203: /* gekko 2.3a */
  556. case 0x00083213: /* gekko 2.3b */
  557. case 0x00083204: /* gekko 2.4 */
  558. case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
  559. case 0x00087200: /* broadway */
  560. vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS;
  561. /* Enable HID2.PSE - in case we need it later */
  562. mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29));
  563. }
  564. }
  565. /* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To
  566. * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to
  567. * emulate 32 bytes dcbz length.
  568. *
  569. * The Book3s_64 inventors also realized this case and implemented a special bit
  570. * in the HID5 register, which is a hypervisor ressource. Thus we can't use it.
  571. *
  572. * My approach here is to patch the dcbz instruction on executing pages.
  573. */
  574. static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte)
  575. {
  576. struct page *hpage;
  577. u64 hpage_offset;
  578. u32 *page;
  579. int i;
  580. hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT);
  581. if (is_error_page(hpage))
  582. return;
  583. hpage_offset = pte->raddr & ~PAGE_MASK;
  584. hpage_offset &= ~0xFFFULL;
  585. hpage_offset /= 4;
  586. get_page(hpage);
  587. page = kmap_atomic(hpage);
  588. /* patch dcbz into reserved instruction, so we trap */
  589. for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++)
  590. if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ)
  591. page[i] &= cpu_to_be32(0xfffffff7);
  592. kunmap_atomic(page);
  593. put_page(hpage);
  594. }
  595. static bool kvmppc_visible_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
  596. {
  597. ulong mp_pa = vcpu->arch.magic_page_pa;
  598. if (!(kvmppc_get_msr(vcpu) & MSR_SF))
  599. mp_pa = (uint32_t)mp_pa;
  600. gpa &= ~0xFFFULL;
  601. if (unlikely(mp_pa) && unlikely((mp_pa & KVM_PAM) == (gpa & KVM_PAM))) {
  602. return true;
  603. }
  604. return kvm_is_visible_gfn(vcpu->kvm, gpa >> PAGE_SHIFT);
  605. }
  606. static int kvmppc_handle_pagefault(struct kvm_vcpu *vcpu,
  607. ulong eaddr, int vec)
  608. {
  609. bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE);
  610. bool iswrite = false;
  611. int r = RESUME_GUEST;
  612. int relocated;
  613. int page_found = 0;
  614. struct kvmppc_pte pte = { 0 };
  615. bool dr = (kvmppc_get_msr(vcpu) & MSR_DR) ? true : false;
  616. bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false;
  617. u64 vsid;
  618. relocated = data ? dr : ir;
  619. if (data && (vcpu->arch.fault_dsisr & DSISR_ISSTORE))
  620. iswrite = true;
  621. /* Resolve real address if translation turned on */
  622. if (relocated) {
  623. page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data, iswrite);
  624. } else {
  625. pte.may_execute = true;
  626. pte.may_read = true;
  627. pte.may_write = true;
  628. pte.raddr = eaddr & KVM_PAM;
  629. pte.eaddr = eaddr;
  630. pte.vpage = eaddr >> 12;
  631. pte.page_size = MMU_PAGE_64K;
  632. pte.wimg = HPTE_R_M;
  633. }
  634. switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) {
  635. case 0:
  636. pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12));
  637. break;
  638. case MSR_DR:
  639. if (!data &&
  640. (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) &&
  641. ((pte.raddr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS))
  642. pte.raddr &= ~SPLIT_HACK_MASK;
  643. fallthrough;
  644. case MSR_IR:
  645. vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid);
  646. if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR)
  647. pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12));
  648. else
  649. pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12));
  650. pte.vpage |= vsid;
  651. if (vsid == -1)
  652. page_found = -EINVAL;
  653. break;
  654. }
  655. if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
  656. (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
  657. /*
  658. * If we do the dcbz hack, we have to NX on every execution,
  659. * so we can patch the executing code. This renders our guest
  660. * NX-less.
  661. */
  662. pte.may_execute = !data;
  663. }
  664. if (page_found == -ENOENT || page_found == -EPERM) {
  665. /* Page not found in guest PTE entries, or protection fault */
  666. u64 flags;
  667. if (page_found == -EPERM)
  668. flags = DSISR_PROTFAULT;
  669. else
  670. flags = DSISR_NOHPTE;
  671. if (data) {
  672. flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE;
  673. kvmppc_core_queue_data_storage(vcpu, eaddr, flags);
  674. } else {
  675. kvmppc_core_queue_inst_storage(vcpu, flags);
  676. }
  677. } else if (page_found == -EINVAL) {
  678. /* Page not found in guest SLB */
  679. kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
  680. kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80);
  681. } else if (kvmppc_visible_gpa(vcpu, pte.raddr)) {
  682. if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) {
  683. /*
  684. * There is already a host HPTE there, presumably
  685. * a read-only one for a page the guest thinks
  686. * is writable, so get rid of it first.
  687. */
  688. kvmppc_mmu_unmap_page(vcpu, &pte);
  689. }
  690. /* The guest's PTE is not mapped yet. Map on the host */
  691. if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) {
  692. /* Exit KVM if mapping failed */
  693. vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
  694. return RESUME_HOST;
  695. }
  696. if (data)
  697. vcpu->stat.sp_storage++;
  698. else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
  699. (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32)))
  700. kvmppc_patch_dcbz(vcpu, &pte);
  701. } else {
  702. /* MMIO */
  703. vcpu->stat.mmio_exits++;
  704. vcpu->arch.paddr_accessed = pte.raddr;
  705. vcpu->arch.vaddr_accessed = pte.eaddr;
  706. r = kvmppc_emulate_mmio(vcpu);
  707. if ( r == RESUME_HOST_NV )
  708. r = RESUME_HOST;
  709. }
  710. return r;
  711. }
  712. /* Give up external provider (FPU, Altivec, VSX) */
  713. void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr)
  714. {
  715. struct thread_struct *t = &current->thread;
  716. /*
  717. * VSX instructions can access FP and vector registers, so if
  718. * we are giving up VSX, make sure we give up FP and VMX as well.
  719. */
  720. if (msr & MSR_VSX)
  721. msr |= MSR_FP | MSR_VEC;
  722. msr &= vcpu->arch.guest_owned_ext;
  723. if (!msr)
  724. return;
  725. #ifdef DEBUG_EXT
  726. printk(KERN_INFO "Giving up ext 0x%lx\n", msr);
  727. #endif
  728. if (msr & MSR_FP) {
  729. /*
  730. * Note that on CPUs with VSX, giveup_fpu stores
  731. * both the traditional FP registers and the added VSX
  732. * registers into thread.fp_state.fpr[].
  733. */
  734. if (t->regs->msr & MSR_FP)
  735. giveup_fpu(current);
  736. t->fp_save_area = NULL;
  737. }
  738. #ifdef CONFIG_ALTIVEC
  739. if (msr & MSR_VEC) {
  740. if (current->thread.regs->msr & MSR_VEC)
  741. giveup_altivec(current);
  742. t->vr_save_area = NULL;
  743. }
  744. #endif
  745. vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX);
  746. kvmppc_recalc_shadow_msr(vcpu);
  747. }
  748. /* Give up facility (TAR / EBB / DSCR) */
  749. void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac)
  750. {
  751. #ifdef CONFIG_PPC_BOOK3S_64
  752. if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) {
  753. /* Facility not available to the guest, ignore giveup request*/
  754. return;
  755. }
  756. switch (fac) {
  757. case FSCR_TAR_LG:
  758. vcpu->arch.tar = mfspr(SPRN_TAR);
  759. mtspr(SPRN_TAR, current->thread.tar);
  760. vcpu->arch.shadow_fscr &= ~FSCR_TAR;
  761. break;
  762. }
  763. #endif
  764. }
  765. /* Handle external providers (FPU, Altivec, VSX) */
  766. static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
  767. ulong msr)
  768. {
  769. struct thread_struct *t = &current->thread;
  770. /* When we have paired singles, we emulate in software */
  771. if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)
  772. return RESUME_GUEST;
  773. if (!(kvmppc_get_msr(vcpu) & msr)) {
  774. kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
  775. return RESUME_GUEST;
  776. }
  777. if (msr == MSR_VSX) {
  778. /* No VSX? Give an illegal instruction interrupt */
  779. #ifdef CONFIG_VSX
  780. if (!cpu_has_feature(CPU_FTR_VSX))
  781. #endif
  782. {
  783. kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
  784. return RESUME_GUEST;
  785. }
  786. /*
  787. * We have to load up all the FP and VMX registers before
  788. * we can let the guest use VSX instructions.
  789. */
  790. msr = MSR_FP | MSR_VEC | MSR_VSX;
  791. }
  792. /* See if we already own all the ext(s) needed */
  793. msr &= ~vcpu->arch.guest_owned_ext;
  794. if (!msr)
  795. return RESUME_GUEST;
  796. #ifdef DEBUG_EXT
  797. printk(KERN_INFO "Loading up ext 0x%lx\n", msr);
  798. #endif
  799. if (msr & MSR_FP) {
  800. preempt_disable();
  801. enable_kernel_fp();
  802. load_fp_state(&vcpu->arch.fp);
  803. disable_kernel_fp();
  804. t->fp_save_area = &vcpu->arch.fp;
  805. preempt_enable();
  806. }
  807. if (msr & MSR_VEC) {
  808. #ifdef CONFIG_ALTIVEC
  809. preempt_disable();
  810. enable_kernel_altivec();
  811. load_vr_state(&vcpu->arch.vr);
  812. disable_kernel_altivec();
  813. t->vr_save_area = &vcpu->arch.vr;
  814. preempt_enable();
  815. #endif
  816. }
  817. t->regs->msr |= msr;
  818. vcpu->arch.guest_owned_ext |= msr;
  819. kvmppc_recalc_shadow_msr(vcpu);
  820. return RESUME_GUEST;
  821. }
  822. /*
  823. * Kernel code using FP or VMX could have flushed guest state to
  824. * the thread_struct; if so, get it back now.
  825. */
  826. static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu)
  827. {
  828. unsigned long lost_ext;
  829. lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr;
  830. if (!lost_ext)
  831. return;
  832. if (lost_ext & MSR_FP) {
  833. preempt_disable();
  834. enable_kernel_fp();
  835. load_fp_state(&vcpu->arch.fp);
  836. disable_kernel_fp();
  837. preempt_enable();
  838. }
  839. #ifdef CONFIG_ALTIVEC
  840. if (lost_ext & MSR_VEC) {
  841. preempt_disable();
  842. enable_kernel_altivec();
  843. load_vr_state(&vcpu->arch.vr);
  844. disable_kernel_altivec();
  845. preempt_enable();
  846. }
  847. #endif
  848. current->thread.regs->msr |= lost_ext;
  849. }
  850. #ifdef CONFIG_PPC_BOOK3S_64
  851. void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac)
  852. {
  853. /* Inject the Interrupt Cause field and trigger a guest interrupt */
  854. vcpu->arch.fscr &= ~(0xffULL << 56);
  855. vcpu->arch.fscr |= (fac << 56);
  856. kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL);
  857. }
  858. static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac)
  859. {
  860. enum emulation_result er = EMULATE_FAIL;
  861. if (!(kvmppc_get_msr(vcpu) & MSR_PR))
  862. er = kvmppc_emulate_instruction(vcpu);
  863. if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) {
  864. /* Couldn't emulate, trigger interrupt in guest */
  865. kvmppc_trigger_fac_interrupt(vcpu, fac);
  866. }
  867. }
  868. /* Enable facilities (TAR, EBB, DSCR) for the guest */
  869. static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
  870. {
  871. bool guest_fac_enabled;
  872. BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
  873. /*
  874. * Not every facility is enabled by FSCR bits, check whether the
  875. * guest has this facility enabled at all.
  876. */
  877. switch (fac) {
  878. case FSCR_TAR_LG:
  879. case FSCR_EBB_LG:
  880. guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac));
  881. break;
  882. case FSCR_TM_LG:
  883. guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM;
  884. break;
  885. default:
  886. guest_fac_enabled = false;
  887. break;
  888. }
  889. if (!guest_fac_enabled) {
  890. /* Facility not enabled by the guest */
  891. kvmppc_trigger_fac_interrupt(vcpu, fac);
  892. return RESUME_GUEST;
  893. }
  894. switch (fac) {
  895. case FSCR_TAR_LG:
  896. /* TAR switching isn't lazy in Linux yet */
  897. current->thread.tar = mfspr(SPRN_TAR);
  898. mtspr(SPRN_TAR, vcpu->arch.tar);
  899. vcpu->arch.shadow_fscr |= FSCR_TAR;
  900. break;
  901. default:
  902. kvmppc_emulate_fac(vcpu, fac);
  903. break;
  904. }
  905. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  906. /* Since we disabled MSR_TM at privilege state, the mfspr instruction
  907. * for TM spr can trigger TM fac unavailable. In this case, the
  908. * emulation is handled by kvmppc_emulate_fac(), which invokes
  909. * kvmppc_emulate_mfspr() finally. But note the mfspr can include
  910. * RT for NV registers. So it need to restore those NV reg to reflect
  911. * the update.
  912. */
  913. if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR))
  914. return RESUME_GUEST_NV;
  915. #endif
  916. return RESUME_GUEST;
  917. }
  918. void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr)
  919. {
  920. if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) {
  921. /* TAR got dropped, drop it in shadow too */
  922. kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
  923. } else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) {
  924. vcpu->arch.fscr = fscr;
  925. kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
  926. return;
  927. }
  928. vcpu->arch.fscr = fscr;
  929. }
  930. #endif
  931. static void kvmppc_setup_debug(struct kvm_vcpu *vcpu)
  932. {
  933. if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
  934. u64 msr = kvmppc_get_msr(vcpu);
  935. kvmppc_set_msr(vcpu, msr | MSR_SE);
  936. }
  937. }
  938. static void kvmppc_clear_debug(struct kvm_vcpu *vcpu)
  939. {
  940. if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
  941. u64 msr = kvmppc_get_msr(vcpu);
  942. kvmppc_set_msr(vcpu, msr & ~MSR_SE);
  943. }
  944. }
  945. static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr)
  946. {
  947. enum emulation_result er;
  948. ulong flags;
  949. u32 last_inst;
  950. int emul, r;
  951. /*
  952. * shadow_srr1 only contains valid flags if we came here via a program
  953. * exception. The other exceptions (emulation assist, FP unavailable,
  954. * etc.) do not provide flags in SRR1, so use an illegal-instruction
  955. * exception when injecting a program interrupt into the guest.
  956. */
  957. if (exit_nr == BOOK3S_INTERRUPT_PROGRAM)
  958. flags = vcpu->arch.shadow_srr1 & 0x1f0000ull;
  959. else
  960. flags = SRR1_PROGILL;
  961. emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
  962. if (emul != EMULATE_DONE)
  963. return RESUME_GUEST;
  964. if (kvmppc_get_msr(vcpu) & MSR_PR) {
  965. #ifdef EXIT_DEBUG
  966. pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n",
  967. kvmppc_get_pc(vcpu), last_inst);
  968. #endif
  969. if ((last_inst & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) {
  970. kvmppc_core_queue_program(vcpu, flags);
  971. return RESUME_GUEST;
  972. }
  973. }
  974. vcpu->stat.emulated_inst_exits++;
  975. er = kvmppc_emulate_instruction(vcpu);
  976. switch (er) {
  977. case EMULATE_DONE:
  978. r = RESUME_GUEST_NV;
  979. break;
  980. case EMULATE_AGAIN:
  981. r = RESUME_GUEST;
  982. break;
  983. case EMULATE_FAIL:
  984. pr_crit("%s: emulation at %lx failed (%08x)\n",
  985. __func__, kvmppc_get_pc(vcpu), last_inst);
  986. kvmppc_core_queue_program(vcpu, flags);
  987. r = RESUME_GUEST;
  988. break;
  989. case EMULATE_DO_MMIO:
  990. vcpu->run->exit_reason = KVM_EXIT_MMIO;
  991. r = RESUME_HOST_NV;
  992. break;
  993. case EMULATE_EXIT_USER:
  994. r = RESUME_HOST_NV;
  995. break;
  996. default:
  997. BUG();
  998. }
  999. return r;
  1000. }
  1001. int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
  1002. {
  1003. struct kvm_run *run = vcpu->run;
  1004. int r = RESUME_HOST;
  1005. int s;
  1006. vcpu->stat.sum_exits++;
  1007. run->exit_reason = KVM_EXIT_UNKNOWN;
  1008. run->ready_for_interrupt_injection = 1;
  1009. /* We get here with MSR.EE=1 */
  1010. trace_kvm_exit(exit_nr, vcpu);
  1011. guest_exit();
  1012. switch (exit_nr) {
  1013. case BOOK3S_INTERRUPT_INST_STORAGE:
  1014. {
  1015. ulong shadow_srr1 = vcpu->arch.shadow_srr1;
  1016. vcpu->stat.pf_instruc++;
  1017. if (kvmppc_is_split_real(vcpu))
  1018. kvmppc_fixup_split_real(vcpu);
  1019. #ifdef CONFIG_PPC_BOOK3S_32
  1020. /* We set segments as unused segments when invalidating them. So
  1021. * treat the respective fault as segment fault. */
  1022. {
  1023. struct kvmppc_book3s_shadow_vcpu *svcpu;
  1024. u32 sr;
  1025. svcpu = svcpu_get(vcpu);
  1026. sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT];
  1027. svcpu_put(svcpu);
  1028. if (sr == SR_INVALID) {
  1029. kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
  1030. r = RESUME_GUEST;
  1031. break;
  1032. }
  1033. }
  1034. #endif
  1035. /* only care about PTEG not found errors, but leave NX alone */
  1036. if (shadow_srr1 & 0x40000000) {
  1037. int idx = srcu_read_lock(&vcpu->kvm->srcu);
  1038. r = kvmppc_handle_pagefault(vcpu, kvmppc_get_pc(vcpu), exit_nr);
  1039. srcu_read_unlock(&vcpu->kvm->srcu, idx);
  1040. vcpu->stat.sp_instruc++;
  1041. } else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
  1042. (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
  1043. /*
  1044. * XXX If we do the dcbz hack we use the NX bit to flush&patch the page,
  1045. * so we can't use the NX bit inside the guest. Let's cross our fingers,
  1046. * that no guest that needs the dcbz hack does NX.
  1047. */
  1048. kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL);
  1049. r = RESUME_GUEST;
  1050. } else {
  1051. kvmppc_core_queue_inst_storage(vcpu,
  1052. shadow_srr1 & 0x58000000);
  1053. r = RESUME_GUEST;
  1054. }
  1055. break;
  1056. }
  1057. case BOOK3S_INTERRUPT_DATA_STORAGE:
  1058. {
  1059. ulong dar = kvmppc_get_fault_dar(vcpu);
  1060. u32 fault_dsisr = vcpu->arch.fault_dsisr;
  1061. vcpu->stat.pf_storage++;
  1062. #ifdef CONFIG_PPC_BOOK3S_32
  1063. /* We set segments as unused segments when invalidating them. So
  1064. * treat the respective fault as segment fault. */
  1065. {
  1066. struct kvmppc_book3s_shadow_vcpu *svcpu;
  1067. u32 sr;
  1068. svcpu = svcpu_get(vcpu);
  1069. sr = svcpu->sr[dar >> SID_SHIFT];
  1070. svcpu_put(svcpu);
  1071. if (sr == SR_INVALID) {
  1072. kvmppc_mmu_map_segment(vcpu, dar);
  1073. r = RESUME_GUEST;
  1074. break;
  1075. }
  1076. }
  1077. #endif
  1078. /*
  1079. * We need to handle missing shadow PTEs, and
  1080. * protection faults due to us mapping a page read-only
  1081. * when the guest thinks it is writable.
  1082. */
  1083. if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) {
  1084. int idx = srcu_read_lock(&vcpu->kvm->srcu);
  1085. r = kvmppc_handle_pagefault(vcpu, dar, exit_nr);
  1086. srcu_read_unlock(&vcpu->kvm->srcu, idx);
  1087. } else {
  1088. kvmppc_core_queue_data_storage(vcpu, dar, fault_dsisr);
  1089. r = RESUME_GUEST;
  1090. }
  1091. break;
  1092. }
  1093. case BOOK3S_INTERRUPT_DATA_SEGMENT:
  1094. if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) {
  1095. kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
  1096. kvmppc_book3s_queue_irqprio(vcpu,
  1097. BOOK3S_INTERRUPT_DATA_SEGMENT);
  1098. }
  1099. r = RESUME_GUEST;
  1100. break;
  1101. case BOOK3S_INTERRUPT_INST_SEGMENT:
  1102. if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) {
  1103. kvmppc_book3s_queue_irqprio(vcpu,
  1104. BOOK3S_INTERRUPT_INST_SEGMENT);
  1105. }
  1106. r = RESUME_GUEST;
  1107. break;
  1108. /* We're good on these - the host merely wanted to get our attention */
  1109. case BOOK3S_INTERRUPT_DECREMENTER:
  1110. case BOOK3S_INTERRUPT_HV_DECREMENTER:
  1111. case BOOK3S_INTERRUPT_DOORBELL:
  1112. case BOOK3S_INTERRUPT_H_DOORBELL:
  1113. vcpu->stat.dec_exits++;
  1114. r = RESUME_GUEST;
  1115. break;
  1116. case BOOK3S_INTERRUPT_EXTERNAL:
  1117. case BOOK3S_INTERRUPT_EXTERNAL_HV:
  1118. case BOOK3S_INTERRUPT_H_VIRT:
  1119. vcpu->stat.ext_intr_exits++;
  1120. r = RESUME_GUEST;
  1121. break;
  1122. case BOOK3S_INTERRUPT_HMI:
  1123. case BOOK3S_INTERRUPT_PERFMON:
  1124. case BOOK3S_INTERRUPT_SYSTEM_RESET:
  1125. r = RESUME_GUEST;
  1126. break;
  1127. case BOOK3S_INTERRUPT_PROGRAM:
  1128. case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
  1129. r = kvmppc_exit_pr_progint(vcpu, exit_nr);
  1130. break;
  1131. case BOOK3S_INTERRUPT_SYSCALL:
  1132. {
  1133. u32 last_sc;
  1134. int emul;
  1135. /* Get last sc for papr */
  1136. if (vcpu->arch.papr_enabled) {
  1137. /* The sc instuction points SRR0 to the next inst */
  1138. emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc);
  1139. if (emul != EMULATE_DONE) {
  1140. kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4);
  1141. r = RESUME_GUEST;
  1142. break;
  1143. }
  1144. }
  1145. if (vcpu->arch.papr_enabled &&
  1146. (last_sc == 0x44000022) &&
  1147. !(kvmppc_get_msr(vcpu) & MSR_PR)) {
  1148. /* SC 1 papr hypercalls */
  1149. ulong cmd = kvmppc_get_gpr(vcpu, 3);
  1150. int i;
  1151. #ifdef CONFIG_PPC_BOOK3S_64
  1152. if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) {
  1153. r = RESUME_GUEST;
  1154. break;
  1155. }
  1156. #endif
  1157. run->papr_hcall.nr = cmd;
  1158. for (i = 0; i < 9; ++i) {
  1159. ulong gpr = kvmppc_get_gpr(vcpu, 4 + i);
  1160. run->papr_hcall.args[i] = gpr;
  1161. }
  1162. run->exit_reason = KVM_EXIT_PAPR_HCALL;
  1163. vcpu->arch.hcall_needed = 1;
  1164. r = RESUME_HOST;
  1165. } else if (vcpu->arch.osi_enabled &&
  1166. (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) &&
  1167. (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) {
  1168. /* MOL hypercalls */
  1169. u64 *gprs = run->osi.gprs;
  1170. int i;
  1171. run->exit_reason = KVM_EXIT_OSI;
  1172. for (i = 0; i < 32; i++)
  1173. gprs[i] = kvmppc_get_gpr(vcpu, i);
  1174. vcpu->arch.osi_needed = 1;
  1175. r = RESUME_HOST_NV;
  1176. } else if (!(kvmppc_get_msr(vcpu) & MSR_PR) &&
  1177. (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
  1178. /* KVM PV hypercalls */
  1179. kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
  1180. r = RESUME_GUEST;
  1181. } else {
  1182. /* Guest syscalls */
  1183. vcpu->stat.syscall_exits++;
  1184. kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
  1185. r = RESUME_GUEST;
  1186. }
  1187. break;
  1188. }
  1189. case BOOK3S_INTERRUPT_FP_UNAVAIL:
  1190. case BOOK3S_INTERRUPT_ALTIVEC:
  1191. case BOOK3S_INTERRUPT_VSX:
  1192. {
  1193. int ext_msr = 0;
  1194. int emul;
  1195. u32 last_inst;
  1196. if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) {
  1197. /* Do paired single instruction emulation */
  1198. emul = kvmppc_get_last_inst(vcpu, INST_GENERIC,
  1199. &last_inst);
  1200. if (emul == EMULATE_DONE)
  1201. r = kvmppc_exit_pr_progint(vcpu, exit_nr);
  1202. else
  1203. r = RESUME_GUEST;
  1204. break;
  1205. }
  1206. /* Enable external provider */
  1207. switch (exit_nr) {
  1208. case BOOK3S_INTERRUPT_FP_UNAVAIL:
  1209. ext_msr = MSR_FP;
  1210. break;
  1211. case BOOK3S_INTERRUPT_ALTIVEC:
  1212. ext_msr = MSR_VEC;
  1213. break;
  1214. case BOOK3S_INTERRUPT_VSX:
  1215. ext_msr = MSR_VSX;
  1216. break;
  1217. }
  1218. r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr);
  1219. break;
  1220. }
  1221. case BOOK3S_INTERRUPT_ALIGNMENT:
  1222. {
  1223. u32 last_inst;
  1224. int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
  1225. if (emul == EMULATE_DONE) {
  1226. u32 dsisr;
  1227. u64 dar;
  1228. dsisr = kvmppc_alignment_dsisr(vcpu, last_inst);
  1229. dar = kvmppc_alignment_dar(vcpu, last_inst);
  1230. kvmppc_set_dsisr(vcpu, dsisr);
  1231. kvmppc_set_dar(vcpu, dar);
  1232. kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
  1233. }
  1234. r = RESUME_GUEST;
  1235. break;
  1236. }
  1237. #ifdef CONFIG_PPC_BOOK3S_64
  1238. case BOOK3S_INTERRUPT_FAC_UNAVAIL:
  1239. r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56);
  1240. break;
  1241. #endif
  1242. case BOOK3S_INTERRUPT_MACHINE_CHECK:
  1243. kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
  1244. r = RESUME_GUEST;
  1245. break;
  1246. case BOOK3S_INTERRUPT_TRACE:
  1247. if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
  1248. run->exit_reason = KVM_EXIT_DEBUG;
  1249. r = RESUME_HOST;
  1250. } else {
  1251. kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
  1252. r = RESUME_GUEST;
  1253. }
  1254. break;
  1255. default:
  1256. {
  1257. ulong shadow_srr1 = vcpu->arch.shadow_srr1;
  1258. /* Ugh - bork here! What did we get? */
  1259. printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n",
  1260. exit_nr, kvmppc_get_pc(vcpu), shadow_srr1);
  1261. r = RESUME_HOST;
  1262. BUG();
  1263. break;
  1264. }
  1265. }
  1266. if (!(r & RESUME_HOST)) {
  1267. /* To avoid clobbering exit_reason, only check for signals if
  1268. * we aren't already exiting to userspace for some other
  1269. * reason. */
  1270. /*
  1271. * Interrupts could be timers for the guest which we have to
  1272. * inject again, so let's postpone them until we're in the guest
  1273. * and if we really did time things so badly, then we just exit
  1274. * again due to a host external interrupt.
  1275. */
  1276. s = kvmppc_prepare_to_enter(vcpu);
  1277. if (s <= 0)
  1278. r = s;
  1279. else {
  1280. /* interrupts now hard-disabled */
  1281. kvmppc_fix_ee_before_entry();
  1282. }
  1283. kvmppc_handle_lost_ext(vcpu);
  1284. }
  1285. trace_kvm_book3s_reenter(r, vcpu);
  1286. return r;
  1287. }
  1288. static int kvm_arch_vcpu_ioctl_get_sregs_pr(struct kvm_vcpu *vcpu,
  1289. struct kvm_sregs *sregs)
  1290. {
  1291. struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
  1292. int i;
  1293. sregs->pvr = vcpu->arch.pvr;
  1294. sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1;
  1295. if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
  1296. for (i = 0; i < 64; i++) {
  1297. sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i;
  1298. sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv;
  1299. }
  1300. } else {
  1301. for (i = 0; i < 16; i++)
  1302. sregs->u.s.ppc32.sr[i] = kvmppc_get_sr(vcpu, i);
  1303. for (i = 0; i < 8; i++) {
  1304. sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw;
  1305. sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw;
  1306. }
  1307. }
  1308. return 0;
  1309. }
  1310. static int kvm_arch_vcpu_ioctl_set_sregs_pr(struct kvm_vcpu *vcpu,
  1311. struct kvm_sregs *sregs)
  1312. {
  1313. struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
  1314. int i;
  1315. kvmppc_set_pvr_pr(vcpu, sregs->pvr);
  1316. vcpu3s->sdr1 = sregs->u.s.sdr1;
  1317. #ifdef CONFIG_PPC_BOOK3S_64
  1318. if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
  1319. /* Flush all SLB entries */
  1320. vcpu->arch.mmu.slbmte(vcpu, 0, 0);
  1321. vcpu->arch.mmu.slbia(vcpu);
  1322. for (i = 0; i < 64; i++) {
  1323. u64 rb = sregs->u.s.ppc64.slb[i].slbe;
  1324. u64 rs = sregs->u.s.ppc64.slb[i].slbv;
  1325. if (rb & SLB_ESID_V)
  1326. vcpu->arch.mmu.slbmte(vcpu, rs, rb);
  1327. }
  1328. } else
  1329. #endif
  1330. {
  1331. for (i = 0; i < 16; i++) {
  1332. vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]);
  1333. }
  1334. for (i = 0; i < 8; i++) {
  1335. kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false,
  1336. (u32)sregs->u.s.ppc32.ibat[i]);
  1337. kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true,
  1338. (u32)(sregs->u.s.ppc32.ibat[i] >> 32));
  1339. kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false,
  1340. (u32)sregs->u.s.ppc32.dbat[i]);
  1341. kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true,
  1342. (u32)(sregs->u.s.ppc32.dbat[i] >> 32));
  1343. }
  1344. }
  1345. /* Flush the MMU after messing with the segments */
  1346. kvmppc_mmu_pte_flush(vcpu, 0, 0);
  1347. return 0;
  1348. }
  1349. static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id,
  1350. union kvmppc_one_reg *val)
  1351. {
  1352. int r = 0;
  1353. switch (id) {
  1354. case KVM_REG_PPC_DEBUG_INST:
  1355. *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
  1356. break;
  1357. case KVM_REG_PPC_HIOR:
  1358. *val = get_reg_val(id, to_book3s(vcpu)->hior);
  1359. break;
  1360. case KVM_REG_PPC_VTB:
  1361. *val = get_reg_val(id, to_book3s(vcpu)->vtb);
  1362. break;
  1363. case KVM_REG_PPC_LPCR:
  1364. case KVM_REG_PPC_LPCR_64:
  1365. /*
  1366. * We are only interested in the LPCR_ILE bit
  1367. */
  1368. if (vcpu->arch.intr_msr & MSR_LE)
  1369. *val = get_reg_val(id, LPCR_ILE);
  1370. else
  1371. *val = get_reg_val(id, 0);
  1372. break;
  1373. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1374. case KVM_REG_PPC_TFHAR:
  1375. *val = get_reg_val(id, vcpu->arch.tfhar);
  1376. break;
  1377. case KVM_REG_PPC_TFIAR:
  1378. *val = get_reg_val(id, vcpu->arch.tfiar);
  1379. break;
  1380. case KVM_REG_PPC_TEXASR:
  1381. *val = get_reg_val(id, vcpu->arch.texasr);
  1382. break;
  1383. case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
  1384. *val = get_reg_val(id,
  1385. vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]);
  1386. break;
  1387. case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
  1388. {
  1389. int i, j;
  1390. i = id - KVM_REG_PPC_TM_VSR0;
  1391. if (i < 32)
  1392. for (j = 0; j < TS_FPRWIDTH; j++)
  1393. val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j];
  1394. else {
  1395. if (cpu_has_feature(CPU_FTR_ALTIVEC))
  1396. val->vval = vcpu->arch.vr_tm.vr[i-32];
  1397. else
  1398. r = -ENXIO;
  1399. }
  1400. break;
  1401. }
  1402. case KVM_REG_PPC_TM_CR:
  1403. *val = get_reg_val(id, vcpu->arch.cr_tm);
  1404. break;
  1405. case KVM_REG_PPC_TM_XER:
  1406. *val = get_reg_val(id, vcpu->arch.xer_tm);
  1407. break;
  1408. case KVM_REG_PPC_TM_LR:
  1409. *val = get_reg_val(id, vcpu->arch.lr_tm);
  1410. break;
  1411. case KVM_REG_PPC_TM_CTR:
  1412. *val = get_reg_val(id, vcpu->arch.ctr_tm);
  1413. break;
  1414. case KVM_REG_PPC_TM_FPSCR:
  1415. *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr);
  1416. break;
  1417. case KVM_REG_PPC_TM_AMR:
  1418. *val = get_reg_val(id, vcpu->arch.amr_tm);
  1419. break;
  1420. case KVM_REG_PPC_TM_PPR:
  1421. *val = get_reg_val(id, vcpu->arch.ppr_tm);
  1422. break;
  1423. case KVM_REG_PPC_TM_VRSAVE:
  1424. *val = get_reg_val(id, vcpu->arch.vrsave_tm);
  1425. break;
  1426. case KVM_REG_PPC_TM_VSCR:
  1427. if (cpu_has_feature(CPU_FTR_ALTIVEC))
  1428. *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]);
  1429. else
  1430. r = -ENXIO;
  1431. break;
  1432. case KVM_REG_PPC_TM_DSCR:
  1433. *val = get_reg_val(id, vcpu->arch.dscr_tm);
  1434. break;
  1435. case KVM_REG_PPC_TM_TAR:
  1436. *val = get_reg_val(id, vcpu->arch.tar_tm);
  1437. break;
  1438. #endif
  1439. default:
  1440. r = -EINVAL;
  1441. break;
  1442. }
  1443. return r;
  1444. }
  1445. static void kvmppc_set_lpcr_pr(struct kvm_vcpu *vcpu, u64 new_lpcr)
  1446. {
  1447. if (new_lpcr & LPCR_ILE)
  1448. vcpu->arch.intr_msr |= MSR_LE;
  1449. else
  1450. vcpu->arch.intr_msr &= ~MSR_LE;
  1451. }
  1452. static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id,
  1453. union kvmppc_one_reg *val)
  1454. {
  1455. int r = 0;
  1456. switch (id) {
  1457. case KVM_REG_PPC_HIOR:
  1458. to_book3s(vcpu)->hior = set_reg_val(id, *val);
  1459. to_book3s(vcpu)->hior_explicit = true;
  1460. break;
  1461. case KVM_REG_PPC_VTB:
  1462. to_book3s(vcpu)->vtb = set_reg_val(id, *val);
  1463. break;
  1464. case KVM_REG_PPC_LPCR:
  1465. case KVM_REG_PPC_LPCR_64:
  1466. kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val));
  1467. break;
  1468. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1469. case KVM_REG_PPC_TFHAR:
  1470. vcpu->arch.tfhar = set_reg_val(id, *val);
  1471. break;
  1472. case KVM_REG_PPC_TFIAR:
  1473. vcpu->arch.tfiar = set_reg_val(id, *val);
  1474. break;
  1475. case KVM_REG_PPC_TEXASR:
  1476. vcpu->arch.texasr = set_reg_val(id, *val);
  1477. break;
  1478. case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
  1479. vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] =
  1480. set_reg_val(id, *val);
  1481. break;
  1482. case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
  1483. {
  1484. int i, j;
  1485. i = id - KVM_REG_PPC_TM_VSR0;
  1486. if (i < 32)
  1487. for (j = 0; j < TS_FPRWIDTH; j++)
  1488. vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j];
  1489. else
  1490. if (cpu_has_feature(CPU_FTR_ALTIVEC))
  1491. vcpu->arch.vr_tm.vr[i-32] = val->vval;
  1492. else
  1493. r = -ENXIO;
  1494. break;
  1495. }
  1496. case KVM_REG_PPC_TM_CR:
  1497. vcpu->arch.cr_tm = set_reg_val(id, *val);
  1498. break;
  1499. case KVM_REG_PPC_TM_XER:
  1500. vcpu->arch.xer_tm = set_reg_val(id, *val);
  1501. break;
  1502. case KVM_REG_PPC_TM_LR:
  1503. vcpu->arch.lr_tm = set_reg_val(id, *val);
  1504. break;
  1505. case KVM_REG_PPC_TM_CTR:
  1506. vcpu->arch.ctr_tm = set_reg_val(id, *val);
  1507. break;
  1508. case KVM_REG_PPC_TM_FPSCR:
  1509. vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);
  1510. break;
  1511. case KVM_REG_PPC_TM_AMR:
  1512. vcpu->arch.amr_tm = set_reg_val(id, *val);
  1513. break;
  1514. case KVM_REG_PPC_TM_PPR:
  1515. vcpu->arch.ppr_tm = set_reg_val(id, *val);
  1516. break;
  1517. case KVM_REG_PPC_TM_VRSAVE:
  1518. vcpu->arch.vrsave_tm = set_reg_val(id, *val);
  1519. break;
  1520. case KVM_REG_PPC_TM_VSCR:
  1521. if (cpu_has_feature(CPU_FTR_ALTIVEC))
  1522. vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);
  1523. else
  1524. r = -ENXIO;
  1525. break;
  1526. case KVM_REG_PPC_TM_DSCR:
  1527. vcpu->arch.dscr_tm = set_reg_val(id, *val);
  1528. break;
  1529. case KVM_REG_PPC_TM_TAR:
  1530. vcpu->arch.tar_tm = set_reg_val(id, *val);
  1531. break;
  1532. #endif
  1533. default:
  1534. r = -EINVAL;
  1535. break;
  1536. }
  1537. return r;
  1538. }
  1539. static int kvmppc_core_vcpu_create_pr(struct kvm_vcpu *vcpu)
  1540. {
  1541. struct kvmppc_vcpu_book3s *vcpu_book3s;
  1542. unsigned long p;
  1543. int err;
  1544. err = -ENOMEM;
  1545. vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s));
  1546. if (!vcpu_book3s)
  1547. goto out;
  1548. vcpu->arch.book3s = vcpu_book3s;
  1549. #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
  1550. vcpu->arch.shadow_vcpu =
  1551. kzalloc(sizeof(*vcpu->arch.shadow_vcpu), GFP_KERNEL);
  1552. if (!vcpu->arch.shadow_vcpu)
  1553. goto free_vcpu3s;
  1554. #endif
  1555. p = __get_free_page(GFP_KERNEL|__GFP_ZERO);
  1556. if (!p)
  1557. goto free_shadow_vcpu;
  1558. vcpu->arch.shared = (void *)p;
  1559. #ifdef CONFIG_PPC_BOOK3S_64
  1560. /* Always start the shared struct in native endian mode */
  1561. #ifdef __BIG_ENDIAN__
  1562. vcpu->arch.shared_big_endian = true;
  1563. #else
  1564. vcpu->arch.shared_big_endian = false;
  1565. #endif
  1566. /*
  1567. * Default to the same as the host if we're on sufficiently
  1568. * recent machine that we have 1TB segments;
  1569. * otherwise default to PPC970FX.
  1570. */
  1571. vcpu->arch.pvr = 0x3C0301;
  1572. if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
  1573. vcpu->arch.pvr = mfspr(SPRN_PVR);
  1574. vcpu->arch.intr_msr = MSR_SF;
  1575. #else
  1576. /* default to book3s_32 (750) */
  1577. vcpu->arch.pvr = 0x84202;
  1578. vcpu->arch.intr_msr = 0;
  1579. #endif
  1580. kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr);
  1581. vcpu->arch.slb_nr = 64;
  1582. vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE;
  1583. err = kvmppc_mmu_init_pr(vcpu);
  1584. if (err < 0)
  1585. goto free_shared_page;
  1586. return 0;
  1587. free_shared_page:
  1588. free_page((unsigned long)vcpu->arch.shared);
  1589. free_shadow_vcpu:
  1590. #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
  1591. kfree(vcpu->arch.shadow_vcpu);
  1592. free_vcpu3s:
  1593. #endif
  1594. vfree(vcpu_book3s);
  1595. out:
  1596. return err;
  1597. }
  1598. static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu)
  1599. {
  1600. struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
  1601. kvmppc_mmu_destroy_pr(vcpu);
  1602. free_page((unsigned long)vcpu->arch.shared & PAGE_MASK);
  1603. #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
  1604. kfree(vcpu->arch.shadow_vcpu);
  1605. #endif
  1606. vfree(vcpu_book3s);
  1607. }
  1608. static int kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu)
  1609. {
  1610. int ret;
  1611. /* Check if we can run the vcpu at all */
  1612. if (!vcpu->arch.sane) {
  1613. vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
  1614. ret = -EINVAL;
  1615. goto out;
  1616. }
  1617. kvmppc_setup_debug(vcpu);
  1618. /*
  1619. * Interrupts could be timers for the guest which we have to inject
  1620. * again, so let's postpone them until we're in the guest and if we
  1621. * really did time things so badly, then we just exit again due to
  1622. * a host external interrupt.
  1623. */
  1624. ret = kvmppc_prepare_to_enter(vcpu);
  1625. if (ret <= 0)
  1626. goto out;
  1627. /* interrupts now hard-disabled */
  1628. /* Save FPU, Altivec and VSX state */
  1629. giveup_all(current);
  1630. /* Preload FPU if it's enabled */
  1631. if (kvmppc_get_msr(vcpu) & MSR_FP)
  1632. kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
  1633. kvmppc_fix_ee_before_entry();
  1634. ret = __kvmppc_vcpu_run(vcpu);
  1635. kvmppc_clear_debug(vcpu);
  1636. /* No need for guest_exit. It's done in handle_exit.
  1637. We also get here with interrupts enabled. */
  1638. /* Make sure we save the guest FPU/Altivec/VSX state */
  1639. kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
  1640. /* Make sure we save the guest TAR/EBB/DSCR state */
  1641. kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
  1642. out:
  1643. vcpu->mode = OUTSIDE_GUEST_MODE;
  1644. return ret;
  1645. }
  1646. /*
  1647. * Get (and clear) the dirty memory log for a memory slot.
  1648. */
  1649. static int kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm,
  1650. struct kvm_dirty_log *log)
  1651. {
  1652. struct kvm_memory_slot *memslot;
  1653. struct kvm_vcpu *vcpu;
  1654. ulong ga, ga_end;
  1655. int is_dirty = 0;
  1656. int r;
  1657. unsigned long n;
  1658. mutex_lock(&kvm->slots_lock);
  1659. r = kvm_get_dirty_log(kvm, log, &is_dirty, &memslot);
  1660. if (r)
  1661. goto out;
  1662. /* If nothing is dirty, don't bother messing with page tables. */
  1663. if (is_dirty) {
  1664. ga = memslot->base_gfn << PAGE_SHIFT;
  1665. ga_end = ga + (memslot->npages << PAGE_SHIFT);
  1666. kvm_for_each_vcpu(n, vcpu, kvm)
  1667. kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
  1668. n = kvm_dirty_bitmap_bytes(memslot);
  1669. memset(memslot->dirty_bitmap, 0, n);
  1670. }
  1671. r = 0;
  1672. out:
  1673. mutex_unlock(&kvm->slots_lock);
  1674. return r;
  1675. }
  1676. static void kvmppc_core_flush_memslot_pr(struct kvm *kvm,
  1677. struct kvm_memory_slot *memslot)
  1678. {
  1679. return;
  1680. }
  1681. static int kvmppc_core_prepare_memory_region_pr(struct kvm *kvm,
  1682. struct kvm_memory_slot *memslot,
  1683. const struct kvm_userspace_memory_region *mem,
  1684. enum kvm_mr_change change)
  1685. {
  1686. return 0;
  1687. }
  1688. static void kvmppc_core_commit_memory_region_pr(struct kvm *kvm,
  1689. const struct kvm_userspace_memory_region *mem,
  1690. const struct kvm_memory_slot *old,
  1691. const struct kvm_memory_slot *new,
  1692. enum kvm_mr_change change)
  1693. {
  1694. return;
  1695. }
  1696. static void kvmppc_core_free_memslot_pr(struct kvm_memory_slot *slot)
  1697. {
  1698. return;
  1699. }
  1700. #ifdef CONFIG_PPC64
  1701. static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm,
  1702. struct kvm_ppc_smmu_info *info)
  1703. {
  1704. long int i;
  1705. struct kvm_vcpu *vcpu;
  1706. info->flags = 0;
  1707. /* SLB is always 64 entries */
  1708. info->slb_size = 64;
  1709. /* Standard 4k base page size segment */
  1710. info->sps[0].page_shift = 12;
  1711. info->sps[0].slb_enc = 0;
  1712. info->sps[0].enc[0].page_shift = 12;
  1713. info->sps[0].enc[0].pte_enc = 0;
  1714. /*
  1715. * 64k large page size.
  1716. * We only want to put this in if the CPUs we're emulating
  1717. * support it, but unfortunately we don't have a vcpu easily
  1718. * to hand here to test. Just pick the first vcpu, and if
  1719. * that doesn't exist yet, report the minimum capability,
  1720. * i.e., no 64k pages.
  1721. * 1T segment support goes along with 64k pages.
  1722. */
  1723. i = 1;
  1724. vcpu = kvm_get_vcpu(kvm, 0);
  1725. if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) {
  1726. info->flags = KVM_PPC_1T_SEGMENTS;
  1727. info->sps[i].page_shift = 16;
  1728. info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01;
  1729. info->sps[i].enc[0].page_shift = 16;
  1730. info->sps[i].enc[0].pte_enc = 1;
  1731. ++i;
  1732. }
  1733. /* Standard 16M large page size segment */
  1734. info->sps[i].page_shift = 24;
  1735. info->sps[i].slb_enc = SLB_VSID_L;
  1736. info->sps[i].enc[0].page_shift = 24;
  1737. info->sps[i].enc[0].pte_enc = 0;
  1738. return 0;
  1739. }
  1740. static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
  1741. {
  1742. if (!cpu_has_feature(CPU_FTR_ARCH_300))
  1743. return -ENODEV;
  1744. /* Require flags and process table base and size to all be zero. */
  1745. if (cfg->flags || cfg->process_table)
  1746. return -EINVAL;
  1747. return 0;
  1748. }
  1749. #else
  1750. static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm,
  1751. struct kvm_ppc_smmu_info *info)
  1752. {
  1753. /* We should not get called */
  1754. BUG();
  1755. return 0;
  1756. }
  1757. #endif /* CONFIG_PPC64 */
  1758. static unsigned int kvm_global_user_count = 0;
  1759. static DEFINE_SPINLOCK(kvm_global_user_count_lock);
  1760. static int kvmppc_core_init_vm_pr(struct kvm *kvm)
  1761. {
  1762. mutex_init(&kvm->arch.hpt_mutex);
  1763. #ifdef CONFIG_PPC_BOOK3S_64
  1764. /* Start out with the default set of hcalls enabled */
  1765. kvmppc_pr_init_default_hcalls(kvm);
  1766. #endif
  1767. if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
  1768. spin_lock(&kvm_global_user_count_lock);
  1769. if (++kvm_global_user_count == 1)
  1770. pseries_disable_reloc_on_exc();
  1771. spin_unlock(&kvm_global_user_count_lock);
  1772. }
  1773. return 0;
  1774. }
  1775. static void kvmppc_core_destroy_vm_pr(struct kvm *kvm)
  1776. {
  1777. #ifdef CONFIG_PPC64
  1778. WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables));
  1779. #endif
  1780. if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
  1781. spin_lock(&kvm_global_user_count_lock);
  1782. BUG_ON(kvm_global_user_count == 0);
  1783. if (--kvm_global_user_count == 0)
  1784. pseries_enable_reloc_on_exc();
  1785. spin_unlock(&kvm_global_user_count_lock);
  1786. }
  1787. }
  1788. static int kvmppc_core_check_processor_compat_pr(void)
  1789. {
  1790. /*
  1791. * PR KVM can work on POWER9 inside a guest partition
  1792. * running in HPT mode. It can't work if we are using
  1793. * radix translation (because radix provides no way for
  1794. * a process to have unique translations in quadrant 3).
  1795. */
  1796. if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled())
  1797. return -EIO;
  1798. return 0;
  1799. }
  1800. static long kvm_arch_vm_ioctl_pr(struct file *filp,
  1801. unsigned int ioctl, unsigned long arg)
  1802. {
  1803. return -ENOTTY;
  1804. }
  1805. static struct kvmppc_ops kvm_ops_pr = {
  1806. .get_sregs = kvm_arch_vcpu_ioctl_get_sregs_pr,
  1807. .set_sregs = kvm_arch_vcpu_ioctl_set_sregs_pr,
  1808. .get_one_reg = kvmppc_get_one_reg_pr,
  1809. .set_one_reg = kvmppc_set_one_reg_pr,
  1810. .vcpu_load = kvmppc_core_vcpu_load_pr,
  1811. .vcpu_put = kvmppc_core_vcpu_put_pr,
  1812. .inject_interrupt = kvmppc_inject_interrupt_pr,
  1813. .set_msr = kvmppc_set_msr_pr,
  1814. .vcpu_run = kvmppc_vcpu_run_pr,
  1815. .vcpu_create = kvmppc_core_vcpu_create_pr,
  1816. .vcpu_free = kvmppc_core_vcpu_free_pr,
  1817. .check_requests = kvmppc_core_check_requests_pr,
  1818. .get_dirty_log = kvm_vm_ioctl_get_dirty_log_pr,
  1819. .flush_memslot = kvmppc_core_flush_memslot_pr,
  1820. .prepare_memory_region = kvmppc_core_prepare_memory_region_pr,
  1821. .commit_memory_region = kvmppc_core_commit_memory_region_pr,
  1822. .unmap_hva_range = kvm_unmap_hva_range_pr,
  1823. .age_hva = kvm_age_hva_pr,
  1824. .test_age_hva = kvm_test_age_hva_pr,
  1825. .set_spte_hva = kvm_set_spte_hva_pr,
  1826. .free_memslot = kvmppc_core_free_memslot_pr,
  1827. .init_vm = kvmppc_core_init_vm_pr,
  1828. .destroy_vm = kvmppc_core_destroy_vm_pr,
  1829. .get_smmu_info = kvm_vm_ioctl_get_smmu_info_pr,
  1830. .emulate_op = kvmppc_core_emulate_op_pr,
  1831. .emulate_mtspr = kvmppc_core_emulate_mtspr_pr,
  1832. .emulate_mfspr = kvmppc_core_emulate_mfspr_pr,
  1833. .fast_vcpu_kick = kvm_vcpu_kick,
  1834. .arch_vm_ioctl = kvm_arch_vm_ioctl_pr,
  1835. #ifdef CONFIG_PPC_BOOK3S_64
  1836. .hcall_implemented = kvmppc_hcall_impl_pr,
  1837. .configure_mmu = kvm_configure_mmu_pr,
  1838. #endif
  1839. .giveup_ext = kvmppc_giveup_ext,
  1840. };
  1841. int kvmppc_book3s_init_pr(void)
  1842. {
  1843. int r;
  1844. r = kvmppc_core_check_processor_compat_pr();
  1845. if (r < 0)
  1846. return r;
  1847. kvm_ops_pr.owner = THIS_MODULE;
  1848. kvmppc_pr_ops = &kvm_ops_pr;
  1849. r = kvmppc_mmu_hpte_sysinit();
  1850. return r;
  1851. }
  1852. void kvmppc_book3s_exit_pr(void)
  1853. {
  1854. kvmppc_pr_ops = NULL;
  1855. kvmppc_mmu_hpte_sysexit();
  1856. }
  1857. /*
  1858. * We only support separate modules for book3s 64
  1859. */
  1860. #ifdef CONFIG_PPC_BOOK3S_64
  1861. module_init(kvmppc_book3s_init_pr);
  1862. module_exit(kvmppc_book3s_exit_pr);
  1863. MODULE_LICENSE("GPL");
  1864. MODULE_ALIAS_MISCDEV(KVM_MINOR);
  1865. MODULE_ALIAS("devname:kvm");
  1866. #endif