book3s_hv_tm_builtin.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2017 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  4. */
  5. #include <linux/kvm_host.h>
  6. #include <asm/kvm_ppc.h>
  7. #include <asm/kvm_book3s.h>
  8. #include <asm/kvm_book3s_64.h>
  9. #include <asm/reg.h>
  10. #include <asm/ppc-opcode.h>
  11. /*
  12. * This handles the cases where the guest is in real suspend mode
  13. * and we want to get back to the guest without dooming the transaction.
  14. * The caller has checked that the guest is in real-suspend mode
  15. * (MSR[TS] = S and the fake-suspend flag is not set).
  16. */
  17. int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu)
  18. {
  19. u32 instr = vcpu->arch.emul_inst;
  20. u64 newmsr, msr, bescr;
  21. int rs;
  22. /*
  23. * rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit
  24. * in these instructions, so masking bit 31 out doesn't change these
  25. * instructions. For the tsr. instruction if bit 31 = 0 then it is per
  26. * ISA an invalid form, however P9 UM, in section 4.6.10 Book II Invalid
  27. * Forms, informs specifically that ignoring bit 31 is an acceptable way
  28. * to handle TM-related invalid forms that have bit 31 = 0. Moreover,
  29. * for emulation purposes both forms (w/ and wo/ bit 31 set) can
  30. * generate a softpatch interrupt. Hence both forms are handled below
  31. * for tsr. to make them behave the same way.
  32. */
  33. switch (instr & PO_XOP_OPCODE_MASK) {
  34. case PPC_INST_RFID:
  35. /* XXX do we need to check for PR=0 here? */
  36. newmsr = vcpu->arch.shregs.srr1;
  37. /* should only get here for Sx -> T1 transition */
  38. if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
  39. return 0;
  40. newmsr = sanitize_msr(newmsr);
  41. vcpu->arch.shregs.msr = newmsr;
  42. vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
  43. vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
  44. return 1;
  45. case PPC_INST_RFEBB:
  46. /* check for PR=1 and arch 2.06 bit set in PCR */
  47. msr = vcpu->arch.shregs.msr;
  48. if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
  49. return 0;
  50. /* check EBB facility is available */
  51. if (!(vcpu->arch.hfscr & HFSCR_EBB) ||
  52. ((msr & MSR_PR) && !(mfspr(SPRN_FSCR) & FSCR_EBB)))
  53. return 0;
  54. bescr = mfspr(SPRN_BESCR);
  55. /* expect to see a S->T transition requested */
  56. if (((bescr >> 30) & 3) != 2)
  57. return 0;
  58. bescr &= ~BESCR_GE;
  59. if (instr & (1 << 11))
  60. bescr |= BESCR_GE;
  61. mtspr(SPRN_BESCR, bescr);
  62. msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
  63. vcpu->arch.shregs.msr = msr;
  64. vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
  65. vcpu->arch.regs.nip = mfspr(SPRN_EBBRR);
  66. return 1;
  67. case PPC_INST_MTMSRD:
  68. /* XXX do we need to check for PR=0 here? */
  69. rs = (instr >> 21) & 0x1f;
  70. newmsr = kvmppc_get_gpr(vcpu, rs);
  71. msr = vcpu->arch.shregs.msr;
  72. /* check this is a Sx -> T1 transition */
  73. if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
  74. return 0;
  75. /* mtmsrd doesn't change LE */
  76. newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
  77. newmsr = sanitize_msr(newmsr);
  78. vcpu->arch.shregs.msr = newmsr;
  79. return 1;
  80. /* ignore bit 31, see comment above */
  81. case (PPC_INST_TSR & PO_XOP_OPCODE_MASK):
  82. /* we know the MSR has the TS field = S (0b01) here */
  83. msr = vcpu->arch.shregs.msr;
  84. /* check for PR=1 and arch 2.06 bit set in PCR */
  85. if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
  86. return 0;
  87. /* check for TM disabled in the HFSCR or MSR */
  88. if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM))
  89. return 0;
  90. /* L=1 => tresume => set TS to T (0b10) */
  91. if (instr & (1 << 21))
  92. vcpu->arch.shregs.msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
  93. /* Set CR0 to 0b0010 */
  94. vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
  95. 0x20000000;
  96. return 1;
  97. }
  98. return 0;
  99. }
  100. /*
  101. * This is called when we are returning to a guest in TM transactional
  102. * state. We roll the guest state back to the checkpointed state.
  103. */
  104. void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu)
  105. {
  106. vcpu->arch.shregs.msr &= ~MSR_TS_MASK; /* go to N state */
  107. vcpu->arch.regs.nip = vcpu->arch.tfhar;
  108. copy_from_checkpoint(vcpu);
  109. vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000;
  110. }