book3s_hv_rm_mmu.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  5. */
  6. #include <linux/types.h>
  7. #include <linux/string.h>
  8. #include <linux/kvm.h>
  9. #include <linux/kvm_host.h>
  10. #include <linux/hugetlb.h>
  11. #include <linux/module.h>
  12. #include <linux/log2.h>
  13. #include <linux/sizes.h>
  14. #include <asm/trace.h>
  15. #include <asm/kvm_ppc.h>
  16. #include <asm/kvm_book3s.h>
  17. #include <asm/book3s/64/mmu-hash.h>
  18. #include <asm/hvcall.h>
  19. #include <asm/synch.h>
  20. #include <asm/ppc-opcode.h>
  21. #include <asm/pte-walk.h>
  22. /* Translate address of a vmalloc'd thing to a linear map address */
  23. static void *real_vmalloc_addr(void *x)
  24. {
  25. unsigned long addr = (unsigned long) x;
  26. pte_t *p;
  27. /*
  28. * assume we don't have huge pages in vmalloc space...
  29. * So don't worry about THP collapse/split. Called
  30. * Only in realmode with MSR_EE = 0, hence won't need irq_save/restore.
  31. */
  32. p = find_init_mm_pte(addr, NULL);
  33. if (!p || !pte_present(*p))
  34. return NULL;
  35. addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
  36. return __va(addr);
  37. }
  38. /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
  39. static int global_invalidates(struct kvm *kvm)
  40. {
  41. int global;
  42. int cpu;
  43. /*
  44. * If there is only one vcore, and it's currently running,
  45. * as indicated by local_paca->kvm_hstate.kvm_vcpu being set,
  46. * we can use tlbiel as long as we mark all other physical
  47. * cores as potentially having stale TLB entries for this lpid.
  48. * Otherwise, don't use tlbiel.
  49. */
  50. if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu)
  51. global = 0;
  52. else
  53. global = 1;
  54. if (!global) {
  55. /* any other core might now have stale TLB entries... */
  56. smp_wmb();
  57. cpumask_setall(&kvm->arch.need_tlb_flush);
  58. cpu = local_paca->kvm_hstate.kvm_vcore->pcpu;
  59. /*
  60. * On POWER9, threads are independent but the TLB is shared,
  61. * so use the bit for the first thread to represent the core.
  62. */
  63. if (cpu_has_feature(CPU_FTR_ARCH_300))
  64. cpu = cpu_first_tlb_thread_sibling(cpu);
  65. cpumask_clear_cpu(cpu, &kvm->arch.need_tlb_flush);
  66. }
  67. return global;
  68. }
  69. /*
  70. * Add this HPTE into the chain for the real page.
  71. * Must be called with the chain locked; it unlocks the chain.
  72. */
  73. void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
  74. unsigned long *rmap, long pte_index, int realmode)
  75. {
  76. struct revmap_entry *head, *tail;
  77. unsigned long i;
  78. if (*rmap & KVMPPC_RMAP_PRESENT) {
  79. i = *rmap & KVMPPC_RMAP_INDEX;
  80. head = &kvm->arch.hpt.rev[i];
  81. if (realmode)
  82. head = real_vmalloc_addr(head);
  83. tail = &kvm->arch.hpt.rev[head->back];
  84. if (realmode)
  85. tail = real_vmalloc_addr(tail);
  86. rev->forw = i;
  87. rev->back = head->back;
  88. tail->forw = pte_index;
  89. head->back = pte_index;
  90. } else {
  91. rev->forw = rev->back = pte_index;
  92. *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
  93. pte_index | KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_HPT;
  94. }
  95. unlock_rmap(rmap);
  96. }
  97. EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
  98. /* Update the dirty bitmap of a memslot */
  99. void kvmppc_update_dirty_map(const struct kvm_memory_slot *memslot,
  100. unsigned long gfn, unsigned long psize)
  101. {
  102. unsigned long npages;
  103. if (!psize || !memslot->dirty_bitmap)
  104. return;
  105. npages = (psize + PAGE_SIZE - 1) / PAGE_SIZE;
  106. gfn -= memslot->base_gfn;
  107. set_dirty_bits_atomic(memslot->dirty_bitmap, gfn, npages);
  108. }
  109. EXPORT_SYMBOL_GPL(kvmppc_update_dirty_map);
  110. static void kvmppc_set_dirty_from_hpte(struct kvm *kvm,
  111. unsigned long hpte_v, unsigned long hpte_gr)
  112. {
  113. struct kvm_memory_slot *memslot;
  114. unsigned long gfn;
  115. unsigned long psize;
  116. psize = kvmppc_actual_pgsz(hpte_v, hpte_gr);
  117. gfn = hpte_rpn(hpte_gr, psize);
  118. memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
  119. if (memslot && memslot->dirty_bitmap)
  120. kvmppc_update_dirty_map(memslot, gfn, psize);
  121. }
  122. /* Returns a pointer to the revmap entry for the page mapped by a HPTE */
  123. static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v,
  124. unsigned long hpte_gr,
  125. struct kvm_memory_slot **memslotp,
  126. unsigned long *gfnp)
  127. {
  128. struct kvm_memory_slot *memslot;
  129. unsigned long *rmap;
  130. unsigned long gfn;
  131. gfn = hpte_rpn(hpte_gr, kvmppc_actual_pgsz(hpte_v, hpte_gr));
  132. memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
  133. if (memslotp)
  134. *memslotp = memslot;
  135. if (gfnp)
  136. *gfnp = gfn;
  137. if (!memslot)
  138. return NULL;
  139. rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
  140. return rmap;
  141. }
  142. /* Remove this HPTE from the chain for a real page */
  143. static void remove_revmap_chain(struct kvm *kvm, long pte_index,
  144. struct revmap_entry *rev,
  145. unsigned long hpte_v, unsigned long hpte_r)
  146. {
  147. struct revmap_entry *next, *prev;
  148. unsigned long ptel, head;
  149. unsigned long *rmap;
  150. unsigned long rcbits;
  151. struct kvm_memory_slot *memslot;
  152. unsigned long gfn;
  153. rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
  154. ptel = rev->guest_rpte |= rcbits;
  155. rmap = revmap_for_hpte(kvm, hpte_v, ptel, &memslot, &gfn);
  156. if (!rmap)
  157. return;
  158. lock_rmap(rmap);
  159. head = *rmap & KVMPPC_RMAP_INDEX;
  160. next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]);
  161. prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]);
  162. next->back = rev->back;
  163. prev->forw = rev->forw;
  164. if (head == pte_index) {
  165. head = rev->forw;
  166. if (head == pte_index)
  167. *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
  168. else
  169. *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
  170. }
  171. *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
  172. if (rcbits & HPTE_R_C)
  173. kvmppc_update_dirty_map(memslot, gfn,
  174. kvmppc_actual_pgsz(hpte_v, hpte_r));
  175. unlock_rmap(rmap);
  176. }
  177. long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
  178. long pte_index, unsigned long pteh, unsigned long ptel,
  179. pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
  180. {
  181. unsigned long i, pa, gpa, gfn, psize;
  182. unsigned long slot_fn, hva;
  183. __be64 *hpte;
  184. struct revmap_entry *rev;
  185. unsigned long g_ptel;
  186. struct kvm_memory_slot *memslot;
  187. unsigned hpage_shift;
  188. bool is_ci;
  189. unsigned long *rmap;
  190. pte_t *ptep;
  191. unsigned int writing;
  192. unsigned long mmu_seq;
  193. unsigned long rcbits;
  194. if (kvm_is_radix(kvm))
  195. return H_FUNCTION;
  196. psize = kvmppc_actual_pgsz(pteh, ptel);
  197. if (!psize)
  198. return H_PARAMETER;
  199. writing = hpte_is_writable(ptel);
  200. pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
  201. ptel &= ~HPTE_GR_RESERVED;
  202. g_ptel = ptel;
  203. /* used later to detect if we might have been invalidated */
  204. mmu_seq = kvm->mmu_notifier_seq;
  205. smp_rmb();
  206. /* Find the memslot (if any) for this address */
  207. gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
  208. gfn = gpa >> PAGE_SHIFT;
  209. memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
  210. pa = 0;
  211. is_ci = false;
  212. rmap = NULL;
  213. if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
  214. /* Emulated MMIO - mark this with key=31 */
  215. pteh |= HPTE_V_ABSENT;
  216. ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
  217. goto do_insert;
  218. }
  219. /* Check if the requested page fits entirely in the memslot. */
  220. if (!slot_is_aligned(memslot, psize))
  221. return H_PARAMETER;
  222. slot_fn = gfn - memslot->base_gfn;
  223. rmap = &memslot->arch.rmap[slot_fn];
  224. /* Translate to host virtual address */
  225. hva = __gfn_to_hva_memslot(memslot, gfn);
  226. arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
  227. ptep = find_kvm_host_pte(kvm, mmu_seq, hva, &hpage_shift);
  228. if (ptep) {
  229. pte_t pte;
  230. unsigned int host_pte_size;
  231. if (hpage_shift)
  232. host_pte_size = 1ul << hpage_shift;
  233. else
  234. host_pte_size = PAGE_SIZE;
  235. /*
  236. * We should always find the guest page size
  237. * to <= host page size, if host is using hugepage
  238. */
  239. if (host_pte_size < psize) {
  240. arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
  241. return H_PARAMETER;
  242. }
  243. pte = kvmppc_read_update_linux_pte(ptep, writing);
  244. if (pte_present(pte) && !pte_protnone(pte)) {
  245. if (writing && !__pte_write(pte))
  246. /* make the actual HPTE be read-only */
  247. ptel = hpte_make_readonly(ptel);
  248. is_ci = pte_ci(pte);
  249. pa = pte_pfn(pte) << PAGE_SHIFT;
  250. pa |= hva & (host_pte_size - 1);
  251. pa |= gpa & ~PAGE_MASK;
  252. }
  253. }
  254. arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
  255. ptel &= HPTE_R_KEY | HPTE_R_PP0 | (psize-1);
  256. ptel |= pa;
  257. if (pa)
  258. pteh |= HPTE_V_VALID;
  259. else {
  260. pteh |= HPTE_V_ABSENT;
  261. ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
  262. }
  263. /*If we had host pte mapping then Check WIMG */
  264. if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) {
  265. if (is_ci)
  266. return H_PARAMETER;
  267. /*
  268. * Allow guest to map emulated device memory as
  269. * uncacheable, but actually make it cacheable.
  270. */
  271. ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
  272. ptel |= HPTE_R_M;
  273. }
  274. /* Find and lock the HPTEG slot to use */
  275. do_insert:
  276. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  277. return H_PARAMETER;
  278. if (likely((flags & H_EXACT) == 0)) {
  279. pte_index &= ~7UL;
  280. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  281. for (i = 0; i < 8; ++i) {
  282. if ((be64_to_cpu(*hpte) & HPTE_V_VALID) == 0 &&
  283. try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
  284. HPTE_V_ABSENT))
  285. break;
  286. hpte += 2;
  287. }
  288. if (i == 8) {
  289. /*
  290. * Since try_lock_hpte doesn't retry (not even stdcx.
  291. * failures), it could be that there is a free slot
  292. * but we transiently failed to lock it. Try again,
  293. * actually locking each slot and checking it.
  294. */
  295. hpte -= 16;
  296. for (i = 0; i < 8; ++i) {
  297. u64 pte;
  298. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  299. cpu_relax();
  300. pte = be64_to_cpu(hpte[0]);
  301. if (!(pte & (HPTE_V_VALID | HPTE_V_ABSENT)))
  302. break;
  303. __unlock_hpte(hpte, pte);
  304. hpte += 2;
  305. }
  306. if (i == 8)
  307. return H_PTEG_FULL;
  308. }
  309. pte_index += i;
  310. } else {
  311. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  312. if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
  313. HPTE_V_ABSENT)) {
  314. /* Lock the slot and check again */
  315. u64 pte;
  316. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  317. cpu_relax();
  318. pte = be64_to_cpu(hpte[0]);
  319. if (pte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
  320. __unlock_hpte(hpte, pte);
  321. return H_PTEG_FULL;
  322. }
  323. }
  324. }
  325. /* Save away the guest's idea of the second HPTE dword */
  326. rev = &kvm->arch.hpt.rev[pte_index];
  327. if (realmode)
  328. rev = real_vmalloc_addr(rev);
  329. if (rev) {
  330. rev->guest_rpte = g_ptel;
  331. note_hpte_modification(kvm, rev);
  332. }
  333. /* Link HPTE into reverse-map chain */
  334. if (pteh & HPTE_V_VALID) {
  335. if (realmode)
  336. rmap = real_vmalloc_addr(rmap);
  337. lock_rmap(rmap);
  338. /* Check for pending invalidations under the rmap chain lock */
  339. if (mmu_notifier_retry(kvm, mmu_seq)) {
  340. /* inval in progress, write a non-present HPTE */
  341. pteh |= HPTE_V_ABSENT;
  342. pteh &= ~HPTE_V_VALID;
  343. ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
  344. unlock_rmap(rmap);
  345. } else {
  346. kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
  347. realmode);
  348. /* Only set R/C in real HPTE if already set in *rmap */
  349. rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
  350. ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
  351. }
  352. }
  353. /* Convert to new format on P9 */
  354. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  355. ptel = hpte_old_to_new_r(pteh, ptel);
  356. pteh = hpte_old_to_new_v(pteh);
  357. }
  358. hpte[1] = cpu_to_be64(ptel);
  359. /* Write the first HPTE dword, unlocking the HPTE and making it valid */
  360. eieio();
  361. __unlock_hpte(hpte, pteh);
  362. asm volatile("ptesync" : : : "memory");
  363. *pte_idx_ret = pte_index;
  364. return H_SUCCESS;
  365. }
  366. EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
  367. long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
  368. long pte_index, unsigned long pteh, unsigned long ptel)
  369. {
  370. return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
  371. vcpu->arch.pgdir, true,
  372. &vcpu->arch.regs.gpr[4]);
  373. }
  374. #ifdef __BIG_ENDIAN__
  375. #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
  376. #else
  377. #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
  378. #endif
  379. static inline int is_mmio_hpte(unsigned long v, unsigned long r)
  380. {
  381. return ((v & HPTE_V_ABSENT) &&
  382. (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
  383. (HPTE_R_KEY_HI | HPTE_R_KEY_LO));
  384. }
  385. static inline void fixup_tlbie_lpid(unsigned long rb_value, unsigned long lpid)
  386. {
  387. if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
  388. /* Radix flush for a hash guest */
  389. unsigned long rb,rs,prs,r,ric;
  390. rb = PPC_BIT(52); /* IS = 2 */
  391. rs = 0; /* lpid = 0 */
  392. prs = 0; /* partition scoped */
  393. r = 1; /* radix format */
  394. ric = 0; /* RIC_FLSUH_TLB */
  395. /*
  396. * Need the extra ptesync to make sure we don't
  397. * re-order the tlbie
  398. */
  399. asm volatile("ptesync": : :"memory");
  400. asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
  401. : : "r"(rb), "i"(r), "i"(prs),
  402. "i"(ric), "r"(rs) : "memory");
  403. }
  404. if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
  405. asm volatile("ptesync": : :"memory");
  406. asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
  407. "r" (rb_value), "r" (lpid));
  408. }
  409. }
  410. static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
  411. long npages, int global, bool need_sync)
  412. {
  413. long i;
  414. /*
  415. * We use the POWER9 5-operand versions of tlbie and tlbiel here.
  416. * Since we are using RIC=0 PRS=0 R=0, and P7/P8 tlbiel ignores
  417. * the RS field, this is backwards-compatible with P7 and P8.
  418. */
  419. if (global) {
  420. if (need_sync)
  421. asm volatile("ptesync" : : : "memory");
  422. for (i = 0; i < npages; ++i) {
  423. asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
  424. "r" (rbvalues[i]), "r" (kvm->arch.lpid));
  425. }
  426. fixup_tlbie_lpid(rbvalues[i - 1], kvm->arch.lpid);
  427. asm volatile("eieio; tlbsync; ptesync" : : : "memory");
  428. } else {
  429. if (need_sync)
  430. asm volatile("ptesync" : : : "memory");
  431. for (i = 0; i < npages; ++i) {
  432. asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :
  433. "r" (rbvalues[i]), "r" (0));
  434. }
  435. asm volatile("ptesync" : : : "memory");
  436. }
  437. }
  438. long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
  439. unsigned long pte_index, unsigned long avpn,
  440. unsigned long *hpret)
  441. {
  442. __be64 *hpte;
  443. unsigned long v, r, rb;
  444. struct revmap_entry *rev;
  445. u64 pte, orig_pte, pte_r;
  446. if (kvm_is_radix(kvm))
  447. return H_FUNCTION;
  448. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  449. return H_PARAMETER;
  450. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  451. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  452. cpu_relax();
  453. pte = orig_pte = be64_to_cpu(hpte[0]);
  454. pte_r = be64_to_cpu(hpte[1]);
  455. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  456. pte = hpte_new_to_old_v(pte, pte_r);
  457. pte_r = hpte_new_to_old_r(pte_r);
  458. }
  459. if ((pte & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
  460. ((flags & H_AVPN) && (pte & ~0x7fUL) != avpn) ||
  461. ((flags & H_ANDCOND) && (pte & avpn) != 0)) {
  462. __unlock_hpte(hpte, orig_pte);
  463. return H_NOT_FOUND;
  464. }
  465. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  466. v = pte & ~HPTE_V_HVLOCK;
  467. if (v & HPTE_V_VALID) {
  468. hpte[0] &= ~cpu_to_be64(HPTE_V_VALID);
  469. rb = compute_tlbie_rb(v, pte_r, pte_index);
  470. do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
  471. /*
  472. * The reference (R) and change (C) bits in a HPT
  473. * entry can be set by hardware at any time up until
  474. * the HPTE is invalidated and the TLB invalidation
  475. * sequence has completed. This means that when
  476. * removing a HPTE, we need to re-read the HPTE after
  477. * the invalidation sequence has completed in order to
  478. * obtain reliable values of R and C.
  479. */
  480. remove_revmap_chain(kvm, pte_index, rev, v,
  481. be64_to_cpu(hpte[1]));
  482. }
  483. r = rev->guest_rpte & ~HPTE_GR_RESERVED;
  484. note_hpte_modification(kvm, rev);
  485. unlock_hpte(hpte, 0);
  486. if (is_mmio_hpte(v, pte_r))
  487. atomic64_inc(&kvm->arch.mmio_update);
  488. if (v & HPTE_V_ABSENT)
  489. v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID;
  490. hpret[0] = v;
  491. hpret[1] = r;
  492. return H_SUCCESS;
  493. }
  494. EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
  495. long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
  496. unsigned long pte_index, unsigned long avpn)
  497. {
  498. return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
  499. &vcpu->arch.regs.gpr[4]);
  500. }
  501. long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
  502. {
  503. struct kvm *kvm = vcpu->kvm;
  504. unsigned long *args = &vcpu->arch.regs.gpr[4];
  505. __be64 *hp, *hptes[4];
  506. unsigned long tlbrb[4];
  507. long int i, j, k, n, found, indexes[4];
  508. unsigned long flags, req, pte_index, rcbits;
  509. int global;
  510. long int ret = H_SUCCESS;
  511. struct revmap_entry *rev, *revs[4];
  512. u64 hp0, hp1;
  513. if (kvm_is_radix(kvm))
  514. return H_FUNCTION;
  515. global = global_invalidates(kvm);
  516. for (i = 0; i < 4 && ret == H_SUCCESS; ) {
  517. n = 0;
  518. for (; i < 4; ++i) {
  519. j = i * 2;
  520. pte_index = args[j];
  521. flags = pte_index >> 56;
  522. pte_index &= ((1ul << 56) - 1);
  523. req = flags >> 6;
  524. flags &= 3;
  525. if (req == 3) { /* no more requests */
  526. i = 4;
  527. break;
  528. }
  529. if (req != 1 || flags == 3 ||
  530. pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) {
  531. /* parameter error */
  532. args[j] = ((0xa0 | flags) << 56) + pte_index;
  533. ret = H_PARAMETER;
  534. break;
  535. }
  536. hp = (__be64 *) (kvm->arch.hpt.virt + (pte_index << 4));
  537. /* to avoid deadlock, don't spin except for first */
  538. if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
  539. if (n)
  540. break;
  541. while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
  542. cpu_relax();
  543. }
  544. found = 0;
  545. hp0 = be64_to_cpu(hp[0]);
  546. hp1 = be64_to_cpu(hp[1]);
  547. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  548. hp0 = hpte_new_to_old_v(hp0, hp1);
  549. hp1 = hpte_new_to_old_r(hp1);
  550. }
  551. if (hp0 & (HPTE_V_ABSENT | HPTE_V_VALID)) {
  552. switch (flags & 3) {
  553. case 0: /* absolute */
  554. found = 1;
  555. break;
  556. case 1: /* andcond */
  557. if (!(hp0 & args[j + 1]))
  558. found = 1;
  559. break;
  560. case 2: /* AVPN */
  561. if ((hp0 & ~0x7fUL) == args[j + 1])
  562. found = 1;
  563. break;
  564. }
  565. }
  566. if (!found) {
  567. hp[0] &= ~cpu_to_be64(HPTE_V_HVLOCK);
  568. args[j] = ((0x90 | flags) << 56) + pte_index;
  569. continue;
  570. }
  571. args[j] = ((0x80 | flags) << 56) + pte_index;
  572. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  573. note_hpte_modification(kvm, rev);
  574. if (!(hp0 & HPTE_V_VALID)) {
  575. /* insert R and C bits from PTE */
  576. rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
  577. args[j] |= rcbits << (56 - 5);
  578. hp[0] = 0;
  579. if (is_mmio_hpte(hp0, hp1))
  580. atomic64_inc(&kvm->arch.mmio_update);
  581. continue;
  582. }
  583. /* leave it locked */
  584. hp[0] &= ~cpu_to_be64(HPTE_V_VALID);
  585. tlbrb[n] = compute_tlbie_rb(hp0, hp1, pte_index);
  586. indexes[n] = j;
  587. hptes[n] = hp;
  588. revs[n] = rev;
  589. ++n;
  590. }
  591. if (!n)
  592. break;
  593. /* Now that we've collected a batch, do the tlbies */
  594. do_tlbies(kvm, tlbrb, n, global, true);
  595. /* Read PTE low words after tlbie to get final R/C values */
  596. for (k = 0; k < n; ++k) {
  597. j = indexes[k];
  598. pte_index = args[j] & ((1ul << 56) - 1);
  599. hp = hptes[k];
  600. rev = revs[k];
  601. remove_revmap_chain(kvm, pte_index, rev,
  602. be64_to_cpu(hp[0]), be64_to_cpu(hp[1]));
  603. rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
  604. args[j] |= rcbits << (56 - 5);
  605. __unlock_hpte(hp, 0);
  606. }
  607. }
  608. return ret;
  609. }
  610. long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
  611. unsigned long pte_index, unsigned long avpn,
  612. unsigned long va)
  613. {
  614. struct kvm *kvm = vcpu->kvm;
  615. __be64 *hpte;
  616. struct revmap_entry *rev;
  617. unsigned long v, r, rb, mask, bits;
  618. u64 pte_v, pte_r;
  619. if (kvm_is_radix(kvm))
  620. return H_FUNCTION;
  621. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  622. return H_PARAMETER;
  623. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  624. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  625. cpu_relax();
  626. v = pte_v = be64_to_cpu(hpte[0]);
  627. if (cpu_has_feature(CPU_FTR_ARCH_300))
  628. v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1]));
  629. if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
  630. ((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) {
  631. __unlock_hpte(hpte, pte_v);
  632. return H_NOT_FOUND;
  633. }
  634. pte_r = be64_to_cpu(hpte[1]);
  635. bits = (flags << 55) & HPTE_R_PP0;
  636. bits |= (flags << 48) & HPTE_R_KEY_HI;
  637. bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
  638. /* Update guest view of 2nd HPTE dword */
  639. mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
  640. HPTE_R_KEY_HI | HPTE_R_KEY_LO;
  641. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  642. if (rev) {
  643. r = (rev->guest_rpte & ~mask) | bits;
  644. rev->guest_rpte = r;
  645. note_hpte_modification(kvm, rev);
  646. }
  647. /* Update HPTE */
  648. if (v & HPTE_V_VALID) {
  649. /*
  650. * If the page is valid, don't let it transition from
  651. * readonly to writable. If it should be writable, we'll
  652. * take a trap and let the page fault code sort it out.
  653. */
  654. r = (pte_r & ~mask) | bits;
  655. if (hpte_is_writable(r) && !hpte_is_writable(pte_r))
  656. r = hpte_make_readonly(r);
  657. /* If the PTE is changing, invalidate it first */
  658. if (r != pte_r) {
  659. rb = compute_tlbie_rb(v, r, pte_index);
  660. hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) |
  661. HPTE_V_ABSENT);
  662. do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
  663. /* Don't lose R/C bit updates done by hardware */
  664. r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C);
  665. hpte[1] = cpu_to_be64(r);
  666. }
  667. }
  668. unlock_hpte(hpte, pte_v & ~HPTE_V_HVLOCK);
  669. asm volatile("ptesync" : : : "memory");
  670. if (is_mmio_hpte(v, pte_r))
  671. atomic64_inc(&kvm->arch.mmio_update);
  672. return H_SUCCESS;
  673. }
  674. long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
  675. unsigned long pte_index)
  676. {
  677. struct kvm *kvm = vcpu->kvm;
  678. __be64 *hpte;
  679. unsigned long v, r;
  680. int i, n = 1;
  681. struct revmap_entry *rev = NULL;
  682. if (kvm_is_radix(kvm))
  683. return H_FUNCTION;
  684. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  685. return H_PARAMETER;
  686. if (flags & H_READ_4) {
  687. pte_index &= ~3;
  688. n = 4;
  689. }
  690. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  691. for (i = 0; i < n; ++i, ++pte_index) {
  692. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  693. v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
  694. r = be64_to_cpu(hpte[1]);
  695. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  696. v = hpte_new_to_old_v(v, r);
  697. r = hpte_new_to_old_r(r);
  698. }
  699. if (v & HPTE_V_ABSENT) {
  700. v &= ~HPTE_V_ABSENT;
  701. v |= HPTE_V_VALID;
  702. }
  703. if (v & HPTE_V_VALID) {
  704. r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
  705. r &= ~HPTE_GR_RESERVED;
  706. }
  707. vcpu->arch.regs.gpr[4 + i * 2] = v;
  708. vcpu->arch.regs.gpr[5 + i * 2] = r;
  709. }
  710. return H_SUCCESS;
  711. }
  712. long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags,
  713. unsigned long pte_index)
  714. {
  715. struct kvm *kvm = vcpu->kvm;
  716. __be64 *hpte;
  717. unsigned long v, r, gr;
  718. struct revmap_entry *rev;
  719. unsigned long *rmap;
  720. long ret = H_NOT_FOUND;
  721. if (kvm_is_radix(kvm))
  722. return H_FUNCTION;
  723. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  724. return H_PARAMETER;
  725. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  726. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  727. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  728. cpu_relax();
  729. v = be64_to_cpu(hpte[0]);
  730. r = be64_to_cpu(hpte[1]);
  731. if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
  732. goto out;
  733. gr = rev->guest_rpte;
  734. if (rev->guest_rpte & HPTE_R_R) {
  735. rev->guest_rpte &= ~HPTE_R_R;
  736. note_hpte_modification(kvm, rev);
  737. }
  738. if (v & HPTE_V_VALID) {
  739. gr |= r & (HPTE_R_R | HPTE_R_C);
  740. if (r & HPTE_R_R) {
  741. kvmppc_clear_ref_hpte(kvm, hpte, pte_index);
  742. rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL);
  743. if (rmap) {
  744. lock_rmap(rmap);
  745. *rmap |= KVMPPC_RMAP_REFERENCED;
  746. unlock_rmap(rmap);
  747. }
  748. }
  749. }
  750. vcpu->arch.regs.gpr[4] = gr;
  751. ret = H_SUCCESS;
  752. out:
  753. unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
  754. return ret;
  755. }
  756. long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags,
  757. unsigned long pte_index)
  758. {
  759. struct kvm *kvm = vcpu->kvm;
  760. __be64 *hpte;
  761. unsigned long v, r, gr;
  762. struct revmap_entry *rev;
  763. long ret = H_NOT_FOUND;
  764. if (kvm_is_radix(kvm))
  765. return H_FUNCTION;
  766. if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
  767. return H_PARAMETER;
  768. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
  769. hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
  770. while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
  771. cpu_relax();
  772. v = be64_to_cpu(hpte[0]);
  773. r = be64_to_cpu(hpte[1]);
  774. if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
  775. goto out;
  776. gr = rev->guest_rpte;
  777. if (gr & HPTE_R_C) {
  778. rev->guest_rpte &= ~HPTE_R_C;
  779. note_hpte_modification(kvm, rev);
  780. }
  781. if (v & HPTE_V_VALID) {
  782. /* need to make it temporarily absent so C is stable */
  783. hpte[0] |= cpu_to_be64(HPTE_V_ABSENT);
  784. kvmppc_invalidate_hpte(kvm, hpte, pte_index);
  785. r = be64_to_cpu(hpte[1]);
  786. gr |= r & (HPTE_R_R | HPTE_R_C);
  787. if (r & HPTE_R_C) {
  788. hpte[1] = cpu_to_be64(r & ~HPTE_R_C);
  789. eieio();
  790. kvmppc_set_dirty_from_hpte(kvm, v, gr);
  791. }
  792. }
  793. vcpu->arch.regs.gpr[4] = gr;
  794. ret = H_SUCCESS;
  795. out:
  796. unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
  797. return ret;
  798. }
  799. static int kvmppc_get_hpa(struct kvm_vcpu *vcpu, unsigned long mmu_seq,
  800. unsigned long gpa, int writing, unsigned long *hpa,
  801. struct kvm_memory_slot **memslot_p)
  802. {
  803. struct kvm *kvm = vcpu->kvm;
  804. struct kvm_memory_slot *memslot;
  805. unsigned long gfn, hva, pa, psize = PAGE_SHIFT;
  806. unsigned int shift;
  807. pte_t *ptep, pte;
  808. /* Find the memslot for this address */
  809. gfn = gpa >> PAGE_SHIFT;
  810. memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
  811. if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
  812. return H_PARAMETER;
  813. /* Translate to host virtual address */
  814. hva = __gfn_to_hva_memslot(memslot, gfn);
  815. /* Try to find the host pte for that virtual address */
  816. ptep = find_kvm_host_pte(kvm, mmu_seq, hva, &shift);
  817. if (!ptep)
  818. return H_TOO_HARD;
  819. pte = kvmppc_read_update_linux_pte(ptep, writing);
  820. if (!pte_present(pte))
  821. return H_TOO_HARD;
  822. /* Convert to a physical address */
  823. if (shift)
  824. psize = 1UL << shift;
  825. pa = pte_pfn(pte) << PAGE_SHIFT;
  826. pa |= hva & (psize - 1);
  827. pa |= gpa & ~PAGE_MASK;
  828. if (hpa)
  829. *hpa = pa;
  830. if (memslot_p)
  831. *memslot_p = memslot;
  832. return H_SUCCESS;
  833. }
  834. static long kvmppc_do_h_page_init_zero(struct kvm_vcpu *vcpu,
  835. unsigned long dest)
  836. {
  837. struct kvm_memory_slot *memslot;
  838. struct kvm *kvm = vcpu->kvm;
  839. unsigned long pa, mmu_seq;
  840. long ret = H_SUCCESS;
  841. int i;
  842. /* Used later to detect if we might have been invalidated */
  843. mmu_seq = kvm->mmu_notifier_seq;
  844. smp_rmb();
  845. arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
  846. ret = kvmppc_get_hpa(vcpu, mmu_seq, dest, 1, &pa, &memslot);
  847. if (ret != H_SUCCESS)
  848. goto out_unlock;
  849. /* Zero the page */
  850. for (i = 0; i < SZ_4K; i += L1_CACHE_BYTES, pa += L1_CACHE_BYTES)
  851. dcbz((void *)pa);
  852. kvmppc_update_dirty_map(memslot, dest >> PAGE_SHIFT, PAGE_SIZE);
  853. out_unlock:
  854. arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
  855. return ret;
  856. }
  857. static long kvmppc_do_h_page_init_copy(struct kvm_vcpu *vcpu,
  858. unsigned long dest, unsigned long src)
  859. {
  860. unsigned long dest_pa, src_pa, mmu_seq;
  861. struct kvm_memory_slot *dest_memslot;
  862. struct kvm *kvm = vcpu->kvm;
  863. long ret = H_SUCCESS;
  864. /* Used later to detect if we might have been invalidated */
  865. mmu_seq = kvm->mmu_notifier_seq;
  866. smp_rmb();
  867. arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
  868. ret = kvmppc_get_hpa(vcpu, mmu_seq, dest, 1, &dest_pa, &dest_memslot);
  869. if (ret != H_SUCCESS)
  870. goto out_unlock;
  871. ret = kvmppc_get_hpa(vcpu, mmu_seq, src, 0, &src_pa, NULL);
  872. if (ret != H_SUCCESS)
  873. goto out_unlock;
  874. /* Copy the page */
  875. memcpy((void *)dest_pa, (void *)src_pa, SZ_4K);
  876. kvmppc_update_dirty_map(dest_memslot, dest >> PAGE_SHIFT, PAGE_SIZE);
  877. out_unlock:
  878. arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
  879. return ret;
  880. }
  881. long kvmppc_rm_h_page_init(struct kvm_vcpu *vcpu, unsigned long flags,
  882. unsigned long dest, unsigned long src)
  883. {
  884. struct kvm *kvm = vcpu->kvm;
  885. u64 pg_mask = SZ_4K - 1; /* 4K page size */
  886. long ret = H_SUCCESS;
  887. /* Don't handle radix mode here, go up to the virtual mode handler */
  888. if (kvm_is_radix(kvm))
  889. return H_TOO_HARD;
  890. /* Check for invalid flags (H_PAGE_SET_LOANED covers all CMO flags) */
  891. if (flags & ~(H_ICACHE_INVALIDATE | H_ICACHE_SYNCHRONIZE |
  892. H_ZERO_PAGE | H_COPY_PAGE | H_PAGE_SET_LOANED))
  893. return H_PARAMETER;
  894. /* dest (and src if copy_page flag set) must be page aligned */
  895. if ((dest & pg_mask) || ((flags & H_COPY_PAGE) && (src & pg_mask)))
  896. return H_PARAMETER;
  897. /* zero and/or copy the page as determined by the flags */
  898. if (flags & H_COPY_PAGE)
  899. ret = kvmppc_do_h_page_init_copy(vcpu, dest, src);
  900. else if (flags & H_ZERO_PAGE)
  901. ret = kvmppc_do_h_page_init_zero(vcpu, dest);
  902. /* We can ignore the other flags */
  903. return ret;
  904. }
  905. void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep,
  906. unsigned long pte_index)
  907. {
  908. unsigned long rb;
  909. u64 hp0, hp1;
  910. hptep[0] &= ~cpu_to_be64(HPTE_V_VALID);
  911. hp0 = be64_to_cpu(hptep[0]);
  912. hp1 = be64_to_cpu(hptep[1]);
  913. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  914. hp0 = hpte_new_to_old_v(hp0, hp1);
  915. hp1 = hpte_new_to_old_r(hp1);
  916. }
  917. rb = compute_tlbie_rb(hp0, hp1, pte_index);
  918. do_tlbies(kvm, &rb, 1, 1, true);
  919. }
  920. EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
  921. void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep,
  922. unsigned long pte_index)
  923. {
  924. unsigned long rb;
  925. unsigned char rbyte;
  926. u64 hp0, hp1;
  927. hp0 = be64_to_cpu(hptep[0]);
  928. hp1 = be64_to_cpu(hptep[1]);
  929. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  930. hp0 = hpte_new_to_old_v(hp0, hp1);
  931. hp1 = hpte_new_to_old_r(hp1);
  932. }
  933. rb = compute_tlbie_rb(hp0, hp1, pte_index);
  934. rbyte = (be64_to_cpu(hptep[1]) & ~HPTE_R_R) >> 8;
  935. /* modify only the second-last byte, which contains the ref bit */
  936. *((char *)hptep + 14) = rbyte;
  937. do_tlbies(kvm, &rb, 1, 1, false);
  938. }
  939. EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
  940. static int slb_base_page_shift[4] = {
  941. 24, /* 16M */
  942. 16, /* 64k */
  943. 34, /* 16G */
  944. 20, /* 1M, unsupported */
  945. };
  946. static struct mmio_hpte_cache_entry *mmio_cache_search(struct kvm_vcpu *vcpu,
  947. unsigned long eaddr, unsigned long slb_v, long mmio_update)
  948. {
  949. struct mmio_hpte_cache_entry *entry = NULL;
  950. unsigned int pshift;
  951. unsigned int i;
  952. for (i = 0; i < MMIO_HPTE_CACHE_SIZE; i++) {
  953. entry = &vcpu->arch.mmio_cache.entry[i];
  954. if (entry->mmio_update == mmio_update) {
  955. pshift = entry->slb_base_pshift;
  956. if ((entry->eaddr >> pshift) == (eaddr >> pshift) &&
  957. entry->slb_v == slb_v)
  958. return entry;
  959. }
  960. }
  961. return NULL;
  962. }
  963. static struct mmio_hpte_cache_entry *
  964. next_mmio_cache_entry(struct kvm_vcpu *vcpu)
  965. {
  966. unsigned int index = vcpu->arch.mmio_cache.index;
  967. vcpu->arch.mmio_cache.index++;
  968. if (vcpu->arch.mmio_cache.index == MMIO_HPTE_CACHE_SIZE)
  969. vcpu->arch.mmio_cache.index = 0;
  970. return &vcpu->arch.mmio_cache.entry[index];
  971. }
  972. /* When called from virtmode, this func should be protected by
  973. * preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK
  974. * can trigger deadlock issue.
  975. */
  976. long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
  977. unsigned long valid)
  978. {
  979. unsigned int i;
  980. unsigned int pshift;
  981. unsigned long somask;
  982. unsigned long vsid, hash;
  983. unsigned long avpn;
  984. __be64 *hpte;
  985. unsigned long mask, val;
  986. unsigned long v, r, orig_v;
  987. /* Get page shift, work out hash and AVPN etc. */
  988. mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
  989. val = 0;
  990. pshift = 12;
  991. if (slb_v & SLB_VSID_L) {
  992. mask |= HPTE_V_LARGE;
  993. val |= HPTE_V_LARGE;
  994. pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
  995. }
  996. if (slb_v & SLB_VSID_B_1T) {
  997. somask = (1UL << 40) - 1;
  998. vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
  999. vsid ^= vsid << 25;
  1000. } else {
  1001. somask = (1UL << 28) - 1;
  1002. vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
  1003. }
  1004. hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvmppc_hpt_mask(&kvm->arch.hpt);
  1005. avpn = slb_v & ~(somask >> 16); /* also includes B */
  1006. avpn |= (eaddr & somask) >> 16;
  1007. if (pshift >= 24)
  1008. avpn &= ~((1UL << (pshift - 16)) - 1);
  1009. else
  1010. avpn &= ~0x7fUL;
  1011. val |= avpn;
  1012. for (;;) {
  1013. hpte = (__be64 *)(kvm->arch.hpt.virt + (hash << 7));
  1014. for (i = 0; i < 16; i += 2) {
  1015. /* Read the PTE racily */
  1016. v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
  1017. if (cpu_has_feature(CPU_FTR_ARCH_300))
  1018. v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1]));
  1019. /* Check valid/absent, hash, segment size and AVPN */
  1020. if (!(v & valid) || (v & mask) != val)
  1021. continue;
  1022. /* Lock the PTE and read it under the lock */
  1023. while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
  1024. cpu_relax();
  1025. v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
  1026. r = be64_to_cpu(hpte[i+1]);
  1027. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  1028. v = hpte_new_to_old_v(v, r);
  1029. r = hpte_new_to_old_r(r);
  1030. }
  1031. /*
  1032. * Check the HPTE again, including base page size
  1033. */
  1034. if ((v & valid) && (v & mask) == val &&
  1035. kvmppc_hpte_base_page_shift(v, r) == pshift)
  1036. /* Return with the HPTE still locked */
  1037. return (hash << 3) + (i >> 1);
  1038. __unlock_hpte(&hpte[i], orig_v);
  1039. }
  1040. if (val & HPTE_V_SECONDARY)
  1041. break;
  1042. val |= HPTE_V_SECONDARY;
  1043. hash = hash ^ kvmppc_hpt_mask(&kvm->arch.hpt);
  1044. }
  1045. return -1;
  1046. }
  1047. EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
  1048. /*
  1049. * Called in real mode to check whether an HPTE not found fault
  1050. * is due to accessing a paged-out page or an emulated MMIO page,
  1051. * or if a protection fault is due to accessing a page that the
  1052. * guest wanted read/write access to but which we made read-only.
  1053. * Returns a possibly modified status (DSISR) value if not
  1054. * (i.e. pass the interrupt to the guest),
  1055. * -1 to pass the fault up to host kernel mode code, -2 to do that
  1056. * and also load the instruction word (for MMIO emulation),
  1057. * or 0 if we should make the guest retry the access.
  1058. */
  1059. long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
  1060. unsigned long slb_v, unsigned int status, bool data)
  1061. {
  1062. struct kvm *kvm = vcpu->kvm;
  1063. long int index;
  1064. unsigned long v, r, gr, orig_v;
  1065. __be64 *hpte;
  1066. unsigned long valid;
  1067. struct revmap_entry *rev;
  1068. unsigned long pp, key;
  1069. struct mmio_hpte_cache_entry *cache_entry = NULL;
  1070. long mmio_update = 0;
  1071. /* For protection fault, expect to find a valid HPTE */
  1072. valid = HPTE_V_VALID;
  1073. if (status & DSISR_NOHPTE) {
  1074. valid |= HPTE_V_ABSENT;
  1075. mmio_update = atomic64_read(&kvm->arch.mmio_update);
  1076. cache_entry = mmio_cache_search(vcpu, addr, slb_v, mmio_update);
  1077. }
  1078. if (cache_entry) {
  1079. index = cache_entry->pte_index;
  1080. v = cache_entry->hpte_v;
  1081. r = cache_entry->hpte_r;
  1082. gr = cache_entry->rpte;
  1083. } else {
  1084. index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
  1085. if (index < 0) {
  1086. if (status & DSISR_NOHPTE)
  1087. return status; /* there really was no HPTE */
  1088. return 0; /* for prot fault, HPTE disappeared */
  1089. }
  1090. hpte = (__be64 *)(kvm->arch.hpt.virt + (index << 4));
  1091. v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
  1092. r = be64_to_cpu(hpte[1]);
  1093. if (cpu_has_feature(CPU_FTR_ARCH_300)) {
  1094. v = hpte_new_to_old_v(v, r);
  1095. r = hpte_new_to_old_r(r);
  1096. }
  1097. rev = real_vmalloc_addr(&kvm->arch.hpt.rev[index]);
  1098. gr = rev->guest_rpte;
  1099. unlock_hpte(hpte, orig_v);
  1100. }
  1101. /* For not found, if the HPTE is valid by now, retry the instruction */
  1102. if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
  1103. return 0;
  1104. /* Check access permissions to the page */
  1105. pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
  1106. key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
  1107. status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
  1108. if (!data) {
  1109. if (gr & (HPTE_R_N | HPTE_R_G))
  1110. return status | SRR1_ISI_N_G_OR_CIP;
  1111. if (!hpte_read_permission(pp, slb_v & key))
  1112. return status | SRR1_ISI_PROT;
  1113. } else if (status & DSISR_ISSTORE) {
  1114. /* check write permission */
  1115. if (!hpte_write_permission(pp, slb_v & key))
  1116. return status | DSISR_PROTFAULT;
  1117. } else {
  1118. if (!hpte_read_permission(pp, slb_v & key))
  1119. return status | DSISR_PROTFAULT;
  1120. }
  1121. /* Check storage key, if applicable */
  1122. if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
  1123. unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
  1124. if (status & DSISR_ISSTORE)
  1125. perm >>= 1;
  1126. if (perm & 1)
  1127. return status | DSISR_KEYFAULT;
  1128. }
  1129. /* Save HPTE info for virtual-mode handler */
  1130. vcpu->arch.pgfault_addr = addr;
  1131. vcpu->arch.pgfault_index = index;
  1132. vcpu->arch.pgfault_hpte[0] = v;
  1133. vcpu->arch.pgfault_hpte[1] = r;
  1134. vcpu->arch.pgfault_cache = cache_entry;
  1135. /* Check the storage key to see if it is possibly emulated MMIO */
  1136. if ((r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
  1137. (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) {
  1138. if (!cache_entry) {
  1139. unsigned int pshift = 12;
  1140. unsigned int pshift_index;
  1141. if (slb_v & SLB_VSID_L) {
  1142. pshift_index = ((slb_v & SLB_VSID_LP) >> 4);
  1143. pshift = slb_base_page_shift[pshift_index];
  1144. }
  1145. cache_entry = next_mmio_cache_entry(vcpu);
  1146. cache_entry->eaddr = addr;
  1147. cache_entry->slb_base_pshift = pshift;
  1148. cache_entry->pte_index = index;
  1149. cache_entry->hpte_v = v;
  1150. cache_entry->hpte_r = r;
  1151. cache_entry->rpte = gr;
  1152. cache_entry->slb_v = slb_v;
  1153. cache_entry->mmio_update = mmio_update;
  1154. }
  1155. if (data && (vcpu->arch.shregs.msr & MSR_IR))
  1156. return -2; /* MMIO emulation - load instr word */
  1157. }
  1158. return -1; /* send fault up to host kernel mode */
  1159. }