book3s_hv_interrupts.S 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. *
  4. * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  5. *
  6. * Derived from book3s_interrupts.S, which is:
  7. * Copyright SUSE Linux Products GmbH 2009
  8. *
  9. * Authors: Alexander Graf <agraf@suse.de>
  10. */
  11. #include <asm/ppc_asm.h>
  12. #include <asm/kvm_asm.h>
  13. #include <asm/reg.h>
  14. #include <asm/page.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/exception-64s.h>
  17. #include <asm/ppc-opcode.h>
  18. #include <asm/asm-compat.h>
  19. #include <asm/feature-fixups.h>
  20. /*****************************************************************************
  21. * *
  22. * Guest entry / exit code that is in kernel module memory (vmalloc) *
  23. * *
  24. ****************************************************************************/
  25. /* Registers:
  26. * none
  27. */
  28. _GLOBAL(__kvmppc_vcore_entry)
  29. /* Write correct stack frame */
  30. mflr r0
  31. std r0,PPC_LR_STKOFF(r1)
  32. /* Save host state to the stack */
  33. stdu r1, -SWITCH_FRAME_SIZE(r1)
  34. /* Save non-volatile registers (r14 - r31) and CR */
  35. SAVE_NVGPRS(r1)
  36. mfcr r3
  37. std r3, _CCR(r1)
  38. /* Save host DSCR */
  39. mfspr r3, SPRN_DSCR
  40. std r3, HSTATE_DSCR(r13)
  41. BEGIN_FTR_SECTION
  42. /* Save host DABR */
  43. mfspr r3, SPRN_DABR
  44. std r3, HSTATE_DABR(r13)
  45. END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
  46. /* Save host PMU registers */
  47. bl kvmhv_save_host_pmu
  48. /*
  49. * Put whatever is in the decrementer into the
  50. * hypervisor decrementer.
  51. * Because of a hardware deviation in P8 and P9,
  52. * we need to set LPCR[HDICE] before writing HDEC.
  53. */
  54. ld r5, HSTATE_KVM_VCORE(r13)
  55. ld r6, VCORE_KVM(r5)
  56. ld r9, KVM_HOST_LPCR(r6)
  57. ori r8, r9, LPCR_HDICE
  58. mtspr SPRN_LPCR, r8
  59. isync
  60. andis. r0, r9, LPCR_LD@h
  61. mfspr r8,SPRN_DEC
  62. mftb r7
  63. BEGIN_FTR_SECTION
  64. /* On POWER9, don't sign-extend if host LPCR[LD] bit is set */
  65. bne 32f
  66. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
  67. extsw r8,r8
  68. 32: mtspr SPRN_HDEC,r8
  69. add r8,r8,r7
  70. std r8,HSTATE_DECEXP(r13)
  71. /* Jump to partition switch code */
  72. bl kvmppc_hv_entry_trampoline
  73. nop
  74. /*
  75. * We return here in virtual mode after the guest exits
  76. * with something that we can't handle in real mode.
  77. * Interrupts are still hard-disabled.
  78. */
  79. /*
  80. * Register usage at this point:
  81. *
  82. * R1 = host R1
  83. * R2 = host R2
  84. * R3 = trap number on this thread
  85. * R12 = exit handler id
  86. * R13 = PACA
  87. */
  88. /* Restore non-volatile host registers (r14 - r31) and CR */
  89. REST_NVGPRS(r1)
  90. ld r4, _CCR(r1)
  91. mtcr r4
  92. addi r1, r1, SWITCH_FRAME_SIZE
  93. ld r0, PPC_LR_STKOFF(r1)
  94. mtlr r0
  95. blr
  96. _GLOBAL(kvmhv_save_host_pmu)
  97. BEGIN_FTR_SECTION
  98. /* Work around P8 PMAE bug */
  99. li r3, -1
  100. clrrdi r3, r3, 10
  101. mfspr r8, SPRN_MMCR2
  102. mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
  103. isync
  104. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  105. li r3, 1
  106. sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
  107. mfspr r7, SPRN_MMCR0 /* save MMCR0 */
  108. mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
  109. mfspr r6, SPRN_MMCRA
  110. /* Clear MMCRA in order to disable SDAR updates */
  111. li r5, 0
  112. mtspr SPRN_MMCRA, r5
  113. isync
  114. lbz r5, PACA_PMCINUSE(r13) /* is the host using the PMU? */
  115. cmpwi r5, 0
  116. beq 31f /* skip if not */
  117. mfspr r5, SPRN_MMCR1
  118. mfspr r9, SPRN_SIAR
  119. mfspr r10, SPRN_SDAR
  120. std r7, HSTATE_MMCR0(r13)
  121. std r5, HSTATE_MMCR1(r13)
  122. std r6, HSTATE_MMCRA(r13)
  123. std r9, HSTATE_SIAR(r13)
  124. std r10, HSTATE_SDAR(r13)
  125. BEGIN_FTR_SECTION
  126. mfspr r9, SPRN_SIER
  127. std r8, HSTATE_MMCR2(r13)
  128. std r9, HSTATE_SIER(r13)
  129. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  130. BEGIN_FTR_SECTION
  131. mfspr r5, SPRN_MMCR3
  132. mfspr r6, SPRN_SIER2
  133. mfspr r7, SPRN_SIER3
  134. std r5, HSTATE_MMCR3(r13)
  135. std r6, HSTATE_SIER2(r13)
  136. std r7, HSTATE_SIER3(r13)
  137. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
  138. mfspr r3, SPRN_PMC1
  139. mfspr r5, SPRN_PMC2
  140. mfspr r6, SPRN_PMC3
  141. mfspr r7, SPRN_PMC4
  142. mfspr r8, SPRN_PMC5
  143. mfspr r9, SPRN_PMC6
  144. stw r3, HSTATE_PMC1(r13)
  145. stw r5, HSTATE_PMC2(r13)
  146. stw r6, HSTATE_PMC3(r13)
  147. stw r7, HSTATE_PMC4(r13)
  148. stw r8, HSTATE_PMC5(r13)
  149. stw r9, HSTATE_PMC6(r13)
  150. 31: blr