rtas_pci.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
  4. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  5. *
  6. * RTAS specific routines for PCI.
  7. *
  8. * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/threads.h>
  12. #include <linux/pci.h>
  13. #include <linux/string.h>
  14. #include <linux/init.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/io.h>
  17. #include <asm/irq.h>
  18. #include <asm/prom.h>
  19. #include <asm/machdep.h>
  20. #include <asm/pci-bridge.h>
  21. #include <asm/iommu.h>
  22. #include <asm/rtas.h>
  23. #include <asm/mpic.h>
  24. #include <asm/ppc-pci.h>
  25. #include <asm/eeh.h>
  26. /* RTAS tokens */
  27. static int read_pci_config;
  28. static int write_pci_config;
  29. static int ibm_read_pci_config;
  30. static int ibm_write_pci_config;
  31. static inline int config_access_valid(struct pci_dn *dn, int where)
  32. {
  33. if (where < 256)
  34. return 1;
  35. if (where < 4096 && dn->pci_ext_config_space)
  36. return 1;
  37. return 0;
  38. }
  39. int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
  40. {
  41. int returnval = -1;
  42. unsigned long buid, addr;
  43. int ret;
  44. if (!pdn)
  45. return PCIBIOS_DEVICE_NOT_FOUND;
  46. if (!config_access_valid(pdn, where))
  47. return PCIBIOS_BAD_REGISTER_NUMBER;
  48. #ifdef CONFIG_EEH
  49. if (pdn->edev && pdn->edev->pe &&
  50. (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
  51. return PCIBIOS_SET_FAILED;
  52. #endif
  53. addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
  54. buid = pdn->phb->buid;
  55. if (buid) {
  56. ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
  57. addr, BUID_HI(buid), BUID_LO(buid), size);
  58. } else {
  59. ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
  60. }
  61. *val = returnval;
  62. if (ret)
  63. return PCIBIOS_DEVICE_NOT_FOUND;
  64. return PCIBIOS_SUCCESSFUL;
  65. }
  66. static int rtas_pci_read_config(struct pci_bus *bus,
  67. unsigned int devfn,
  68. int where, int size, u32 *val)
  69. {
  70. struct pci_dn *pdn;
  71. int ret;
  72. *val = 0xFFFFFFFF;
  73. pdn = pci_get_pdn_by_devfn(bus, devfn);
  74. /* Validity of pdn is checked in here */
  75. ret = rtas_read_config(pdn, where, size, val);
  76. if (*val == EEH_IO_ERROR_VALUE(size) &&
  77. eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
  78. return PCIBIOS_DEVICE_NOT_FOUND;
  79. return ret;
  80. }
  81. int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
  82. {
  83. unsigned long buid, addr;
  84. int ret;
  85. if (!pdn)
  86. return PCIBIOS_DEVICE_NOT_FOUND;
  87. if (!config_access_valid(pdn, where))
  88. return PCIBIOS_BAD_REGISTER_NUMBER;
  89. #ifdef CONFIG_EEH
  90. if (pdn->edev && pdn->edev->pe &&
  91. (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
  92. return PCIBIOS_SET_FAILED;
  93. #endif
  94. addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
  95. buid = pdn->phb->buid;
  96. if (buid) {
  97. ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
  98. BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
  99. } else {
  100. ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
  101. }
  102. if (ret)
  103. return PCIBIOS_DEVICE_NOT_FOUND;
  104. return PCIBIOS_SUCCESSFUL;
  105. }
  106. static int rtas_pci_write_config(struct pci_bus *bus,
  107. unsigned int devfn,
  108. int where, int size, u32 val)
  109. {
  110. struct pci_dn *pdn;
  111. pdn = pci_get_pdn_by_devfn(bus, devfn);
  112. /* Validity of pdn is checked in here. */
  113. return rtas_write_config(pdn, where, size, val);
  114. }
  115. static struct pci_ops rtas_pci_ops = {
  116. .read = rtas_pci_read_config,
  117. .write = rtas_pci_write_config,
  118. };
  119. static int is_python(struct device_node *dev)
  120. {
  121. const char *model = of_get_property(dev, "model", NULL);
  122. if (model && strstr(model, "Python"))
  123. return 1;
  124. return 0;
  125. }
  126. static void python_countermeasures(struct device_node *dev)
  127. {
  128. struct resource registers;
  129. void __iomem *chip_regs;
  130. volatile u32 val;
  131. if (of_address_to_resource(dev, 0, &registers)) {
  132. printk(KERN_ERR "Can't get address for Python workarounds !\n");
  133. return;
  134. }
  135. /* Python's register file is 1 MB in size. */
  136. chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
  137. /*
  138. * Firmware doesn't always clear this bit which is critical
  139. * for good performance - Anton
  140. */
  141. #define PRG_CL_RESET_VALID 0x00010000
  142. val = in_be32(chip_regs + 0xf6030);
  143. if (val & PRG_CL_RESET_VALID) {
  144. printk(KERN_INFO "Python workaround: ");
  145. val &= ~PRG_CL_RESET_VALID;
  146. out_be32(chip_regs + 0xf6030, val);
  147. /*
  148. * We must read it back for changes to
  149. * take effect
  150. */
  151. val = in_be32(chip_regs + 0xf6030);
  152. printk("reg0: %x\n", val);
  153. }
  154. iounmap(chip_regs);
  155. }
  156. void __init init_pci_config_tokens(void)
  157. {
  158. read_pci_config = rtas_token("read-pci-config");
  159. write_pci_config = rtas_token("write-pci-config");
  160. ibm_read_pci_config = rtas_token("ibm,read-pci-config");
  161. ibm_write_pci_config = rtas_token("ibm,write-pci-config");
  162. }
  163. unsigned long get_phb_buid(struct device_node *phb)
  164. {
  165. struct resource r;
  166. if (ibm_read_pci_config == -1)
  167. return 0;
  168. if (of_address_to_resource(phb, 0, &r))
  169. return 0;
  170. return r.start;
  171. }
  172. static int phb_set_bus_ranges(struct device_node *dev,
  173. struct pci_controller *phb)
  174. {
  175. const __be32 *bus_range;
  176. unsigned int len;
  177. bus_range = of_get_property(dev, "bus-range", &len);
  178. if (bus_range == NULL || len < 2 * sizeof(int)) {
  179. return 1;
  180. }
  181. phb->first_busno = be32_to_cpu(bus_range[0]);
  182. phb->last_busno = be32_to_cpu(bus_range[1]);
  183. return 0;
  184. }
  185. int rtas_setup_phb(struct pci_controller *phb)
  186. {
  187. struct device_node *dev = phb->dn;
  188. if (is_python(dev))
  189. python_countermeasures(dev);
  190. if (phb_set_bus_ranges(dev, phb))
  191. return 1;
  192. phb->ops = &rtas_pci_ops;
  193. phb->buid = get_phb_buid(dev);
  194. return 0;
  195. }