pmc.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/powerpc/kernel/pmc.c
  4. *
  5. * Copyright (C) 2004 David Gibson, IBM Corporation.
  6. * Includes code formerly from arch/ppc/kernel/perfmon.c:
  7. * Author: Andy Fleming
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc
  9. */
  10. #include <linux/errno.h>
  11. #include <linux/bug.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/export.h>
  14. #include <asm/processor.h>
  15. #include <asm/cputable.h>
  16. #include <asm/pmc.h>
  17. #ifndef MMCR0_PMAO
  18. #define MMCR0_PMAO 0
  19. #endif
  20. static void dummy_perf(struct pt_regs *regs)
  21. {
  22. #if defined(CONFIG_FSL_EMB_PERFMON)
  23. mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
  24. #elif defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
  25. if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
  26. mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO));
  27. #else
  28. mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
  29. #endif
  30. }
  31. static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
  32. static void *pmc_owner_caller; /* mostly for debugging */
  33. perf_irq_t perf_irq = dummy_perf;
  34. int reserve_pmc_hardware(perf_irq_t new_perf_irq)
  35. {
  36. int err = 0;
  37. raw_spin_lock(&pmc_owner_lock);
  38. if (pmc_owner_caller) {
  39. printk(KERN_WARNING "reserve_pmc_hardware: "
  40. "PMC hardware busy (reserved by caller %p)\n",
  41. pmc_owner_caller);
  42. err = -EBUSY;
  43. goto out;
  44. }
  45. pmc_owner_caller = __builtin_return_address(0);
  46. perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
  47. out:
  48. raw_spin_unlock(&pmc_owner_lock);
  49. return err;
  50. }
  51. EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
  52. void release_pmc_hardware(void)
  53. {
  54. raw_spin_lock(&pmc_owner_lock);
  55. WARN_ON(! pmc_owner_caller);
  56. pmc_owner_caller = NULL;
  57. perf_irq = dummy_perf;
  58. raw_spin_unlock(&pmc_owner_lock);
  59. }
  60. EXPORT_SYMBOL_GPL(release_pmc_hardware);
  61. #ifdef CONFIG_PPC64
  62. void power4_enable_pmcs(void)
  63. {
  64. unsigned long hid0;
  65. hid0 = mfspr(SPRN_HID0);
  66. hid0 |= 1UL << (63 - 20);
  67. /* POWER4 requires the following sequence */
  68. asm volatile(
  69. "sync\n"
  70. "mtspr %1, %0\n"
  71. "mfspr %0, %1\n"
  72. "mfspr %0, %1\n"
  73. "mfspr %0, %1\n"
  74. "mfspr %0, %1\n"
  75. "mfspr %0, %1\n"
  76. "mfspr %0, %1\n"
  77. "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
  78. "memory");
  79. }
  80. #endif /* CONFIG_PPC64 */