pci_64.c 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Port for PPC64 David Engebretsen, IBM Corp.
  4. * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  5. *
  6. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  7. * Rework, based on alpha PCI code.
  8. */
  9. #undef DEBUG
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/string.h>
  13. #include <linux/init.h>
  14. #include <linux/export.h>
  15. #include <linux/mm.h>
  16. #include <linux/list.h>
  17. #include <linux/syscalls.h>
  18. #include <linux/irq.h>
  19. #include <linux/vmalloc.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <asm/prom.h>
  23. #include <asm/pci-bridge.h>
  24. #include <asm/byteorder.h>
  25. #include <asm/machdep.h>
  26. #include <asm/ppc-pci.h>
  27. /* pci_io_base -- the base address from which io bars are offsets.
  28. * This is the lowest I/O base address (so bar values are always positive),
  29. * and it *must* be the start of ISA space if an ISA bus exists because
  30. * ISA drivers use hard coded offsets. If no ISA bus exists nothing
  31. * is mapped on the first 64K of IO space
  32. */
  33. unsigned long pci_io_base;
  34. EXPORT_SYMBOL(pci_io_base);
  35. static int __init pcibios_init(void)
  36. {
  37. struct pci_controller *hose, *tmp;
  38. printk(KERN_INFO "PCI: Probing PCI hardware\n");
  39. /* For now, override phys_mem_access_prot. If we need it,g
  40. * later, we may move that initialization to each ppc_md
  41. */
  42. ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
  43. /* On ppc64, we always enable PCI domains and we keep domain 0
  44. * backward compatible in /proc for video cards
  45. */
  46. pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
  47. /* Scan all of the recorded PCI controllers. */
  48. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  49. pcibios_scan_phb(hose);
  50. /* Call common code to handle resource allocation */
  51. pcibios_resource_survey();
  52. /* Add devices. */
  53. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  54. pci_bus_add_devices(hose->bus);
  55. /* Call machine dependent fixup */
  56. if (ppc_md.pcibios_fixup)
  57. ppc_md.pcibios_fixup();
  58. printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
  59. return 0;
  60. }
  61. subsys_initcall(pcibios_init);
  62. int pcibios_unmap_io_space(struct pci_bus *bus)
  63. {
  64. struct pci_controller *hose;
  65. WARN_ON(bus == NULL);
  66. /* If this is not a PHB, we only flush the hash table over
  67. * the area mapped by this bridge. We don't play with the PTE
  68. * mappings since we might have to deal with sub-page alignments
  69. * so flushing the hash table is the only sane way to make sure
  70. * that no hash entries are covering that removed bridge area
  71. * while still allowing other busses overlapping those pages
  72. *
  73. * Note: If we ever support P2P hotplug on Book3E, we'll have
  74. * to do an appropriate TLB flush here too
  75. */
  76. if (bus->self) {
  77. #ifdef CONFIG_PPC_BOOK3S_64
  78. struct resource *res = bus->resource[0];
  79. #endif
  80. pr_debug("IO unmapping for PCI-PCI bridge %s\n",
  81. pci_name(bus->self));
  82. #ifdef CONFIG_PPC_BOOK3S_64
  83. __flush_hash_table_range(res->start + _IO_BASE,
  84. res->end + _IO_BASE + 1);
  85. #endif
  86. return 0;
  87. }
  88. /* Get the host bridge */
  89. hose = pci_bus_to_host(bus);
  90. pr_debug("IO unmapping for PHB %pOF\n", hose->dn);
  91. pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
  92. iounmap(hose->io_base_alloc);
  93. return 0;
  94. }
  95. EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
  96. void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size)
  97. {
  98. struct vm_struct *area;
  99. unsigned long addr;
  100. WARN_ON_ONCE(paddr & ~PAGE_MASK);
  101. WARN_ON_ONCE(size & ~PAGE_MASK);
  102. /*
  103. * Let's allocate some IO space for that guy. We don't pass VM_IOREMAP
  104. * because we don't care about alignment tricks that the core does in
  105. * that case. Maybe we should due to stupid card with incomplete
  106. * address decoding but I'd rather not deal with those outside of the
  107. * reserved 64K legacy region.
  108. */
  109. area = __get_vm_area_caller(size, 0, PHB_IO_BASE, PHB_IO_END,
  110. __builtin_return_address(0));
  111. if (!area)
  112. return NULL;
  113. addr = (unsigned long)area->addr;
  114. if (ioremap_page_range(addr, addr + size, paddr,
  115. pgprot_noncached(PAGE_KERNEL))) {
  116. unmap_kernel_range(addr, size);
  117. return NULL;
  118. }
  119. return (void __iomem *)addr;
  120. }
  121. EXPORT_SYMBOL_GPL(ioremap_phb);
  122. static int pcibios_map_phb_io_space(struct pci_controller *hose)
  123. {
  124. unsigned long phys_page;
  125. unsigned long size_page;
  126. unsigned long io_virt_offset;
  127. phys_page = ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
  128. size_page = ALIGN(hose->pci_io_size, PAGE_SIZE);
  129. /* Make sure IO area address is clear */
  130. hose->io_base_alloc = NULL;
  131. /* If there's no IO to map on that bus, get away too */
  132. if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
  133. return 0;
  134. /* Let's allocate some IO space for that guy. We don't pass
  135. * VM_IOREMAP because we don't care about alignment tricks that
  136. * the core does in that case. Maybe we should due to stupid card
  137. * with incomplete address decoding but I'd rather not deal with
  138. * those outside of the reserved 64K legacy region.
  139. */
  140. hose->io_base_alloc = ioremap_phb(phys_page, size_page);
  141. if (!hose->io_base_alloc)
  142. return -ENOMEM;
  143. hose->io_base_virt = hose->io_base_alloc +
  144. hose->io_base_phys - phys_page;
  145. pr_debug("IO mapping for PHB %pOF\n", hose->dn);
  146. pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
  147. hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
  148. pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
  149. hose->pci_io_size, size_page);
  150. /* Fixup hose IO resource */
  151. io_virt_offset = pcibios_io_space_offset(hose);
  152. hose->io_resource.start += io_virt_offset;
  153. hose->io_resource.end += io_virt_offset;
  154. pr_debug(" hose->io_resource=%pR\n", &hose->io_resource);
  155. return 0;
  156. }
  157. int pcibios_map_io_space(struct pci_bus *bus)
  158. {
  159. WARN_ON(bus == NULL);
  160. /* If this not a PHB, nothing to do, page tables still exist and
  161. * thus HPTEs will be faulted in when needed
  162. */
  163. if (bus->self) {
  164. pr_debug("IO mapping for PCI-PCI bridge %s\n",
  165. pci_name(bus->self));
  166. pr_debug(" virt=0x%016llx...0x%016llx\n",
  167. bus->resource[0]->start + _IO_BASE,
  168. bus->resource[0]->end + _IO_BASE);
  169. return 0;
  170. }
  171. return pcibios_map_phb_io_space(pci_bus_to_host(bus));
  172. }
  173. EXPORT_SYMBOL_GPL(pcibios_map_io_space);
  174. void pcibios_setup_phb_io_space(struct pci_controller *hose)
  175. {
  176. pcibios_map_phb_io_space(hose);
  177. }
  178. #define IOBASE_BRIDGE_NUMBER 0
  179. #define IOBASE_MEMORY 1
  180. #define IOBASE_IO 2
  181. #define IOBASE_ISA_IO 3
  182. #define IOBASE_ISA_MEM 4
  183. SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus,
  184. unsigned long, in_devfn)
  185. {
  186. struct pci_controller* hose;
  187. struct pci_bus *tmp_bus, *bus = NULL;
  188. struct device_node *hose_node;
  189. /* Argh ! Please forgive me for that hack, but that's the
  190. * simplest way to get existing XFree to not lockup on some
  191. * G5 machines... So when something asks for bus 0 io base
  192. * (bus 0 is HT root), we return the AGP one instead.
  193. */
  194. if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
  195. struct device_node *agp;
  196. agp = of_find_compatible_node(NULL, NULL, "u3-agp");
  197. if (agp)
  198. in_bus = 0xf0;
  199. of_node_put(agp);
  200. }
  201. /* That syscall isn't quite compatible with PCI domains, but it's
  202. * used on pre-domains setup. We return the first match
  203. */
  204. list_for_each_entry(tmp_bus, &pci_root_buses, node) {
  205. if (in_bus >= tmp_bus->number &&
  206. in_bus <= tmp_bus->busn_res.end) {
  207. bus = tmp_bus;
  208. break;
  209. }
  210. }
  211. if (bus == NULL || bus->dev.of_node == NULL)
  212. return -ENODEV;
  213. hose_node = bus->dev.of_node;
  214. hose = PCI_DN(hose_node)->phb;
  215. switch (which) {
  216. case IOBASE_BRIDGE_NUMBER:
  217. return (long)hose->first_busno;
  218. case IOBASE_MEMORY:
  219. return (long)hose->mem_offset[0];
  220. case IOBASE_IO:
  221. return (long)hose->io_base_phys;
  222. case IOBASE_ISA_IO:
  223. return (long)isa_io_base;
  224. case IOBASE_ISA_MEM:
  225. return -EINVAL;
  226. }
  227. return -EOPNOTSUPP;
  228. }
  229. #ifdef CONFIG_NUMA
  230. int pcibus_to_node(struct pci_bus *bus)
  231. {
  232. struct pci_controller *phb = pci_bus_to_host(bus);
  233. return phb->node;
  234. }
  235. EXPORT_SYMBOL(pcibus_to_node);
  236. #endif