pci-common.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Contains common pci routines for ALL ppc platform
  4. * (based on pci_32.c and pci_64.c)
  5. *
  6. * Port for PPC64 David Engebretsen, IBM Corp.
  7. * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  8. *
  9. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  10. * Rework, based on alpha PCI code.
  11. *
  12. * Common pmac/prep/chrp pci routines. -- Cort
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/string.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/export.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_pci.h>
  22. #include <linux/mm.h>
  23. #include <linux/shmem_fs.h>
  24. #include <linux/list.h>
  25. #include <linux/syscalls.h>
  26. #include <linux/irq.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/slab.h>
  29. #include <linux/vgaarb.h>
  30. #include <linux/numa.h>
  31. #include <asm/processor.h>
  32. #include <asm/io.h>
  33. #include <asm/prom.h>
  34. #include <asm/pci-bridge.h>
  35. #include <asm/byteorder.h>
  36. #include <asm/machdep.h>
  37. #include <asm/ppc-pci.h>
  38. #include <asm/eeh.h>
  39. #include "../../../drivers/pci/pci.h"
  40. /* hose_spinlock protects accesses to the the phb_bitmap. */
  41. static DEFINE_SPINLOCK(hose_spinlock);
  42. LIST_HEAD(hose_list);
  43. /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
  44. #define MAX_PHBS 0x10000
  45. /*
  46. * For dynamic PHB numbering: used/free PHBs tracking bitmap.
  47. * Accesses to this bitmap should be protected by hose_spinlock.
  48. */
  49. static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
  50. /* ISA Memory physical address */
  51. resource_size_t isa_mem_base;
  52. EXPORT_SYMBOL(isa_mem_base);
  53. static const struct dma_map_ops *pci_dma_ops;
  54. void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
  55. {
  56. pci_dma_ops = dma_ops;
  57. }
  58. /*
  59. * This function should run under locking protection, specifically
  60. * hose_spinlock.
  61. */
  62. static int get_phb_number(struct device_node *dn)
  63. {
  64. int ret, phb_id = -1;
  65. u32 prop_32;
  66. u64 prop;
  67. /*
  68. * Try fixed PHB numbering first, by checking archs and reading
  69. * the respective device-tree properties. Firstly, try powernv by
  70. * reading "ibm,opal-phbid", only present in OPAL environment.
  71. */
  72. ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
  73. if (ret) {
  74. ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
  75. prop = prop_32;
  76. }
  77. if (!ret)
  78. phb_id = (int)(prop & (MAX_PHBS - 1));
  79. /* We need to be sure to not use the same PHB number twice. */
  80. if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
  81. return phb_id;
  82. /*
  83. * If not pseries nor powernv, or if fixed PHB numbering tried to add
  84. * the same PHB number twice, then fallback to dynamic PHB numbering.
  85. */
  86. phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
  87. BUG_ON(phb_id >= MAX_PHBS);
  88. set_bit(phb_id, phb_bitmap);
  89. return phb_id;
  90. }
  91. struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
  92. {
  93. struct pci_controller *phb;
  94. phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
  95. if (phb == NULL)
  96. return NULL;
  97. spin_lock(&hose_spinlock);
  98. phb->global_number = get_phb_number(dev);
  99. list_add_tail(&phb->list_node, &hose_list);
  100. spin_unlock(&hose_spinlock);
  101. phb->dn = dev;
  102. phb->is_dynamic = slab_is_available();
  103. #ifdef CONFIG_PPC64
  104. if (dev) {
  105. int nid = of_node_to_nid(dev);
  106. if (nid < 0 || !node_online(nid))
  107. nid = NUMA_NO_NODE;
  108. PHB_SET_NODE(phb, nid);
  109. }
  110. #endif
  111. return phb;
  112. }
  113. EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
  114. void pcibios_free_controller(struct pci_controller *phb)
  115. {
  116. spin_lock(&hose_spinlock);
  117. /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
  118. if (phb->global_number < MAX_PHBS)
  119. clear_bit(phb->global_number, phb_bitmap);
  120. list_del(&phb->list_node);
  121. spin_unlock(&hose_spinlock);
  122. if (phb->is_dynamic)
  123. kfree(phb);
  124. }
  125. EXPORT_SYMBOL_GPL(pcibios_free_controller);
  126. /*
  127. * This function is used to call pcibios_free_controller()
  128. * in a deferred manner: a callback from the PCI subsystem.
  129. *
  130. * _*DO NOT*_ call pcibios_free_controller() explicitly if
  131. * this is used (or it may access an invalid *phb pointer).
  132. *
  133. * The callback occurs when all references to the root bus
  134. * are dropped (e.g., child buses/devices and their users).
  135. *
  136. * It's called as .release_fn() of 'struct pci_host_bridge'
  137. * which is associated with the 'struct pci_controller.bus'
  138. * (root bus) - it expects .release_data to hold a pointer
  139. * to 'struct pci_controller'.
  140. *
  141. * In order to use it, register .release_fn()/release_data
  142. * like this:
  143. *
  144. * pci_set_host_bridge_release(bridge,
  145. * pcibios_free_controller_deferred
  146. * (void *) phb);
  147. *
  148. * e.g. in the pcibios_root_bridge_prepare() callback from
  149. * pci_create_root_bus().
  150. */
  151. void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
  152. {
  153. struct pci_controller *phb = (struct pci_controller *)
  154. bridge->release_data;
  155. pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
  156. pcibios_free_controller(phb);
  157. }
  158. EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
  159. /*
  160. * The function is used to return the minimal alignment
  161. * for memory or I/O windows of the associated P2P bridge.
  162. * By default, 4KiB alignment for I/O windows and 1MiB for
  163. * memory windows.
  164. */
  165. resource_size_t pcibios_window_alignment(struct pci_bus *bus,
  166. unsigned long type)
  167. {
  168. struct pci_controller *phb = pci_bus_to_host(bus);
  169. if (phb->controller_ops.window_alignment)
  170. return phb->controller_ops.window_alignment(bus, type);
  171. /*
  172. * PCI core will figure out the default
  173. * alignment: 4KiB for I/O and 1MiB for
  174. * memory window.
  175. */
  176. return 1;
  177. }
  178. void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
  179. {
  180. struct pci_controller *hose = pci_bus_to_host(bus);
  181. if (hose->controller_ops.setup_bridge)
  182. hose->controller_ops.setup_bridge(bus, type);
  183. }
  184. void pcibios_reset_secondary_bus(struct pci_dev *dev)
  185. {
  186. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  187. if (phb->controller_ops.reset_secondary_bus) {
  188. phb->controller_ops.reset_secondary_bus(dev);
  189. return;
  190. }
  191. pci_reset_secondary_bus(dev);
  192. }
  193. resource_size_t pcibios_default_alignment(void)
  194. {
  195. if (ppc_md.pcibios_default_alignment)
  196. return ppc_md.pcibios_default_alignment();
  197. return 0;
  198. }
  199. #ifdef CONFIG_PCI_IOV
  200. resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
  201. {
  202. if (ppc_md.pcibios_iov_resource_alignment)
  203. return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
  204. return pci_iov_resource_size(pdev, resno);
  205. }
  206. int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
  207. {
  208. if (ppc_md.pcibios_sriov_enable)
  209. return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
  210. return 0;
  211. }
  212. int pcibios_sriov_disable(struct pci_dev *pdev)
  213. {
  214. if (ppc_md.pcibios_sriov_disable)
  215. return ppc_md.pcibios_sriov_disable(pdev);
  216. return 0;
  217. }
  218. #endif /* CONFIG_PCI_IOV */
  219. static resource_size_t pcibios_io_size(const struct pci_controller *hose)
  220. {
  221. #ifdef CONFIG_PPC64
  222. return hose->pci_io_size;
  223. #else
  224. return resource_size(&hose->io_resource);
  225. #endif
  226. }
  227. int pcibios_vaddr_is_ioport(void __iomem *address)
  228. {
  229. int ret = 0;
  230. struct pci_controller *hose;
  231. resource_size_t size;
  232. spin_lock(&hose_spinlock);
  233. list_for_each_entry(hose, &hose_list, list_node) {
  234. size = pcibios_io_size(hose);
  235. if (address >= hose->io_base_virt &&
  236. address < (hose->io_base_virt + size)) {
  237. ret = 1;
  238. break;
  239. }
  240. }
  241. spin_unlock(&hose_spinlock);
  242. return ret;
  243. }
  244. unsigned long pci_address_to_pio(phys_addr_t address)
  245. {
  246. struct pci_controller *hose;
  247. resource_size_t size;
  248. unsigned long ret = ~0;
  249. spin_lock(&hose_spinlock);
  250. list_for_each_entry(hose, &hose_list, list_node) {
  251. size = pcibios_io_size(hose);
  252. if (address >= hose->io_base_phys &&
  253. address < (hose->io_base_phys + size)) {
  254. unsigned long base =
  255. (unsigned long)hose->io_base_virt - _IO_BASE;
  256. ret = base + (address - hose->io_base_phys);
  257. break;
  258. }
  259. }
  260. spin_unlock(&hose_spinlock);
  261. return ret;
  262. }
  263. EXPORT_SYMBOL_GPL(pci_address_to_pio);
  264. /*
  265. * Return the domain number for this bus.
  266. */
  267. int pci_domain_nr(struct pci_bus *bus)
  268. {
  269. struct pci_controller *hose = pci_bus_to_host(bus);
  270. return hose->global_number;
  271. }
  272. EXPORT_SYMBOL(pci_domain_nr);
  273. /* This routine is meant to be used early during boot, when the
  274. * PCI bus numbers have not yet been assigned, and you need to
  275. * issue PCI config cycles to an OF device.
  276. * It could also be used to "fix" RTAS config cycles if you want
  277. * to set pci_assign_all_buses to 1 and still use RTAS for PCI
  278. * config cycles.
  279. */
  280. struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
  281. {
  282. while(node) {
  283. struct pci_controller *hose, *tmp;
  284. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  285. if (hose->dn == node)
  286. return hose;
  287. node = node->parent;
  288. }
  289. return NULL;
  290. }
  291. struct pci_controller *pci_find_controller_for_domain(int domain_nr)
  292. {
  293. struct pci_controller *hose;
  294. list_for_each_entry(hose, &hose_list, list_node)
  295. if (hose->global_number == domain_nr)
  296. return hose;
  297. return NULL;
  298. }
  299. /*
  300. * Reads the interrupt pin to determine if interrupt is use by card.
  301. * If the interrupt is used, then gets the interrupt line from the
  302. * openfirmware and sets it in the pci_dev and pci_config line.
  303. */
  304. static int pci_read_irq_line(struct pci_dev *pci_dev)
  305. {
  306. int virq;
  307. pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
  308. /* Try to get a mapping from the device-tree */
  309. virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
  310. if (virq <= 0) {
  311. u8 line, pin;
  312. /* If that fails, lets fallback to what is in the config
  313. * space and map that through the default controller. We
  314. * also set the type to level low since that's what PCI
  315. * interrupts are. If your platform does differently, then
  316. * either provide a proper interrupt tree or don't use this
  317. * function.
  318. */
  319. if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
  320. return -1;
  321. if (pin == 0)
  322. return -1;
  323. if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
  324. line == 0xff || line == 0) {
  325. return -1;
  326. }
  327. pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
  328. line, pin);
  329. virq = irq_create_mapping(NULL, line);
  330. if (virq)
  331. irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
  332. }
  333. if (!virq) {
  334. pr_debug(" Failed to map !\n");
  335. return -1;
  336. }
  337. pr_debug(" Mapped to linux irq %d\n", virq);
  338. pci_dev->irq = virq;
  339. return 0;
  340. }
  341. /*
  342. * Platform support for /proc/bus/pci/X/Y mmap()s.
  343. * -- paulus.
  344. */
  345. int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
  346. {
  347. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  348. resource_size_t ioaddr = pci_resource_start(pdev, bar);
  349. if (!hose)
  350. return -EINVAL;
  351. /* Convert to an offset within this PCI controller */
  352. ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
  353. vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
  354. return 0;
  355. }
  356. /*
  357. * This one is used by /dev/mem and fbdev who have no clue about the
  358. * PCI device, it tries to find the PCI device first and calls the
  359. * above routine
  360. */
  361. pgprot_t pci_phys_mem_access_prot(struct file *file,
  362. unsigned long pfn,
  363. unsigned long size,
  364. pgprot_t prot)
  365. {
  366. struct pci_dev *pdev = NULL;
  367. struct resource *found = NULL;
  368. resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
  369. int i;
  370. if (page_is_ram(pfn))
  371. return prot;
  372. prot = pgprot_noncached(prot);
  373. for_each_pci_dev(pdev) {
  374. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  375. struct resource *rp = &pdev->resource[i];
  376. int flags = rp->flags;
  377. /* Active and same type? */
  378. if ((flags & IORESOURCE_MEM) == 0)
  379. continue;
  380. /* In the range of this resource? */
  381. if (offset < (rp->start & PAGE_MASK) ||
  382. offset > rp->end)
  383. continue;
  384. found = rp;
  385. break;
  386. }
  387. if (found)
  388. break;
  389. }
  390. if (found) {
  391. if (found->flags & IORESOURCE_PREFETCH)
  392. prot = pgprot_noncached_wc(prot);
  393. pci_dev_put(pdev);
  394. }
  395. pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
  396. (unsigned long long)offset, pgprot_val(prot));
  397. return prot;
  398. }
  399. /* This provides legacy IO read access on a bus */
  400. int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
  401. {
  402. unsigned long offset;
  403. struct pci_controller *hose = pci_bus_to_host(bus);
  404. struct resource *rp = &hose->io_resource;
  405. void __iomem *addr;
  406. /* Check if port can be supported by that bus. We only check
  407. * the ranges of the PHB though, not the bus itself as the rules
  408. * for forwarding legacy cycles down bridges are not our problem
  409. * here. So if the host bridge supports it, we do it.
  410. */
  411. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  412. offset += port;
  413. if (!(rp->flags & IORESOURCE_IO))
  414. return -ENXIO;
  415. if (offset < rp->start || (offset + size) > rp->end)
  416. return -ENXIO;
  417. addr = hose->io_base_virt + port;
  418. switch(size) {
  419. case 1:
  420. *((u8 *)val) = in_8(addr);
  421. return 1;
  422. case 2:
  423. if (port & 1)
  424. return -EINVAL;
  425. *((u16 *)val) = in_le16(addr);
  426. return 2;
  427. case 4:
  428. if (port & 3)
  429. return -EINVAL;
  430. *((u32 *)val) = in_le32(addr);
  431. return 4;
  432. }
  433. return -EINVAL;
  434. }
  435. /* This provides legacy IO write access on a bus */
  436. int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
  437. {
  438. unsigned long offset;
  439. struct pci_controller *hose = pci_bus_to_host(bus);
  440. struct resource *rp = &hose->io_resource;
  441. void __iomem *addr;
  442. /* Check if port can be supported by that bus. We only check
  443. * the ranges of the PHB though, not the bus itself as the rules
  444. * for forwarding legacy cycles down bridges are not our problem
  445. * here. So if the host bridge supports it, we do it.
  446. */
  447. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  448. offset += port;
  449. if (!(rp->flags & IORESOURCE_IO))
  450. return -ENXIO;
  451. if (offset < rp->start || (offset + size) > rp->end)
  452. return -ENXIO;
  453. addr = hose->io_base_virt + port;
  454. /* WARNING: The generic code is idiotic. It gets passed a pointer
  455. * to what can be a 1, 2 or 4 byte quantity and always reads that
  456. * as a u32, which means that we have to correct the location of
  457. * the data read within those 32 bits for size 1 and 2
  458. */
  459. switch(size) {
  460. case 1:
  461. out_8(addr, val >> 24);
  462. return 1;
  463. case 2:
  464. if (port & 1)
  465. return -EINVAL;
  466. out_le16(addr, val >> 16);
  467. return 2;
  468. case 4:
  469. if (port & 3)
  470. return -EINVAL;
  471. out_le32(addr, val);
  472. return 4;
  473. }
  474. return -EINVAL;
  475. }
  476. /* This provides legacy IO or memory mmap access on a bus */
  477. int pci_mmap_legacy_page_range(struct pci_bus *bus,
  478. struct vm_area_struct *vma,
  479. enum pci_mmap_state mmap_state)
  480. {
  481. struct pci_controller *hose = pci_bus_to_host(bus);
  482. resource_size_t offset =
  483. ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
  484. resource_size_t size = vma->vm_end - vma->vm_start;
  485. struct resource *rp;
  486. pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
  487. pci_domain_nr(bus), bus->number,
  488. mmap_state == pci_mmap_mem ? "MEM" : "IO",
  489. (unsigned long long)offset,
  490. (unsigned long long)(offset + size - 1));
  491. if (mmap_state == pci_mmap_mem) {
  492. /* Hack alert !
  493. *
  494. * Because X is lame and can fail starting if it gets an error trying
  495. * to mmap legacy_mem (instead of just moving on without legacy memory
  496. * access) we fake it here by giving it anonymous memory, effectively
  497. * behaving just like /dev/zero
  498. */
  499. if ((offset + size) > hose->isa_mem_size) {
  500. printk(KERN_DEBUG
  501. "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
  502. current->comm, current->pid, pci_domain_nr(bus), bus->number);
  503. if (vma->vm_flags & VM_SHARED)
  504. return shmem_zero_setup(vma);
  505. return 0;
  506. }
  507. offset += hose->isa_mem_phys;
  508. } else {
  509. unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  510. unsigned long roffset = offset + io_offset;
  511. rp = &hose->io_resource;
  512. if (!(rp->flags & IORESOURCE_IO))
  513. return -ENXIO;
  514. if (roffset < rp->start || (roffset + size) > rp->end)
  515. return -ENXIO;
  516. offset += hose->io_base_phys;
  517. }
  518. pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
  519. vma->vm_pgoff = offset >> PAGE_SHIFT;
  520. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  521. return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  522. vma->vm_end - vma->vm_start,
  523. vma->vm_page_prot);
  524. }
  525. void pci_resource_to_user(const struct pci_dev *dev, int bar,
  526. const struct resource *rsrc,
  527. resource_size_t *start, resource_size_t *end)
  528. {
  529. struct pci_bus_region region;
  530. if (rsrc->flags & IORESOURCE_IO) {
  531. pcibios_resource_to_bus(dev->bus, &region,
  532. (struct resource *) rsrc);
  533. *start = region.start;
  534. *end = region.end;
  535. return;
  536. }
  537. /* We pass a CPU physical address to userland for MMIO instead of a
  538. * BAR value because X is lame and expects to be able to use that
  539. * to pass to /dev/mem!
  540. *
  541. * That means we may have 64-bit values where some apps only expect
  542. * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
  543. */
  544. *start = rsrc->start;
  545. *end = rsrc->end;
  546. }
  547. /**
  548. * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
  549. * @hose: newly allocated pci_controller to be setup
  550. * @dev: device node of the host bridge
  551. * @primary: set if primary bus (32 bits only, soon to be deprecated)
  552. *
  553. * This function will parse the "ranges" property of a PCI host bridge device
  554. * node and setup the resource mapping of a pci controller based on its
  555. * content.
  556. *
  557. * Life would be boring if it wasn't for a few issues that we have to deal
  558. * with here:
  559. *
  560. * - We can only cope with one IO space range and up to 3 Memory space
  561. * ranges. However, some machines (thanks Apple !) tend to split their
  562. * space into lots of small contiguous ranges. So we have to coalesce.
  563. *
  564. * - Some busses have IO space not starting at 0, which causes trouble with
  565. * the way we do our IO resource renumbering. The code somewhat deals with
  566. * it for 64 bits but I would expect problems on 32 bits.
  567. *
  568. * - Some 32 bits platforms such as 4xx can have physical space larger than
  569. * 32 bits so we need to use 64 bits values for the parsing
  570. */
  571. void pci_process_bridge_OF_ranges(struct pci_controller *hose,
  572. struct device_node *dev, int primary)
  573. {
  574. int memno = 0;
  575. struct resource *res;
  576. struct of_pci_range range;
  577. struct of_pci_range_parser parser;
  578. printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
  579. dev, primary ? "(primary)" : "");
  580. /* Check for ranges property */
  581. if (of_pci_range_parser_init(&parser, dev))
  582. return;
  583. /* Parse it */
  584. for_each_of_pci_range(&parser, &range) {
  585. /* If we failed translation or got a zero-sized region
  586. * (some FW try to feed us with non sensical zero sized regions
  587. * such as power3 which look like some kind of attempt at exposing
  588. * the VGA memory hole)
  589. */
  590. if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
  591. continue;
  592. /* Act based on address space type */
  593. res = NULL;
  594. switch (range.flags & IORESOURCE_TYPE_BITS) {
  595. case IORESOURCE_IO:
  596. printk(KERN_INFO
  597. " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
  598. range.cpu_addr, range.cpu_addr + range.size - 1,
  599. range.pci_addr);
  600. /* We support only one IO range */
  601. if (hose->pci_io_size) {
  602. printk(KERN_INFO
  603. " \\--> Skipped (too many) !\n");
  604. continue;
  605. }
  606. #ifdef CONFIG_PPC32
  607. /* On 32 bits, limit I/O space to 16MB */
  608. if (range.size > 0x01000000)
  609. range.size = 0x01000000;
  610. /* 32 bits needs to map IOs here */
  611. hose->io_base_virt = ioremap(range.cpu_addr,
  612. range.size);
  613. /* Expect trouble if pci_addr is not 0 */
  614. if (primary)
  615. isa_io_base =
  616. (unsigned long)hose->io_base_virt;
  617. #endif /* CONFIG_PPC32 */
  618. /* pci_io_size and io_base_phys always represent IO
  619. * space starting at 0 so we factor in pci_addr
  620. */
  621. hose->pci_io_size = range.pci_addr + range.size;
  622. hose->io_base_phys = range.cpu_addr - range.pci_addr;
  623. /* Build resource */
  624. res = &hose->io_resource;
  625. range.cpu_addr = range.pci_addr;
  626. break;
  627. case IORESOURCE_MEM:
  628. printk(KERN_INFO
  629. " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
  630. range.cpu_addr, range.cpu_addr + range.size - 1,
  631. range.pci_addr,
  632. (range.flags & IORESOURCE_PREFETCH) ?
  633. "Prefetch" : "");
  634. /* We support only 3 memory ranges */
  635. if (memno >= 3) {
  636. printk(KERN_INFO
  637. " \\--> Skipped (too many) !\n");
  638. continue;
  639. }
  640. /* Handles ISA memory hole space here */
  641. if (range.pci_addr == 0) {
  642. if (primary || isa_mem_base == 0)
  643. isa_mem_base = range.cpu_addr;
  644. hose->isa_mem_phys = range.cpu_addr;
  645. hose->isa_mem_size = range.size;
  646. }
  647. /* Build resource */
  648. hose->mem_offset[memno] = range.cpu_addr -
  649. range.pci_addr;
  650. res = &hose->mem_resources[memno++];
  651. break;
  652. }
  653. if (res != NULL) {
  654. res->name = dev->full_name;
  655. res->flags = range.flags;
  656. res->start = range.cpu_addr;
  657. res->end = range.cpu_addr + range.size - 1;
  658. res->parent = res->child = res->sibling = NULL;
  659. }
  660. }
  661. }
  662. /* Decide whether to display the domain number in /proc */
  663. int pci_proc_domain(struct pci_bus *bus)
  664. {
  665. struct pci_controller *hose = pci_bus_to_host(bus);
  666. if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
  667. return 0;
  668. if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
  669. return hose->global_number != 0;
  670. return 1;
  671. }
  672. int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  673. {
  674. if (ppc_md.pcibios_root_bridge_prepare)
  675. return ppc_md.pcibios_root_bridge_prepare(bridge);
  676. return 0;
  677. }
  678. /* This header fixup will do the resource fixup for all devices as they are
  679. * probed, but not for bridge ranges
  680. */
  681. static void pcibios_fixup_resources(struct pci_dev *dev)
  682. {
  683. struct pci_controller *hose = pci_bus_to_host(dev->bus);
  684. int i;
  685. if (!hose) {
  686. printk(KERN_ERR "No host bridge for PCI dev %s !\n",
  687. pci_name(dev));
  688. return;
  689. }
  690. if (dev->is_virtfn)
  691. return;
  692. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  693. struct resource *res = dev->resource + i;
  694. struct pci_bus_region reg;
  695. if (!res->flags)
  696. continue;
  697. /* If we're going to re-assign everything, we mark all resources
  698. * as unset (and 0-base them). In addition, we mark BARs starting
  699. * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
  700. * since in that case, we don't want to re-assign anything
  701. */
  702. pcibios_resource_to_bus(dev->bus, &reg, res);
  703. if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
  704. (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
  705. /* Only print message if not re-assigning */
  706. if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
  707. pr_debug("PCI:%s Resource %d %pR is unassigned\n",
  708. pci_name(dev), i, res);
  709. res->end -= res->start;
  710. res->start = 0;
  711. res->flags |= IORESOURCE_UNSET;
  712. continue;
  713. }
  714. pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
  715. }
  716. /* Call machine specific resource fixup */
  717. if (ppc_md.pcibios_fixup_resources)
  718. ppc_md.pcibios_fixup_resources(dev);
  719. }
  720. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
  721. /* This function tries to figure out if a bridge resource has been initialized
  722. * by the firmware or not. It doesn't have to be absolutely bullet proof, but
  723. * things go more smoothly when it gets it right. It should covers cases such
  724. * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
  725. */
  726. static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
  727. struct resource *res)
  728. {
  729. struct pci_controller *hose = pci_bus_to_host(bus);
  730. struct pci_dev *dev = bus->self;
  731. resource_size_t offset;
  732. struct pci_bus_region region;
  733. u16 command;
  734. int i;
  735. /* We don't do anything if PCI_PROBE_ONLY is set */
  736. if (pci_has_flag(PCI_PROBE_ONLY))
  737. return 0;
  738. /* Job is a bit different between memory and IO */
  739. if (res->flags & IORESOURCE_MEM) {
  740. pcibios_resource_to_bus(dev->bus, &region, res);
  741. /* If the BAR is non-0 then it's probably been initialized */
  742. if (region.start != 0)
  743. return 0;
  744. /* The BAR is 0, let's check if memory decoding is enabled on
  745. * the bridge. If not, we consider it unassigned
  746. */
  747. pci_read_config_word(dev, PCI_COMMAND, &command);
  748. if ((command & PCI_COMMAND_MEMORY) == 0)
  749. return 1;
  750. /* Memory decoding is enabled and the BAR is 0. If any of the bridge
  751. * resources covers that starting address (0 then it's good enough for
  752. * us for memory space)
  753. */
  754. for (i = 0; i < 3; i++) {
  755. if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
  756. hose->mem_resources[i].start == hose->mem_offset[i])
  757. return 0;
  758. }
  759. /* Well, it starts at 0 and we know it will collide so we may as
  760. * well consider it as unassigned. That covers the Apple case.
  761. */
  762. return 1;
  763. } else {
  764. /* If the BAR is non-0, then we consider it assigned */
  765. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  766. if (((res->start - offset) & 0xfffffffful) != 0)
  767. return 0;
  768. /* Here, we are a bit different than memory as typically IO space
  769. * starting at low addresses -is- valid. What we do instead if that
  770. * we consider as unassigned anything that doesn't have IO enabled
  771. * in the PCI command register, and that's it.
  772. */
  773. pci_read_config_word(dev, PCI_COMMAND, &command);
  774. if (command & PCI_COMMAND_IO)
  775. return 0;
  776. /* It's starting at 0 and IO is disabled in the bridge, consider
  777. * it unassigned
  778. */
  779. return 1;
  780. }
  781. }
  782. /* Fixup resources of a PCI<->PCI bridge */
  783. static void pcibios_fixup_bridge(struct pci_bus *bus)
  784. {
  785. struct resource *res;
  786. int i;
  787. struct pci_dev *dev = bus->self;
  788. pci_bus_for_each_resource(bus, res, i) {
  789. if (!res || !res->flags)
  790. continue;
  791. if (i >= 3 && bus->self->transparent)
  792. continue;
  793. /* If we're going to reassign everything, we can
  794. * shrink the P2P resource to have size as being
  795. * of 0 in order to save space.
  796. */
  797. if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
  798. res->flags |= IORESOURCE_UNSET;
  799. res->start = 0;
  800. res->end = -1;
  801. continue;
  802. }
  803. pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
  804. /* Try to detect uninitialized P2P bridge resources,
  805. * and clear them out so they get re-assigned later
  806. */
  807. if (pcibios_uninitialized_bridge_resource(bus, res)) {
  808. res->flags = 0;
  809. pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
  810. }
  811. }
  812. }
  813. void pcibios_setup_bus_self(struct pci_bus *bus)
  814. {
  815. struct pci_controller *phb;
  816. /* Fix up the bus resources for P2P bridges */
  817. if (bus->self != NULL)
  818. pcibios_fixup_bridge(bus);
  819. /* Platform specific bus fixups. This is currently only used
  820. * by fsl_pci and I'm hoping to get rid of it at some point
  821. */
  822. if (ppc_md.pcibios_fixup_bus)
  823. ppc_md.pcibios_fixup_bus(bus);
  824. /* Setup bus DMA mappings */
  825. phb = pci_bus_to_host(bus);
  826. if (phb->controller_ops.dma_bus_setup)
  827. phb->controller_ops.dma_bus_setup(bus);
  828. }
  829. void pcibios_bus_add_device(struct pci_dev *dev)
  830. {
  831. struct pci_controller *phb;
  832. /* Fixup NUMA node as it may not be setup yet by the generic
  833. * code and is needed by the DMA init
  834. */
  835. set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
  836. /* Hook up default DMA ops */
  837. set_dma_ops(&dev->dev, pci_dma_ops);
  838. dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
  839. /* Additional platform DMA/iommu setup */
  840. phb = pci_bus_to_host(dev->bus);
  841. if (phb->controller_ops.dma_dev_setup)
  842. phb->controller_ops.dma_dev_setup(dev);
  843. /* Read default IRQs and fixup if necessary */
  844. pci_read_irq_line(dev);
  845. if (ppc_md.pci_irq_fixup)
  846. ppc_md.pci_irq_fixup(dev);
  847. if (ppc_md.pcibios_bus_add_device)
  848. ppc_md.pcibios_bus_add_device(dev);
  849. }
  850. int pcibios_add_device(struct pci_dev *dev)
  851. {
  852. #ifdef CONFIG_PCI_IOV
  853. if (ppc_md.pcibios_fixup_sriov)
  854. ppc_md.pcibios_fixup_sriov(dev);
  855. #endif /* CONFIG_PCI_IOV */
  856. return 0;
  857. }
  858. void pcibios_set_master(struct pci_dev *dev)
  859. {
  860. /* No special bus mastering setup handling */
  861. }
  862. void pcibios_fixup_bus(struct pci_bus *bus)
  863. {
  864. /* When called from the generic PCI probe, read PCI<->PCI bridge
  865. * bases. This is -not- called when generating the PCI tree from
  866. * the OF device-tree.
  867. */
  868. pci_read_bridge_bases(bus);
  869. /* Now fixup the bus bus */
  870. pcibios_setup_bus_self(bus);
  871. }
  872. EXPORT_SYMBOL(pcibios_fixup_bus);
  873. static int skip_isa_ioresource_align(struct pci_dev *dev)
  874. {
  875. if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
  876. !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
  877. return 1;
  878. return 0;
  879. }
  880. /*
  881. * We need to avoid collisions with `mirrored' VGA ports
  882. * and other strange ISA hardware, so we always want the
  883. * addresses to be allocated in the 0x000-0x0ff region
  884. * modulo 0x400.
  885. *
  886. * Why? Because some silly external IO cards only decode
  887. * the low 10 bits of the IO address. The 0x00-0xff region
  888. * is reserved for motherboard devices that decode all 16
  889. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  890. * but we want to try to avoid allocating at 0x2900-0x2bff
  891. * which might have be mirrored at 0x0100-0x03ff..
  892. */
  893. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  894. resource_size_t size, resource_size_t align)
  895. {
  896. struct pci_dev *dev = data;
  897. resource_size_t start = res->start;
  898. if (res->flags & IORESOURCE_IO) {
  899. if (skip_isa_ioresource_align(dev))
  900. return start;
  901. if (start & 0x300)
  902. start = (start + 0x3ff) & ~0x3ff;
  903. }
  904. return start;
  905. }
  906. EXPORT_SYMBOL(pcibios_align_resource);
  907. /*
  908. * Reparent resource children of pr that conflict with res
  909. * under res, and make res replace those children.
  910. */
  911. static int reparent_resources(struct resource *parent,
  912. struct resource *res)
  913. {
  914. struct resource *p, **pp;
  915. struct resource **firstpp = NULL;
  916. for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
  917. if (p->end < res->start)
  918. continue;
  919. if (res->end < p->start)
  920. break;
  921. if (p->start < res->start || p->end > res->end)
  922. return -1; /* not completely contained */
  923. if (firstpp == NULL)
  924. firstpp = pp;
  925. }
  926. if (firstpp == NULL)
  927. return -1; /* didn't find any conflicting entries? */
  928. res->parent = parent;
  929. res->child = *firstpp;
  930. res->sibling = *pp;
  931. *firstpp = res;
  932. *pp = NULL;
  933. for (p = res->child; p != NULL; p = p->sibling) {
  934. p->parent = res;
  935. pr_debug("PCI: Reparented %s %pR under %s\n",
  936. p->name, p, res->name);
  937. }
  938. return 0;
  939. }
  940. /*
  941. * Handle resources of PCI devices. If the world were perfect, we could
  942. * just allocate all the resource regions and do nothing more. It isn't.
  943. * On the other hand, we cannot just re-allocate all devices, as it would
  944. * require us to know lots of host bridge internals. So we attempt to
  945. * keep as much of the original configuration as possible, but tweak it
  946. * when it's found to be wrong.
  947. *
  948. * Known BIOS problems we have to work around:
  949. * - I/O or memory regions not configured
  950. * - regions configured, but not enabled in the command register
  951. * - bogus I/O addresses above 64K used
  952. * - expansion ROMs left enabled (this may sound harmless, but given
  953. * the fact the PCI specs explicitly allow address decoders to be
  954. * shared between expansion ROMs and other resource regions, it's
  955. * at least dangerous)
  956. *
  957. * Our solution:
  958. * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  959. * This gives us fixed barriers on where we can allocate.
  960. * (2) Allocate resources for all enabled devices. If there is
  961. * a collision, just mark the resource as unallocated. Also
  962. * disable expansion ROMs during this step.
  963. * (3) Try to allocate resources for disabled devices. If the
  964. * resources were assigned correctly, everything goes well,
  965. * if they weren't, they won't disturb allocation of other
  966. * resources.
  967. * (4) Assign new addresses to resources which were either
  968. * not configured at all or misconfigured. If explicitly
  969. * requested by the user, configure expansion ROM address
  970. * as well.
  971. */
  972. static void pcibios_allocate_bus_resources(struct pci_bus *bus)
  973. {
  974. struct pci_bus *b;
  975. int i;
  976. struct resource *res, *pr;
  977. pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
  978. pci_domain_nr(bus), bus->number);
  979. pci_bus_for_each_resource(bus, res, i) {
  980. if (!res || !res->flags || res->start > res->end || res->parent)
  981. continue;
  982. /* If the resource was left unset at this point, we clear it */
  983. if (res->flags & IORESOURCE_UNSET)
  984. goto clear_resource;
  985. if (bus->parent == NULL)
  986. pr = (res->flags & IORESOURCE_IO) ?
  987. &ioport_resource : &iomem_resource;
  988. else {
  989. pr = pci_find_parent_resource(bus->self, res);
  990. if (pr == res) {
  991. /* this happens when the generic PCI
  992. * code (wrongly) decides that this
  993. * bridge is transparent -- paulus
  994. */
  995. continue;
  996. }
  997. }
  998. pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
  999. bus->self ? pci_name(bus->self) : "PHB", bus->number,
  1000. i, res, pr, (pr && pr->name) ? pr->name : "nil");
  1001. if (pr && !(pr->flags & IORESOURCE_UNSET)) {
  1002. struct pci_dev *dev = bus->self;
  1003. if (request_resource(pr, res) == 0)
  1004. continue;
  1005. /*
  1006. * Must be a conflict with an existing entry.
  1007. * Move that entry (or entries) under the
  1008. * bridge resource and try again.
  1009. */
  1010. if (reparent_resources(pr, res) == 0)
  1011. continue;
  1012. if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
  1013. pci_claim_bridge_resource(dev,
  1014. i + PCI_BRIDGE_RESOURCES) == 0)
  1015. continue;
  1016. }
  1017. pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
  1018. i, bus->number);
  1019. clear_resource:
  1020. /* The resource might be figured out when doing
  1021. * reassignment based on the resources required
  1022. * by the downstream PCI devices. Here we set
  1023. * the size of the resource to be 0 in order to
  1024. * save more space.
  1025. */
  1026. res->start = 0;
  1027. res->end = -1;
  1028. res->flags = 0;
  1029. }
  1030. list_for_each_entry(b, &bus->children, node)
  1031. pcibios_allocate_bus_resources(b);
  1032. }
  1033. static inline void alloc_resource(struct pci_dev *dev, int idx)
  1034. {
  1035. struct resource *pr, *r = &dev->resource[idx];
  1036. pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
  1037. pci_name(dev), idx, r);
  1038. pr = pci_find_parent_resource(dev, r);
  1039. if (!pr || (pr->flags & IORESOURCE_UNSET) ||
  1040. request_resource(pr, r) < 0) {
  1041. printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
  1042. " of device %s, will remap\n", idx, pci_name(dev));
  1043. if (pr)
  1044. pr_debug("PCI: parent is %p: %pR\n", pr, pr);
  1045. /* We'll assign a new address later */
  1046. r->flags |= IORESOURCE_UNSET;
  1047. r->end -= r->start;
  1048. r->start = 0;
  1049. }
  1050. }
  1051. static void __init pcibios_allocate_resources(int pass)
  1052. {
  1053. struct pci_dev *dev = NULL;
  1054. int idx, disabled;
  1055. u16 command;
  1056. struct resource *r;
  1057. for_each_pci_dev(dev) {
  1058. pci_read_config_word(dev, PCI_COMMAND, &command);
  1059. for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
  1060. r = &dev->resource[idx];
  1061. if (r->parent) /* Already allocated */
  1062. continue;
  1063. if (!r->flags || (r->flags & IORESOURCE_UNSET))
  1064. continue; /* Not assigned at all */
  1065. /* We only allocate ROMs on pass 1 just in case they
  1066. * have been screwed up by firmware
  1067. */
  1068. if (idx == PCI_ROM_RESOURCE )
  1069. disabled = 1;
  1070. if (r->flags & IORESOURCE_IO)
  1071. disabled = !(command & PCI_COMMAND_IO);
  1072. else
  1073. disabled = !(command & PCI_COMMAND_MEMORY);
  1074. if (pass == disabled)
  1075. alloc_resource(dev, idx);
  1076. }
  1077. if (pass)
  1078. continue;
  1079. r = &dev->resource[PCI_ROM_RESOURCE];
  1080. if (r->flags) {
  1081. /* Turn the ROM off, leave the resource region,
  1082. * but keep it unregistered.
  1083. */
  1084. u32 reg;
  1085. pci_read_config_dword(dev, dev->rom_base_reg, &reg);
  1086. if (reg & PCI_ROM_ADDRESS_ENABLE) {
  1087. pr_debug("PCI: Switching off ROM of %s\n",
  1088. pci_name(dev));
  1089. r->flags &= ~IORESOURCE_ROM_ENABLE;
  1090. pci_write_config_dword(dev, dev->rom_base_reg,
  1091. reg & ~PCI_ROM_ADDRESS_ENABLE);
  1092. }
  1093. }
  1094. }
  1095. }
  1096. static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
  1097. {
  1098. struct pci_controller *hose = pci_bus_to_host(bus);
  1099. resource_size_t offset;
  1100. struct resource *res, *pres;
  1101. int i;
  1102. pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
  1103. /* Check for IO */
  1104. if (!(hose->io_resource.flags & IORESOURCE_IO))
  1105. goto no_io;
  1106. offset = (unsigned long)hose->io_base_virt - _IO_BASE;
  1107. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  1108. BUG_ON(res == NULL);
  1109. res->name = "Legacy IO";
  1110. res->flags = IORESOURCE_IO;
  1111. res->start = offset;
  1112. res->end = (offset + 0xfff) & 0xfffffffful;
  1113. pr_debug("Candidate legacy IO: %pR\n", res);
  1114. if (request_resource(&hose->io_resource, res)) {
  1115. printk(KERN_DEBUG
  1116. "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
  1117. pci_domain_nr(bus), bus->number, res);
  1118. kfree(res);
  1119. }
  1120. no_io:
  1121. /* Check for memory */
  1122. for (i = 0; i < 3; i++) {
  1123. pres = &hose->mem_resources[i];
  1124. offset = hose->mem_offset[i];
  1125. if (!(pres->flags & IORESOURCE_MEM))
  1126. continue;
  1127. pr_debug("hose mem res: %pR\n", pres);
  1128. if ((pres->start - offset) <= 0xa0000 &&
  1129. (pres->end - offset) >= 0xbffff)
  1130. break;
  1131. }
  1132. if (i >= 3)
  1133. return;
  1134. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  1135. BUG_ON(res == NULL);
  1136. res->name = "Legacy VGA memory";
  1137. res->flags = IORESOURCE_MEM;
  1138. res->start = 0xa0000 + offset;
  1139. res->end = 0xbffff + offset;
  1140. pr_debug("Candidate VGA memory: %pR\n", res);
  1141. if (request_resource(pres, res)) {
  1142. printk(KERN_DEBUG
  1143. "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
  1144. pci_domain_nr(bus), bus->number, res);
  1145. kfree(res);
  1146. }
  1147. }
  1148. void __init pcibios_resource_survey(void)
  1149. {
  1150. struct pci_bus *b;
  1151. /* Allocate and assign resources */
  1152. list_for_each_entry(b, &pci_root_buses, node)
  1153. pcibios_allocate_bus_resources(b);
  1154. if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
  1155. pcibios_allocate_resources(0);
  1156. pcibios_allocate_resources(1);
  1157. }
  1158. /* Before we start assigning unassigned resource, we try to reserve
  1159. * the low IO area and the VGA memory area if they intersect the
  1160. * bus available resources to avoid allocating things on top of them
  1161. */
  1162. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1163. list_for_each_entry(b, &pci_root_buses, node)
  1164. pcibios_reserve_legacy_regions(b);
  1165. }
  1166. /* Now, if the platform didn't decide to blindly trust the firmware,
  1167. * we proceed to assigning things that were left unassigned
  1168. */
  1169. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1170. pr_debug("PCI: Assigning unassigned resources...\n");
  1171. pci_assign_unassigned_resources();
  1172. }
  1173. }
  1174. /* This is used by the PCI hotplug driver to allocate resource
  1175. * of newly plugged busses. We can try to consolidate with the
  1176. * rest of the code later, for now, keep it as-is as our main
  1177. * resource allocation function doesn't deal with sub-trees yet.
  1178. */
  1179. void pcibios_claim_one_bus(struct pci_bus *bus)
  1180. {
  1181. struct pci_dev *dev;
  1182. struct pci_bus *child_bus;
  1183. list_for_each_entry(dev, &bus->devices, bus_list) {
  1184. int i;
  1185. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  1186. struct resource *r = &dev->resource[i];
  1187. if (r->parent || !r->start || !r->flags)
  1188. continue;
  1189. pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
  1190. pci_name(dev), i, r);
  1191. if (pci_claim_resource(dev, i) == 0)
  1192. continue;
  1193. pci_claim_bridge_resource(dev, i);
  1194. }
  1195. }
  1196. list_for_each_entry(child_bus, &bus->children, node)
  1197. pcibios_claim_one_bus(child_bus);
  1198. }
  1199. EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
  1200. /* pcibios_finish_adding_to_bus
  1201. *
  1202. * This is to be called by the hotplug code after devices have been
  1203. * added to a bus, this include calling it for a PHB that is just
  1204. * being added
  1205. */
  1206. void pcibios_finish_adding_to_bus(struct pci_bus *bus)
  1207. {
  1208. pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
  1209. pci_domain_nr(bus), bus->number);
  1210. /* Allocate bus and devices resources */
  1211. pcibios_allocate_bus_resources(bus);
  1212. pcibios_claim_one_bus(bus);
  1213. if (!pci_has_flag(PCI_PROBE_ONLY)) {
  1214. if (bus->self)
  1215. pci_assign_unassigned_bridge_resources(bus->self);
  1216. else
  1217. pci_assign_unassigned_bus_resources(bus);
  1218. }
  1219. /* Add new devices to global lists. Register in proc, sysfs. */
  1220. pci_bus_add_devices(bus);
  1221. }
  1222. EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
  1223. int pcibios_enable_device(struct pci_dev *dev, int mask)
  1224. {
  1225. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  1226. if (phb->controller_ops.enable_device_hook)
  1227. if (!phb->controller_ops.enable_device_hook(dev))
  1228. return -EINVAL;
  1229. return pci_enable_resources(dev, mask);
  1230. }
  1231. void pcibios_disable_device(struct pci_dev *dev)
  1232. {
  1233. struct pci_controller *phb = pci_bus_to_host(dev->bus);
  1234. if (phb->controller_ops.disable_device)
  1235. phb->controller_ops.disable_device(dev);
  1236. }
  1237. resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
  1238. {
  1239. return (unsigned long) hose->io_base_virt - _IO_BASE;
  1240. }
  1241. static void pcibios_setup_phb_resources(struct pci_controller *hose,
  1242. struct list_head *resources)
  1243. {
  1244. struct resource *res;
  1245. resource_size_t offset;
  1246. int i;
  1247. /* Hookup PHB IO resource */
  1248. res = &hose->io_resource;
  1249. if (!res->flags) {
  1250. pr_debug("PCI: I/O resource not set for host"
  1251. " bridge %pOF (domain %d)\n",
  1252. hose->dn, hose->global_number);
  1253. } else {
  1254. offset = pcibios_io_space_offset(hose);
  1255. pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
  1256. res, (unsigned long long)offset);
  1257. pci_add_resource_offset(resources, res, offset);
  1258. }
  1259. /* Hookup PHB Memory resources */
  1260. for (i = 0; i < 3; ++i) {
  1261. res = &hose->mem_resources[i];
  1262. if (!res->flags)
  1263. continue;
  1264. offset = hose->mem_offset[i];
  1265. pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
  1266. res, (unsigned long long)offset);
  1267. pci_add_resource_offset(resources, res, offset);
  1268. }
  1269. }
  1270. /*
  1271. * Null PCI config access functions, for the case when we can't
  1272. * find a hose.
  1273. */
  1274. #define NULL_PCI_OP(rw, size, type) \
  1275. static int \
  1276. null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
  1277. { \
  1278. return PCIBIOS_DEVICE_NOT_FOUND; \
  1279. }
  1280. static int
  1281. null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  1282. int len, u32 *val)
  1283. {
  1284. return PCIBIOS_DEVICE_NOT_FOUND;
  1285. }
  1286. static int
  1287. null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
  1288. int len, u32 val)
  1289. {
  1290. return PCIBIOS_DEVICE_NOT_FOUND;
  1291. }
  1292. static struct pci_ops null_pci_ops =
  1293. {
  1294. .read = null_read_config,
  1295. .write = null_write_config,
  1296. };
  1297. /*
  1298. * These functions are used early on before PCI scanning is done
  1299. * and all of the pci_dev and pci_bus structures have been created.
  1300. */
  1301. static struct pci_bus *
  1302. fake_pci_bus(struct pci_controller *hose, int busnr)
  1303. {
  1304. static struct pci_bus bus;
  1305. if (hose == NULL) {
  1306. printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
  1307. }
  1308. bus.number = busnr;
  1309. bus.sysdata = hose;
  1310. bus.ops = hose? hose->ops: &null_pci_ops;
  1311. return &bus;
  1312. }
  1313. #define EARLY_PCI_OP(rw, size, type) \
  1314. int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
  1315. int devfn, int offset, type value) \
  1316. { \
  1317. return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
  1318. devfn, offset, value); \
  1319. }
  1320. EARLY_PCI_OP(read, byte, u8 *)
  1321. EARLY_PCI_OP(read, word, u16 *)
  1322. EARLY_PCI_OP(read, dword, u32 *)
  1323. EARLY_PCI_OP(write, byte, u8)
  1324. EARLY_PCI_OP(write, word, u16)
  1325. EARLY_PCI_OP(write, dword, u32)
  1326. int early_find_capability(struct pci_controller *hose, int bus, int devfn,
  1327. int cap)
  1328. {
  1329. return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
  1330. }
  1331. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  1332. {
  1333. struct pci_controller *hose = bus->sysdata;
  1334. return of_node_get(hose->dn);
  1335. }
  1336. /**
  1337. * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
  1338. * @hose: Pointer to the PCI host controller instance structure
  1339. */
  1340. void pcibios_scan_phb(struct pci_controller *hose)
  1341. {
  1342. LIST_HEAD(resources);
  1343. struct pci_bus *bus;
  1344. struct device_node *node = hose->dn;
  1345. int mode;
  1346. pr_debug("PCI: Scanning PHB %pOF\n", node);
  1347. /* Get some IO space for the new PHB */
  1348. pcibios_setup_phb_io_space(hose);
  1349. /* Wire up PHB bus resources */
  1350. pcibios_setup_phb_resources(hose, &resources);
  1351. hose->busn.start = hose->first_busno;
  1352. hose->busn.end = hose->last_busno;
  1353. hose->busn.flags = IORESOURCE_BUS;
  1354. pci_add_resource(&resources, &hose->busn);
  1355. /* Create an empty bus for the toplevel */
  1356. bus = pci_create_root_bus(hose->parent, hose->first_busno,
  1357. hose->ops, hose, &resources);
  1358. if (bus == NULL) {
  1359. pr_err("Failed to create bus for PCI domain %04x\n",
  1360. hose->global_number);
  1361. pci_free_resource_list(&resources);
  1362. return;
  1363. }
  1364. hose->bus = bus;
  1365. /* Get probe mode and perform scan */
  1366. mode = PCI_PROBE_NORMAL;
  1367. if (node && hose->controller_ops.probe_mode)
  1368. mode = hose->controller_ops.probe_mode(bus);
  1369. pr_debug(" probe mode: %d\n", mode);
  1370. if (mode == PCI_PROBE_DEVTREE)
  1371. of_scan_bus(node, bus);
  1372. if (mode == PCI_PROBE_NORMAL) {
  1373. pci_bus_update_busn_res_end(bus, 255);
  1374. hose->last_busno = pci_scan_child_bus(bus);
  1375. pci_bus_update_busn_res_end(bus, hose->last_busno);
  1376. }
  1377. /* Platform gets a chance to do some global fixups before
  1378. * we proceed to resource allocation
  1379. */
  1380. if (ppc_md.pcibios_fixup_phb)
  1381. ppc_md.pcibios_fixup_phb(hose);
  1382. /* Configure PCI Express settings */
  1383. if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
  1384. struct pci_bus *child;
  1385. list_for_each_entry(child, &bus->children, node)
  1386. pcie_bus_configure_settings(child);
  1387. }
  1388. }
  1389. EXPORT_SYMBOL_GPL(pcibios_scan_phb);
  1390. static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
  1391. {
  1392. int i, class = dev->class >> 8;
  1393. /* When configured as agent, programing interface = 1 */
  1394. int prog_if = dev->class & 0xf;
  1395. if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
  1396. class == PCI_CLASS_BRIDGE_OTHER) &&
  1397. (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
  1398. (prog_if == 0) &&
  1399. (dev->bus->parent == NULL)) {
  1400. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1401. dev->resource[i].start = 0;
  1402. dev->resource[i].end = 0;
  1403. dev->resource[i].flags = 0;
  1404. }
  1405. }
  1406. }
  1407. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
  1408. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
  1409. static int __init discover_phbs(void)
  1410. {
  1411. if (ppc_md.discover_phbs)
  1412. ppc_md.discover_phbs();
  1413. return 0;
  1414. }
  1415. core_initcall(discover_phbs);