l2cr_6xx.S 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. L2CR functions
  4. Copyright © 1997-1998 by PowerLogix R & D, Inc.
  5. */
  6. /*
  7. Thur, Dec. 12, 1998.
  8. - First public release, contributed by PowerLogix.
  9. ***********
  10. Sat, Aug. 7, 1999.
  11. - Terry: Made sure code disabled interrupts before running. (Previously
  12. it was assumed interrupts were already disabled).
  13. - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
  14. instead of 2MB. (Prob. only 3 is necessary).
  15. - Terry: Updated for workaround to HID0[DPM] processor bug
  16. during global invalidates.
  17. ***********
  18. Thu, July 13, 2000.
  19. - Terry: Added isync to correct for an errata.
  20. 22 August 2001.
  21. - DanM: Finally added the 7450 patch I've had for the past
  22. several months. The L2CR is similar, but I'm going
  23. to assume the user of this functions knows what they
  24. are doing.
  25. Author: Terry Greeniaus (tgree@phys.ualberta.ca)
  26. Please e-mail updates to this file to me, thanks!
  27. */
  28. #include <asm/processor.h>
  29. #include <asm/cputable.h>
  30. #include <asm/ppc_asm.h>
  31. #include <asm/cache.h>
  32. #include <asm/page.h>
  33. #include <asm/feature-fixups.h>
  34. /* Usage:
  35. When setting the L2CR register, you must do a few special
  36. things. If you are enabling the cache, you must perform a
  37. global invalidate. If you are disabling the cache, you must
  38. flush the cache contents first. This routine takes care of
  39. doing these things. When first enabling the cache, make sure
  40. you pass in the L2CR you want, as well as passing in the
  41. global invalidate bit set. A global invalidate will only be
  42. performed if the L2I bit is set in applyThis. When enabling
  43. the cache, you should also set the L2E bit in applyThis. If
  44. you want to modify the L2CR contents after the cache has been
  45. enabled, the recommended procedure is to first call
  46. __setL2CR(0) to disable the cache and then call it again with
  47. the new values for L2CR. Examples:
  48. _setL2CR(0) - disables the cache
  49. _setL2CR(0xB3A04000) - enables my G3 upgrade card:
  50. - L2E set to turn on the cache
  51. - L2SIZ set to 1MB
  52. - L2CLK set to 1:1
  53. - L2RAM set to pipelined synchronous late-write
  54. - L2I set to perform a global invalidation
  55. - L2OH set to 0.5 nS
  56. - L2DF set because this upgrade card
  57. requires it
  58. A similar call should work for your card. You need to know
  59. the correct setting for your card and then place them in the
  60. fields I have outlined above. Other fields support optional
  61. features, such as L2DO which caches only data, or L2TS which
  62. causes cache pushes from the L1 cache to go to the L2 cache
  63. instead of to main memory.
  64. IMPORTANT:
  65. Starting with the 7450, the bits in this register have moved
  66. or behave differently. The Enable, Parity Enable, Size,
  67. and L2 Invalidate are the only bits that have not moved.
  68. The size is read-only for these processors with internal L2
  69. cache, and the invalidate is a control as well as status.
  70. -- Dan
  71. */
  72. /*
  73. * Summary: this procedure ignores the L2I bit in the value passed in,
  74. * flushes the cache if it was already enabled, always invalidates the
  75. * cache, then enables the cache if the L2E bit is set in the value
  76. * passed in.
  77. * -- paulus.
  78. */
  79. _GLOBAL(_set_L2CR)
  80. /* Make sure this is a 750 or 7400 chip */
  81. BEGIN_FTR_SECTION
  82. li r3,-1
  83. blr
  84. END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
  85. mflr r9
  86. /* Stop DST streams */
  87. BEGIN_FTR_SECTION
  88. DSSALL
  89. sync
  90. END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  91. /* Turn off interrupts and data relocation. */
  92. mfmsr r7 /* Save MSR in r7 */
  93. rlwinm r4,r7,0,17,15
  94. rlwinm r4,r4,0,28,26 /* Turn off DR bit */
  95. sync
  96. mtmsr r4
  97. isync
  98. /* Before we perform the global invalidation, we must disable dynamic
  99. * power management via HID0[DPM] to work around a processor bug where
  100. * DPM can possibly interfere with the state machine in the processor
  101. * that invalidates the L2 cache tags.
  102. */
  103. mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
  104. rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
  105. sync
  106. mtspr SPRN_HID0,r4 /* Disable DPM */
  107. sync
  108. /* Get the current enable bit of the L2CR into r4 */
  109. mfspr r4,SPRN_L2CR
  110. /* Tweak some bits */
  111. rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
  112. rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
  113. rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
  114. /* Check to see if we need to flush */
  115. rlwinm. r4,r4,0,0,0
  116. beq 2f
  117. /* Flush the cache. First, read the first 4MB of memory (physical) to
  118. * put new data in the cache. (Actually we only need
  119. * the size of the L2 cache plus the size of the L1 cache, but 4MB will
  120. * cover everything just to be safe).
  121. */
  122. /**** Might be a good idea to set L2DO here - to prevent instructions
  123. from getting into the cache. But since we invalidate
  124. the next time we enable the cache it doesn't really matter.
  125. Don't do this unless you accommodate all processor variations.
  126. The bit moved on the 7450.....
  127. ****/
  128. BEGIN_FTR_SECTION
  129. /* Disable L2 prefetch on some 745x and try to ensure
  130. * L2 prefetch engines are idle. As explained by errata
  131. * text, we can't be sure they are, we just hope very hard
  132. * that well be enough (sic !). At least I noticed Apple
  133. * doesn't even bother doing the dcbf's here...
  134. */
  135. mfspr r4,SPRN_MSSCR0
  136. rlwinm r4,r4,0,0,29
  137. sync
  138. mtspr SPRN_MSSCR0,r4
  139. sync
  140. isync
  141. lis r4,KERNELBASE@h
  142. dcbf 0,r4
  143. dcbf 0,r4
  144. dcbf 0,r4
  145. dcbf 0,r4
  146. END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
  147. /* TODO: use HW flush assist when available */
  148. lis r4,0x0002
  149. mtctr r4
  150. li r4,0
  151. 1:
  152. lwzx r0,0,r4
  153. addi r4,r4,32 /* Go to start of next cache line */
  154. bdnz 1b
  155. isync
  156. /* Now, flush the first 4MB of memory */
  157. lis r4,0x0002
  158. mtctr r4
  159. li r4,0
  160. sync
  161. 1:
  162. dcbf 0,r4
  163. addi r4,r4,32 /* Go to start of next cache line */
  164. bdnz 1b
  165. 2:
  166. /* Set up the L2CR configuration bits (and switch L2 off) */
  167. /* CPU errata: Make sure the mtspr below is already in the
  168. * L1 icache
  169. */
  170. b 20f
  171. .balign L1_CACHE_BYTES
  172. 22:
  173. sync
  174. mtspr SPRN_L2CR,r3
  175. sync
  176. b 23f
  177. 20:
  178. b 21f
  179. 21: sync
  180. isync
  181. b 22b
  182. 23:
  183. /* Perform a global invalidation */
  184. oris r3,r3,0x0020
  185. sync
  186. mtspr SPRN_L2CR,r3
  187. sync
  188. isync /* For errata */
  189. BEGIN_FTR_SECTION
  190. /* On the 7450, we wait for the L2I bit to clear......
  191. */
  192. 10: mfspr r3,SPRN_L2CR
  193. andis. r4,r3,0x0020
  194. bne 10b
  195. b 11f
  196. END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
  197. /* Wait for the invalidation to complete */
  198. 3: mfspr r3,SPRN_L2CR
  199. rlwinm. r4,r3,0,31,31
  200. bne 3b
  201. 11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
  202. sync
  203. mtspr SPRN_L2CR,r3
  204. sync
  205. /* See if we need to enable the cache */
  206. cmplwi r5,0
  207. beq 4f
  208. /* Enable the cache */
  209. oris r3,r3,0x8000
  210. mtspr SPRN_L2CR,r3
  211. sync
  212. /* Enable L2 HW prefetch on 744x/745x */
  213. BEGIN_FTR_SECTION
  214. mfspr r3,SPRN_MSSCR0
  215. ori r3,r3,3
  216. sync
  217. mtspr SPRN_MSSCR0,r3
  218. sync
  219. isync
  220. END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
  221. 4:
  222. /* Restore HID0[DPM] to whatever it was before */
  223. sync
  224. mtspr 1008,r8
  225. sync
  226. /* Restore MSR (restores EE and DR bits to original state) */
  227. mtmsr r7
  228. isync
  229. mtlr r9
  230. blr
  231. _GLOBAL(_get_L2CR)
  232. /* Return the L2CR contents */
  233. li r3,0
  234. BEGIN_FTR_SECTION
  235. mfspr r3,SPRN_L2CR
  236. END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
  237. blr
  238. /*
  239. * Here is a similar routine for dealing with the L3 cache
  240. * on the 745x family of chips
  241. */
  242. _GLOBAL(_set_L3CR)
  243. /* Make sure this is a 745x chip */
  244. BEGIN_FTR_SECTION
  245. li r3,-1
  246. blr
  247. END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
  248. /* Turn off interrupts and data relocation. */
  249. mfmsr r7 /* Save MSR in r7 */
  250. rlwinm r4,r7,0,17,15
  251. rlwinm r4,r4,0,28,26 /* Turn off DR bit */
  252. sync
  253. mtmsr r4
  254. isync
  255. /* Stop DST streams */
  256. DSSALL
  257. sync
  258. /* Get the current enable bit of the L3CR into r4 */
  259. mfspr r4,SPRN_L3CR
  260. /* Tweak some bits */
  261. rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
  262. rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
  263. rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
  264. rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
  265. /* Check to see if we need to flush */
  266. rlwinm. r4,r4,0,0,0
  267. beq 2f
  268. /* Flush the cache.
  269. */
  270. /* TODO: use HW flush assist */
  271. lis r4,0x0008
  272. mtctr r4
  273. li r4,0
  274. 1:
  275. lwzx r0,0,r4
  276. dcbf 0,r4
  277. addi r4,r4,32 /* Go to start of next cache line */
  278. bdnz 1b
  279. 2:
  280. /* Set up the L3CR configuration bits (and switch L3 off) */
  281. sync
  282. mtspr SPRN_L3CR,r3
  283. sync
  284. oris r3,r3,L3CR_L3RES@h /* Set reserved bit 5 */
  285. mtspr SPRN_L3CR,r3
  286. sync
  287. oris r3,r3,L3CR_L3CLKEN@h /* Set clken */
  288. mtspr SPRN_L3CR,r3
  289. sync
  290. /* Wait for stabilize */
  291. li r0,256
  292. mtctr r0
  293. 1: bdnz 1b
  294. /* Perform a global invalidation */
  295. ori r3,r3,0x0400
  296. sync
  297. mtspr SPRN_L3CR,r3
  298. sync
  299. isync
  300. /* We wait for the L3I bit to clear...... */
  301. 10: mfspr r3,SPRN_L3CR
  302. andi. r4,r3,0x0400
  303. bne 10b
  304. /* Clear CLKEN */
  305. rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
  306. mtspr SPRN_L3CR,r3
  307. sync
  308. /* Wait for stabilize */
  309. li r0,256
  310. mtctr r0
  311. 1: bdnz 1b
  312. /* See if we need to enable the cache */
  313. cmplwi r5,0
  314. beq 4f
  315. /* Enable the cache */
  316. oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
  317. mtspr SPRN_L3CR,r3
  318. sync
  319. /* Wait for stabilize */
  320. li r0,256
  321. mtctr r0
  322. 1: bdnz 1b
  323. /* Restore MSR (restores EE and DR bits to original state) */
  324. 4:
  325. mtmsr r7
  326. isync
  327. blr
  328. _GLOBAL(_get_L3CR)
  329. /* Return the L3CR contents */
  330. li r3,0
  331. BEGIN_FTR_SECTION
  332. mfspr r3,SPRN_L3CR
  333. END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
  334. blr
  335. /* --- End of PowerLogix code ---
  336. */
  337. /* flush_disable_L1() - Flush and disable L1 cache
  338. *
  339. * clobbers r0, r3, ctr, cr0
  340. * Must be called with interrupts disabled and MMU enabled.
  341. */
  342. _GLOBAL(__flush_disable_L1)
  343. /* Stop pending alitvec streams and memory accesses */
  344. BEGIN_FTR_SECTION
  345. DSSALL
  346. END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  347. sync
  348. /* Load counter to 0x4000 cache lines (512k) and
  349. * load cache with datas
  350. */
  351. li r3,0x4000 /* 512kB / 32B */
  352. mtctr r3
  353. lis r3,KERNELBASE@h
  354. 1:
  355. lwz r0,0(r3)
  356. addi r3,r3,0x0020 /* Go to start of next cache line */
  357. bdnz 1b
  358. isync
  359. sync
  360. /* Now flush those cache lines */
  361. li r3,0x4000 /* 512kB / 32B */
  362. mtctr r3
  363. lis r3,KERNELBASE@h
  364. 1:
  365. dcbf 0,r3
  366. addi r3,r3,0x0020 /* Go to start of next cache line */
  367. bdnz 1b
  368. sync
  369. /* We can now disable the L1 cache (HID0:DCE, HID0:ICE) */
  370. mfspr r3,SPRN_HID0
  371. rlwinm r3,r3,0,18,15
  372. mtspr SPRN_HID0,r3
  373. sync
  374. isync
  375. blr
  376. /* inval_enable_L1 - Invalidate and enable L1 cache
  377. *
  378. * Assumes L1 is already disabled and MSR:EE is off
  379. *
  380. * clobbers r3
  381. */
  382. _GLOBAL(__inval_enable_L1)
  383. /* Enable and then Flash inval the instruction & data cache */
  384. mfspr r3,SPRN_HID0
  385. ori r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
  386. sync
  387. isync
  388. mtspr SPRN_HID0,r3
  389. xori r3,r3, HID0_ICFI|HID0_DCI
  390. mtspr SPRN_HID0,r3
  391. sync
  392. blr
  393. _ASM_NOKPROBE_SYMBOL(__inval_enable_L1)