entry_64.S 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * PowerPC version
  4. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  5. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  6. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  7. * Adapted for Power Macintosh by Paul Mackerras.
  8. * Low-level exception handlers and MMU support
  9. * rewritten by Paul Mackerras.
  10. * Copyright (C) 1996 Paul Mackerras.
  11. * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  12. *
  13. * This file contains the system call entry code, context switch
  14. * code, and exception/interrupt return code for PowerPC.
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <asm/cache.h>
  19. #include <asm/unistd.h>
  20. #include <asm/processor.h>
  21. #include <asm/page.h>
  22. #include <asm/mmu.h>
  23. #include <asm/thread_info.h>
  24. #include <asm/code-patching-asm.h>
  25. #include <asm/ppc_asm.h>
  26. #include <asm/asm-offsets.h>
  27. #include <asm/cputable.h>
  28. #include <asm/firmware.h>
  29. #include <asm/bug.h>
  30. #include <asm/ptrace.h>
  31. #include <asm/irqflags.h>
  32. #include <asm/hw_irq.h>
  33. #include <asm/context_tracking.h>
  34. #include <asm/tm.h>
  35. #include <asm/ppc-opcode.h>
  36. #include <asm/barrier.h>
  37. #include <asm/export.h>
  38. #include <asm/asm-compat.h>
  39. #ifdef CONFIG_PPC_BOOK3S
  40. #include <asm/exception-64s.h>
  41. #else
  42. #include <asm/exception-64e.h>
  43. #endif
  44. #include <asm/feature-fixups.h>
  45. #include <asm/kup.h>
  46. /*
  47. * System calls.
  48. */
  49. .section ".toc","aw"
  50. SYS_CALL_TABLE:
  51. .tc sys_call_table[TC],sys_call_table
  52. #ifdef CONFIG_COMPAT
  53. COMPAT_SYS_CALL_TABLE:
  54. .tc compat_sys_call_table[TC],compat_sys_call_table
  55. #endif
  56. /* This value is used to mark exception frames on the stack. */
  57. exception_marker:
  58. .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
  59. .section ".text"
  60. .align 7
  61. #ifdef CONFIG_PPC_BOOK3S
  62. .macro system_call_vectored name trapnr
  63. .globl system_call_vectored_\name
  64. system_call_vectored_\name:
  65. _ASM_NOKPROBE_SYMBOL(system_call_vectored_\name)
  66. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  67. BEGIN_FTR_SECTION
  68. extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
  69. bne .Ltabort_syscall
  70. END_FTR_SECTION_IFSET(CPU_FTR_TM)
  71. #endif
  72. SCV_INTERRUPT_TO_KERNEL
  73. mr r10,r1
  74. ld r1,PACAKSAVE(r13)
  75. std r10,0(r1)
  76. std r11,_NIP(r1)
  77. std r12,_MSR(r1)
  78. std r0,GPR0(r1)
  79. std r10,GPR1(r1)
  80. std r2,GPR2(r1)
  81. ld r2,PACATOC(r13)
  82. mfcr r12
  83. li r11,0
  84. /* Can we avoid saving r3-r8 in common case? */
  85. std r3,GPR3(r1)
  86. std r4,GPR4(r1)
  87. std r5,GPR5(r1)
  88. std r6,GPR6(r1)
  89. std r7,GPR7(r1)
  90. std r8,GPR8(r1)
  91. /* Zero r9-r12, this should only be required when restoring all GPRs */
  92. std r11,GPR9(r1)
  93. std r11,GPR10(r1)
  94. std r11,GPR11(r1)
  95. std r11,GPR12(r1)
  96. std r9,GPR13(r1)
  97. SAVE_NVGPRS(r1)
  98. std r11,_XER(r1)
  99. std r11,_LINK(r1)
  100. std r11,_CTR(r1)
  101. li r11,\trapnr
  102. std r11,_TRAP(r1)
  103. std r12,_CCR(r1)
  104. std r3,ORIG_GPR3(r1)
  105. addi r10,r1,STACK_FRAME_OVERHEAD
  106. ld r11,exception_marker@toc(r2)
  107. std r11,-16(r10) /* "regshere" marker */
  108. BEGIN_FTR_SECTION
  109. HMT_MEDIUM
  110. END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
  111. /*
  112. * RECONCILE_IRQ_STATE without calling trace_hardirqs_off(), which
  113. * would clobber syscall parameters. Also we always enter with IRQs
  114. * enabled and nothing pending. system_call_exception() will call
  115. * trace_hardirqs_off().
  116. *
  117. * scv enters with MSR[EE]=1, so don't set PACA_IRQ_HARD_DIS. The
  118. * entry vector already sets PACAIRQSOFTMASK to IRQS_ALL_DISABLED.
  119. */
  120. /* Calling convention has r9 = orig r0, r10 = regs */
  121. mr r9,r0
  122. bl system_call_exception
  123. .Lsyscall_vectored_\name\()_exit:
  124. addi r4,r1,STACK_FRAME_OVERHEAD
  125. li r5,1 /* scv */
  126. bl syscall_exit_prepare
  127. ld r2,_CCR(r1)
  128. ld r4,_NIP(r1)
  129. ld r5,_MSR(r1)
  130. BEGIN_FTR_SECTION
  131. stdcx. r0,0,r1 /* to clear the reservation */
  132. END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  133. BEGIN_FTR_SECTION
  134. HMT_MEDIUM_LOW
  135. END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
  136. cmpdi r3,0
  137. bne .Lsyscall_vectored_\name\()_restore_regs
  138. /* rfscv returns with LR->NIA and CTR->MSR */
  139. mtlr r4
  140. mtctr r5
  141. /* Could zero these as per ABI, but we may consider a stricter ABI
  142. * which preserves these if libc implementations can benefit, so
  143. * restore them for now until further measurement is done. */
  144. ld r0,GPR0(r1)
  145. ld r4,GPR4(r1)
  146. ld r5,GPR5(r1)
  147. ld r6,GPR6(r1)
  148. ld r7,GPR7(r1)
  149. ld r8,GPR8(r1)
  150. /* Zero volatile regs that may contain sensitive kernel data */
  151. li r9,0
  152. li r10,0
  153. li r11,0
  154. li r12,0
  155. mtspr SPRN_XER,r0
  156. /*
  157. * We don't need to restore AMR on the way back to userspace for KUAP.
  158. * The value of AMR only matters while we're in the kernel.
  159. */
  160. mtcr r2
  161. ld r2,GPR2(r1)
  162. ld r3,GPR3(r1)
  163. ld r13,GPR13(r1)
  164. ld r1,GPR1(r1)
  165. RFSCV_TO_USER
  166. b . /* prevent speculative execution */
  167. .Lsyscall_vectored_\name\()_restore_regs:
  168. li r3,0
  169. mtmsrd r3,1
  170. mtspr SPRN_SRR0,r4
  171. mtspr SPRN_SRR1,r5
  172. ld r3,_CTR(r1)
  173. ld r4,_LINK(r1)
  174. ld r5,_XER(r1)
  175. REST_NVGPRS(r1)
  176. ld r0,GPR0(r1)
  177. mtcr r2
  178. mtctr r3
  179. mtlr r4
  180. mtspr SPRN_XER,r5
  181. REST_10GPRS(2, r1)
  182. REST_2GPRS(12, r1)
  183. ld r1,GPR1(r1)
  184. RFI_TO_USER
  185. .endm
  186. system_call_vectored common 0x3000
  187. /*
  188. * We instantiate another entry copy for the SIGILL variant, with TRAP=0x7ff0
  189. * which is tested by system_call_exception when r0 is -1 (as set by vector
  190. * entry code).
  191. */
  192. system_call_vectored sigill 0x7ff0
  193. /*
  194. * Entered via kernel return set up by kernel/sstep.c, must match entry regs
  195. */
  196. .globl system_call_vectored_emulate
  197. system_call_vectored_emulate:
  198. _ASM_NOKPROBE_SYMBOL(system_call_vectored_emulate)
  199. li r10,IRQS_ALL_DISABLED
  200. stb r10,PACAIRQSOFTMASK(r13)
  201. b system_call_vectored_common
  202. #endif
  203. .balign IFETCH_ALIGN_BYTES
  204. .globl system_call_common
  205. system_call_common:
  206. _ASM_NOKPROBE_SYMBOL(system_call_common)
  207. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  208. BEGIN_FTR_SECTION
  209. extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
  210. bne .Ltabort_syscall
  211. END_FTR_SECTION_IFSET(CPU_FTR_TM)
  212. #endif
  213. mr r10,r1
  214. ld r1,PACAKSAVE(r13)
  215. std r10,0(r1)
  216. std r11,_NIP(r1)
  217. std r12,_MSR(r1)
  218. std r0,GPR0(r1)
  219. std r10,GPR1(r1)
  220. std r2,GPR2(r1)
  221. #ifdef CONFIG_PPC_FSL_BOOK3E
  222. START_BTB_FLUSH_SECTION
  223. BTB_FLUSH(r10)
  224. END_BTB_FLUSH_SECTION
  225. #endif
  226. ld r2,PACATOC(r13)
  227. mfcr r12
  228. li r11,0
  229. /* Can we avoid saving r3-r8 in common case? */
  230. std r3,GPR3(r1)
  231. std r4,GPR4(r1)
  232. std r5,GPR5(r1)
  233. std r6,GPR6(r1)
  234. std r7,GPR7(r1)
  235. std r8,GPR8(r1)
  236. /* Zero r9-r12, this should only be required when restoring all GPRs */
  237. std r11,GPR9(r1)
  238. std r11,GPR10(r1)
  239. std r11,GPR11(r1)
  240. std r11,GPR12(r1)
  241. std r9,GPR13(r1)
  242. SAVE_NVGPRS(r1)
  243. std r11,_XER(r1)
  244. std r11,_CTR(r1)
  245. mflr r10
  246. /*
  247. * This clears CR0.SO (bit 28), which is the error indication on
  248. * return from this system call.
  249. */
  250. rldimi r12,r11,28,(63-28)
  251. li r11,0xc00
  252. std r10,_LINK(r1)
  253. std r11,_TRAP(r1)
  254. std r12,_CCR(r1)
  255. std r3,ORIG_GPR3(r1)
  256. addi r10,r1,STACK_FRAME_OVERHEAD
  257. ld r11,exception_marker@toc(r2)
  258. std r11,-16(r10) /* "regshere" marker */
  259. /*
  260. * RECONCILE_IRQ_STATE without calling trace_hardirqs_off(), which
  261. * would clobber syscall parameters. Also we always enter with IRQs
  262. * enabled and nothing pending. system_call_exception() will call
  263. * trace_hardirqs_off().
  264. */
  265. li r11,IRQS_ALL_DISABLED
  266. li r12,PACA_IRQ_HARD_DIS
  267. stb r11,PACAIRQSOFTMASK(r13)
  268. stb r12,PACAIRQHAPPENED(r13)
  269. /* Calling convention has r9 = orig r0, r10 = regs */
  270. mr r9,r0
  271. bl system_call_exception
  272. .Lsyscall_exit:
  273. addi r4,r1,STACK_FRAME_OVERHEAD
  274. li r5,0 /* !scv */
  275. bl syscall_exit_prepare
  276. ld r2,_CCR(r1)
  277. ld r4,_NIP(r1)
  278. ld r5,_MSR(r1)
  279. ld r6,_LINK(r1)
  280. BEGIN_FTR_SECTION
  281. stdcx. r0,0,r1 /* to clear the reservation */
  282. END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  283. mtspr SPRN_SRR0,r4
  284. mtspr SPRN_SRR1,r5
  285. mtlr r6
  286. cmpdi r3,0
  287. bne .Lsyscall_restore_regs
  288. /* Zero volatile regs that may contain sensitive kernel data */
  289. li r0,0
  290. li r4,0
  291. li r5,0
  292. li r6,0
  293. li r7,0
  294. li r8,0
  295. li r9,0
  296. li r10,0
  297. li r11,0
  298. li r12,0
  299. mtctr r0
  300. mtspr SPRN_XER,r0
  301. .Lsyscall_restore_regs_cont:
  302. BEGIN_FTR_SECTION
  303. HMT_MEDIUM_LOW
  304. END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
  305. /*
  306. * We don't need to restore AMR on the way back to userspace for KUAP.
  307. * The value of AMR only matters while we're in the kernel.
  308. */
  309. mtcr r2
  310. ld r2,GPR2(r1)
  311. ld r3,GPR3(r1)
  312. ld r13,GPR13(r1)
  313. ld r1,GPR1(r1)
  314. RFI_TO_USER
  315. b . /* prevent speculative execution */
  316. .Lsyscall_restore_regs:
  317. ld r3,_CTR(r1)
  318. ld r4,_XER(r1)
  319. REST_NVGPRS(r1)
  320. mtctr r3
  321. mtspr SPRN_XER,r4
  322. ld r0,GPR0(r1)
  323. REST_8GPRS(4, r1)
  324. ld r12,GPR12(r1)
  325. b .Lsyscall_restore_regs_cont
  326. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  327. .Ltabort_syscall:
  328. /* Firstly we need to enable TM in the kernel */
  329. mfmsr r10
  330. li r9, 1
  331. rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
  332. mtmsrd r10, 0
  333. /* tabort, this dooms the transaction, nothing else */
  334. li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
  335. TABORT(R9)
  336. /*
  337. * Return directly to userspace. We have corrupted user register state,
  338. * but userspace will never see that register state. Execution will
  339. * resume after the tbegin of the aborted transaction with the
  340. * checkpointed register state.
  341. */
  342. li r9, MSR_RI
  343. andc r10, r10, r9
  344. mtmsrd r10, 1
  345. mtspr SPRN_SRR0, r11
  346. mtspr SPRN_SRR1, r12
  347. RFI_TO_USER
  348. b . /* prevent speculative execution */
  349. #endif
  350. #ifdef CONFIG_PPC_BOOK3S
  351. _GLOBAL(ret_from_fork_scv)
  352. bl schedule_tail
  353. REST_NVGPRS(r1)
  354. li r3,0 /* fork() return value */
  355. b .Lsyscall_vectored_common_exit
  356. #endif
  357. _GLOBAL(ret_from_fork)
  358. bl schedule_tail
  359. REST_NVGPRS(r1)
  360. li r3,0 /* fork() return value */
  361. b .Lsyscall_exit
  362. _GLOBAL(ret_from_kernel_thread)
  363. bl schedule_tail
  364. REST_NVGPRS(r1)
  365. mtctr r14
  366. mr r3,r15
  367. #ifdef PPC64_ELF_ABI_v2
  368. mr r12,r14
  369. #endif
  370. bctrl
  371. li r3,0
  372. b .Lsyscall_exit
  373. #ifdef CONFIG_PPC_BOOK3E
  374. /* Save non-volatile GPRs, if not already saved. */
  375. _GLOBAL(save_nvgprs)
  376. ld r11,_TRAP(r1)
  377. andi. r0,r11,1
  378. beqlr-
  379. SAVE_NVGPRS(r1)
  380. clrrdi r0,r11,1
  381. std r0,_TRAP(r1)
  382. blr
  383. _ASM_NOKPROBE_SYMBOL(save_nvgprs);
  384. #endif
  385. #ifdef CONFIG_PPC_BOOK3S_64
  386. #define FLUSH_COUNT_CACHE \
  387. 1: nop; \
  388. patch_site 1b, patch__call_flush_branch_caches1; \
  389. 1: nop; \
  390. patch_site 1b, patch__call_flush_branch_caches2; \
  391. 1: nop; \
  392. patch_site 1b, patch__call_flush_branch_caches3
  393. .macro nops number
  394. .rept \number
  395. nop
  396. .endr
  397. .endm
  398. .balign 32
  399. .global flush_branch_caches
  400. flush_branch_caches:
  401. /* Save LR into r9 */
  402. mflr r9
  403. // Flush the link stack
  404. .rept 64
  405. bl .+4
  406. .endr
  407. b 1f
  408. nops 6
  409. .balign 32
  410. /* Restore LR */
  411. 1: mtlr r9
  412. // If we're just flushing the link stack, return here
  413. 3: nop
  414. patch_site 3b patch__flush_link_stack_return
  415. li r9,0x7fff
  416. mtctr r9
  417. PPC_BCCTR_FLUSH
  418. 2: nop
  419. patch_site 2b patch__flush_count_cache_return
  420. nops 3
  421. .rept 278
  422. .balign 32
  423. PPC_BCCTR_FLUSH
  424. nops 7
  425. .endr
  426. blr
  427. #else
  428. #define FLUSH_COUNT_CACHE
  429. #endif /* CONFIG_PPC_BOOK3S_64 */
  430. /*
  431. * This routine switches between two different tasks. The process
  432. * state of one is saved on its kernel stack. Then the state
  433. * of the other is restored from its kernel stack. The memory
  434. * management hardware is updated to the second process's state.
  435. * Finally, we can return to the second process, via interrupt_return.
  436. * On entry, r3 points to the THREAD for the current task, r4
  437. * points to the THREAD for the new task.
  438. *
  439. * Note: there are two ways to get to the "going out" portion
  440. * of this code; either by coming in via the entry (_switch)
  441. * or via "fork" which must set up an environment equivalent
  442. * to the "_switch" path. If you change this you'll have to change
  443. * the fork code also.
  444. *
  445. * The code which creates the new task context is in 'copy_thread'
  446. * in arch/powerpc/kernel/process.c
  447. */
  448. .align 7
  449. _GLOBAL(_switch)
  450. mflr r0
  451. std r0,16(r1)
  452. stdu r1,-SWITCH_FRAME_SIZE(r1)
  453. /* r3-r13 are caller saved -- Cort */
  454. SAVE_NVGPRS(r1)
  455. std r0,_NIP(r1) /* Return to switch caller */
  456. mfcr r23
  457. std r23,_CCR(r1)
  458. std r1,KSP(r3) /* Set old stack pointer */
  459. kuap_check_amr r9, r10
  460. FLUSH_COUNT_CACHE /* Clobbers r9, ctr */
  461. /*
  462. * On SMP kernels, care must be taken because a task may be
  463. * scheduled off CPUx and on to CPUy. Memory ordering must be
  464. * considered.
  465. *
  466. * Cacheable stores on CPUx will be visible when the task is
  467. * scheduled on CPUy by virtue of the core scheduler barriers
  468. * (see "Notes on Program-Order guarantees on SMP systems." in
  469. * kernel/sched/core.c).
  470. *
  471. * Uncacheable stores in the case of involuntary preemption must
  472. * be taken care of. The smp_mb__after_spinlock() in __schedule()
  473. * is implemented as hwsync on powerpc, which orders MMIO too. So
  474. * long as there is an hwsync in the context switch path, it will
  475. * be executed on the source CPU after the task has performed
  476. * all MMIO ops on that CPU, and on the destination CPU before the
  477. * task performs any MMIO ops there.
  478. */
  479. /*
  480. * The kernel context switch path must contain a spin_lock,
  481. * which contains larx/stcx, which will clear any reservation
  482. * of the task being switched.
  483. */
  484. #ifdef CONFIG_PPC_BOOK3S
  485. /* Cancel all explict user streams as they will have no use after context
  486. * switch and will stop the HW from creating streams itself
  487. */
  488. DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
  489. #endif
  490. addi r6,r4,-THREAD /* Convert THREAD to 'current' */
  491. std r6,PACACURRENT(r13) /* Set new 'current' */
  492. #if defined(CONFIG_STACKPROTECTOR)
  493. ld r6, TASK_CANARY(r6)
  494. std r6, PACA_CANARY(r13)
  495. #endif
  496. ld r8,KSP(r4) /* new stack pointer */
  497. #ifdef CONFIG_PPC_BOOK3S_64
  498. BEGIN_MMU_FTR_SECTION
  499. b 2f
  500. END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
  501. BEGIN_FTR_SECTION
  502. clrrdi r6,r8,28 /* get its ESID */
  503. clrrdi r9,r1,28 /* get current sp ESID */
  504. FTR_SECTION_ELSE
  505. clrrdi r6,r8,40 /* get its 1T ESID */
  506. clrrdi r9,r1,40 /* get current sp 1T ESID */
  507. ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
  508. clrldi. r0,r6,2 /* is new ESID c00000000? */
  509. cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
  510. cror eq,4*cr1+eq,eq
  511. beq 2f /* if yes, don't slbie it */
  512. /* Bolt in the new stack SLB entry */
  513. ld r7,KSP_VSID(r4) /* Get new stack's VSID */
  514. oris r0,r6,(SLB_ESID_V)@h
  515. ori r0,r0,(SLB_NUM_BOLTED-1)@l
  516. BEGIN_FTR_SECTION
  517. li r9,MMU_SEGSIZE_1T /* insert B field */
  518. oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
  519. rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
  520. END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
  521. /* Update the last bolted SLB. No write barriers are needed
  522. * here, provided we only update the current CPU's SLB shadow
  523. * buffer.
  524. */
  525. ld r9,PACA_SLBSHADOWPTR(r13)
  526. li r12,0
  527. std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
  528. li r12,SLBSHADOW_STACKVSID
  529. STDX_BE r7,r12,r9 /* Save VSID */
  530. li r12,SLBSHADOW_STACKESID
  531. STDX_BE r0,r12,r9 /* Save ESID */
  532. /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
  533. * we have 1TB segments, the only CPUs known to have the errata
  534. * only support less than 1TB of system memory and we'll never
  535. * actually hit this code path.
  536. */
  537. isync
  538. slbie r6
  539. BEGIN_FTR_SECTION
  540. slbie r6 /* Workaround POWER5 < DD2.1 issue */
  541. END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
  542. slbmte r7,r0
  543. isync
  544. 2:
  545. #endif /* CONFIG_PPC_BOOK3S_64 */
  546. clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
  547. /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
  548. because we don't need to leave the 288-byte ABI gap at the
  549. top of the kernel stack. */
  550. addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
  551. /*
  552. * PMU interrupts in radix may come in here. They will use r1, not
  553. * PACAKSAVE, so this stack switch will not cause a problem. They
  554. * will store to the process stack, which may then be migrated to
  555. * another CPU. However the rq lock release on this CPU paired with
  556. * the rq lock acquire on the new CPU before the stack becomes
  557. * active on the new CPU, will order those stores.
  558. */
  559. mr r1,r8 /* start using new stack pointer */
  560. std r7,PACAKSAVE(r13)
  561. ld r6,_CCR(r1)
  562. mtcrf 0xFF,r6
  563. /* r3-r13 are destroyed -- Cort */
  564. REST_NVGPRS(r1)
  565. /* convert old thread to its task_struct for return value */
  566. addi r3,r3,-THREAD
  567. ld r7,_NIP(r1) /* Return to _switch caller in new task */
  568. mtlr r7
  569. addi r1,r1,SWITCH_FRAME_SIZE
  570. blr
  571. #ifdef CONFIG_PPC_BOOK3S
  572. /*
  573. * If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not
  574. * touched, no exit work created, then this can be used.
  575. */
  576. .balign IFETCH_ALIGN_BYTES
  577. .globl fast_interrupt_return
  578. fast_interrupt_return:
  579. _ASM_NOKPROBE_SYMBOL(fast_interrupt_return)
  580. kuap_check_amr r3, r4
  581. ld r5,_MSR(r1)
  582. andi. r0,r5,MSR_PR
  583. bne .Lfast_user_interrupt_return
  584. kuap_restore_amr r3, r4
  585. andi. r0,r5,MSR_RI
  586. li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
  587. bne+ .Lfast_kernel_interrupt_return
  588. addi r3,r1,STACK_FRAME_OVERHEAD
  589. bl unrecoverable_exception
  590. b . /* should not get here */
  591. .balign IFETCH_ALIGN_BYTES
  592. .globl interrupt_return
  593. interrupt_return:
  594. _ASM_NOKPROBE_SYMBOL(interrupt_return)
  595. ld r4,_MSR(r1)
  596. andi. r0,r4,MSR_PR
  597. beq .Lkernel_interrupt_return
  598. addi r3,r1,STACK_FRAME_OVERHEAD
  599. bl interrupt_exit_user_prepare
  600. cmpdi r3,0
  601. bne- .Lrestore_nvgprs
  602. .Lfast_user_interrupt_return:
  603. ld r11,_NIP(r1)
  604. ld r12,_MSR(r1)
  605. BEGIN_FTR_SECTION
  606. ld r10,_PPR(r1)
  607. mtspr SPRN_PPR,r10
  608. END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
  609. mtspr SPRN_SRR0,r11
  610. mtspr SPRN_SRR1,r12
  611. BEGIN_FTR_SECTION
  612. stdcx. r0,0,r1 /* to clear the reservation */
  613. FTR_SECTION_ELSE
  614. ldarx r0,0,r1
  615. ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  616. ld r3,_CCR(r1)
  617. ld r4,_LINK(r1)
  618. ld r5,_CTR(r1)
  619. ld r6,_XER(r1)
  620. li r0,0
  621. REST_4GPRS(7, r1)
  622. REST_2GPRS(11, r1)
  623. REST_GPR(13, r1)
  624. mtcr r3
  625. mtlr r4
  626. mtctr r5
  627. mtspr SPRN_XER,r6
  628. REST_4GPRS(2, r1)
  629. REST_GPR(6, r1)
  630. REST_GPR(0, r1)
  631. REST_GPR(1, r1)
  632. RFI_TO_USER
  633. b . /* prevent speculative execution */
  634. .Lrestore_nvgprs:
  635. REST_NVGPRS(r1)
  636. b .Lfast_user_interrupt_return
  637. .balign IFETCH_ALIGN_BYTES
  638. .Lkernel_interrupt_return:
  639. addi r3,r1,STACK_FRAME_OVERHEAD
  640. bl interrupt_exit_kernel_prepare
  641. .Lfast_kernel_interrupt_return:
  642. cmpdi cr1,r3,0
  643. ld r11,_NIP(r1)
  644. ld r12,_MSR(r1)
  645. mtspr SPRN_SRR0,r11
  646. mtspr SPRN_SRR1,r12
  647. BEGIN_FTR_SECTION
  648. stdcx. r0,0,r1 /* to clear the reservation */
  649. FTR_SECTION_ELSE
  650. ldarx r0,0,r1
  651. ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  652. ld r3,_LINK(r1)
  653. ld r4,_CTR(r1)
  654. ld r5,_XER(r1)
  655. ld r6,_CCR(r1)
  656. li r0,0
  657. REST_4GPRS(7, r1)
  658. REST_2GPRS(11, r1)
  659. mtlr r3
  660. mtctr r4
  661. mtspr SPRN_XER,r5
  662. /*
  663. * Leaving a stale exception_marker on the stack can confuse
  664. * the reliable stack unwinder later on. Clear it.
  665. */
  666. std r0,STACK_FRAME_OVERHEAD-16(r1)
  667. REST_4GPRS(2, r1)
  668. bne- cr1,1f /* emulate stack store */
  669. mtcr r6
  670. REST_GPR(6, r1)
  671. REST_GPR(0, r1)
  672. REST_GPR(1, r1)
  673. RFI_TO_KERNEL
  674. b . /* prevent speculative execution */
  675. 1: /*
  676. * Emulate stack store with update. New r1 value was already calculated
  677. * and updated in our interrupt regs by emulate_loadstore, but we can't
  678. * store the previous value of r1 to the stack before re-loading our
  679. * registers from it, otherwise they could be clobbered. Use
  680. * PACA_EXGEN as temporary storage to hold the store data, as
  681. * interrupts are disabled here so it won't be clobbered.
  682. */
  683. mtcr r6
  684. std r9,PACA_EXGEN+0(r13)
  685. addi r9,r1,INT_FRAME_SIZE /* get original r1 */
  686. REST_GPR(6, r1)
  687. REST_GPR(0, r1)
  688. REST_GPR(1, r1)
  689. std r9,0(r1) /* perform store component of stdu */
  690. ld r9,PACA_EXGEN+0(r13)
  691. RFI_TO_KERNEL
  692. b . /* prevent speculative execution */
  693. #endif /* CONFIG_PPC_BOOK3S */
  694. #ifdef CONFIG_PPC_RTAS
  695. /*
  696. * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
  697. * called with the MMU off.
  698. *
  699. * In addition, we need to be in 32b mode, at least for now.
  700. *
  701. * Note: r3 is an input parameter to rtas, so don't trash it...
  702. */
  703. _GLOBAL(enter_rtas)
  704. mflr r0
  705. std r0,16(r1)
  706. stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
  707. /* Because RTAS is running in 32b mode, it clobbers the high order half
  708. * of all registers that it saves. We therefore save those registers
  709. * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
  710. */
  711. SAVE_GPR(2, r1) /* Save the TOC */
  712. SAVE_GPR(13, r1) /* Save paca */
  713. SAVE_NVGPRS(r1) /* Save the non-volatiles */
  714. mfcr r4
  715. std r4,_CCR(r1)
  716. mfctr r5
  717. std r5,_CTR(r1)
  718. mfspr r6,SPRN_XER
  719. std r6,_XER(r1)
  720. mfdar r7
  721. std r7,_DAR(r1)
  722. mfdsisr r8
  723. std r8,_DSISR(r1)
  724. /* Temporary workaround to clear CR until RTAS can be modified to
  725. * ignore all bits.
  726. */
  727. li r0,0
  728. mtcr r0
  729. #ifdef CONFIG_BUG
  730. /* There is no way it is acceptable to get here with interrupts enabled,
  731. * check it with the asm equivalent of WARN_ON
  732. */
  733. lbz r0,PACAIRQSOFTMASK(r13)
  734. 1: tdeqi r0,IRQS_ENABLED
  735. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
  736. #endif
  737. /* Hard-disable interrupts */
  738. mfmsr r6
  739. rldicl r7,r6,48,1
  740. rotldi r7,r7,16
  741. mtmsrd r7,1
  742. /* Unfortunately, the stack pointer and the MSR are also clobbered,
  743. * so they are saved in the PACA which allows us to restore
  744. * our original state after RTAS returns.
  745. */
  746. std r1,PACAR1(r13)
  747. std r6,PACASAVEDMSR(r13)
  748. /* Setup our real return addr */
  749. LOAD_REG_ADDR(r4,rtas_return_loc)
  750. clrldi r4,r4,2 /* convert to realmode address */
  751. mtlr r4
  752. li r0,0
  753. ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
  754. andc r0,r6,r0
  755. li r9,1
  756. rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
  757. ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
  758. andc r6,r0,r9
  759. __enter_rtas:
  760. sync /* disable interrupts so SRR0/1 */
  761. mtmsrd r0 /* don't get trashed */
  762. LOAD_REG_ADDR(r4, rtas)
  763. ld r5,RTASENTRY(r4) /* get the rtas->entry value */
  764. ld r4,RTASBASE(r4) /* get the rtas->base value */
  765. mtspr SPRN_SRR0,r5
  766. mtspr SPRN_SRR1,r6
  767. RFI_TO_KERNEL
  768. b . /* prevent speculative execution */
  769. rtas_return_loc:
  770. FIXUP_ENDIAN
  771. /*
  772. * Clear RI and set SF before anything.
  773. */
  774. mfmsr r6
  775. li r0,MSR_RI
  776. andc r6,r6,r0
  777. sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
  778. or r6,r6,r0
  779. sync
  780. mtmsrd r6
  781. /* relocation is off at this point */
  782. GET_PACA(r4)
  783. clrldi r4,r4,2 /* convert to realmode address */
  784. bcl 20,31,$+4
  785. 0: mflr r3
  786. ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
  787. ld r1,PACAR1(r4) /* Restore our SP */
  788. ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
  789. mtspr SPRN_SRR0,r3
  790. mtspr SPRN_SRR1,r4
  791. RFI_TO_KERNEL
  792. b . /* prevent speculative execution */
  793. _ASM_NOKPROBE_SYMBOL(__enter_rtas)
  794. _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
  795. .align 3
  796. 1: .8byte rtas_restore_regs
  797. rtas_restore_regs:
  798. /* relocation is on at this point */
  799. REST_GPR(2, r1) /* Restore the TOC */
  800. REST_GPR(13, r1) /* Restore paca */
  801. REST_NVGPRS(r1) /* Restore the non-volatiles */
  802. GET_PACA(r13)
  803. ld r4,_CCR(r1)
  804. mtcr r4
  805. ld r5,_CTR(r1)
  806. mtctr r5
  807. ld r6,_XER(r1)
  808. mtspr SPRN_XER,r6
  809. ld r7,_DAR(r1)
  810. mtdar r7
  811. ld r8,_DSISR(r1)
  812. mtdsisr r8
  813. addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
  814. ld r0,16(r1) /* get return address */
  815. mtlr r0
  816. blr /* return to caller */
  817. #endif /* CONFIG_PPC_RTAS */
  818. _GLOBAL(enter_prom)
  819. mflr r0
  820. std r0,16(r1)
  821. stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
  822. /* Because PROM is running in 32b mode, it clobbers the high order half
  823. * of all registers that it saves. We therefore save those registers
  824. * PROM might touch to the stack. (r0, r3-r13 are caller saved)
  825. */
  826. SAVE_GPR(2, r1)
  827. SAVE_GPR(13, r1)
  828. SAVE_NVGPRS(r1)
  829. mfcr r10
  830. mfmsr r11
  831. std r10,_CCR(r1)
  832. std r11,_MSR(r1)
  833. /* Put PROM address in SRR0 */
  834. mtsrr0 r4
  835. /* Setup our trampoline return addr in LR */
  836. bcl 20,31,$+4
  837. 0: mflr r4
  838. addi r4,r4,(1f - 0b)
  839. mtlr r4
  840. /* Prepare a 32-bit mode big endian MSR
  841. */
  842. #ifdef CONFIG_PPC_BOOK3E
  843. rlwinm r11,r11,0,1,31
  844. mtsrr1 r11
  845. rfi
  846. #else /* CONFIG_PPC_BOOK3E */
  847. LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
  848. andc r11,r11,r12
  849. mtsrr1 r11
  850. RFI_TO_KERNEL
  851. #endif /* CONFIG_PPC_BOOK3E */
  852. 1: /* Return from OF */
  853. FIXUP_ENDIAN
  854. /* Just make sure that r1 top 32 bits didn't get
  855. * corrupt by OF
  856. */
  857. rldicl r1,r1,0,32
  858. /* Restore the MSR (back to 64 bits) */
  859. ld r0,_MSR(r1)
  860. MTMSRD(r0)
  861. isync
  862. /* Restore other registers */
  863. REST_GPR(2, r1)
  864. REST_GPR(13, r1)
  865. REST_NVGPRS(r1)
  866. ld r4,_CCR(r1)
  867. mtcr r4
  868. addi r1,r1,SWITCH_FRAME_SIZE
  869. ld r0,16(r1)
  870. mtlr r0
  871. blr