eeh_pe.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * The file intends to implement PE based on the information from
  4. * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
  5. * All the PEs should be organized as hierarchy tree. The first level
  6. * of the tree will be associated to existing PHBs since the particular
  7. * PE is only meaningful in one PHB domain.
  8. *
  9. * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/export.h>
  13. #include <linux/gfp.h>
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/string.h>
  17. #include <asm/pci-bridge.h>
  18. #include <asm/ppc-pci.h>
  19. static int eeh_pe_aux_size = 0;
  20. static LIST_HEAD(eeh_phb_pe);
  21. /**
  22. * eeh_set_pe_aux_size - Set PE auxillary data size
  23. * @size: PE auxillary data size
  24. *
  25. * Set PE auxillary data size
  26. */
  27. void eeh_set_pe_aux_size(int size)
  28. {
  29. if (size < 0)
  30. return;
  31. eeh_pe_aux_size = size;
  32. }
  33. /**
  34. * eeh_pe_alloc - Allocate PE
  35. * @phb: PCI controller
  36. * @type: PE type
  37. *
  38. * Allocate PE instance dynamically.
  39. */
  40. static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
  41. {
  42. struct eeh_pe *pe;
  43. size_t alloc_size;
  44. alloc_size = sizeof(struct eeh_pe);
  45. if (eeh_pe_aux_size) {
  46. alloc_size = ALIGN(alloc_size, cache_line_size());
  47. alloc_size += eeh_pe_aux_size;
  48. }
  49. /* Allocate PHB PE */
  50. pe = kzalloc(alloc_size, GFP_KERNEL);
  51. if (!pe) return NULL;
  52. /* Initialize PHB PE */
  53. pe->type = type;
  54. pe->phb = phb;
  55. INIT_LIST_HEAD(&pe->child_list);
  56. INIT_LIST_HEAD(&pe->edevs);
  57. pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
  58. cache_line_size());
  59. return pe;
  60. }
  61. /**
  62. * eeh_phb_pe_create - Create PHB PE
  63. * @phb: PCI controller
  64. *
  65. * The function should be called while the PHB is detected during
  66. * system boot or PCI hotplug in order to create PHB PE.
  67. */
  68. int eeh_phb_pe_create(struct pci_controller *phb)
  69. {
  70. struct eeh_pe *pe;
  71. /* Allocate PHB PE */
  72. pe = eeh_pe_alloc(phb, EEH_PE_PHB);
  73. if (!pe) {
  74. pr_err("%s: out of memory!\n", __func__);
  75. return -ENOMEM;
  76. }
  77. /* Put it into the list */
  78. list_add_tail(&pe->child, &eeh_phb_pe);
  79. pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
  80. return 0;
  81. }
  82. /**
  83. * eeh_wait_state - Wait for PE state
  84. * @pe: EEH PE
  85. * @max_wait: maximal period in millisecond
  86. *
  87. * Wait for the state of associated PE. It might take some time
  88. * to retrieve the PE's state.
  89. */
  90. int eeh_wait_state(struct eeh_pe *pe, int max_wait)
  91. {
  92. int ret;
  93. int mwait;
  94. /*
  95. * According to PAPR, the state of PE might be temporarily
  96. * unavailable. Under the circumstance, we have to wait
  97. * for indicated time determined by firmware. The maximal
  98. * wait time is 5 minutes, which is acquired from the original
  99. * EEH implementation. Also, the original implementation
  100. * also defined the minimal wait time as 1 second.
  101. */
  102. #define EEH_STATE_MIN_WAIT_TIME (1000)
  103. #define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
  104. while (1) {
  105. ret = eeh_ops->get_state(pe, &mwait);
  106. if (ret != EEH_STATE_UNAVAILABLE)
  107. return ret;
  108. if (max_wait <= 0) {
  109. pr_warn("%s: Timeout when getting PE's state (%d)\n",
  110. __func__, max_wait);
  111. return EEH_STATE_NOT_SUPPORT;
  112. }
  113. if (mwait < EEH_STATE_MIN_WAIT_TIME) {
  114. pr_warn("%s: Firmware returned bad wait value %d\n",
  115. __func__, mwait);
  116. mwait = EEH_STATE_MIN_WAIT_TIME;
  117. } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
  118. pr_warn("%s: Firmware returned too long wait value %d\n",
  119. __func__, mwait);
  120. mwait = EEH_STATE_MAX_WAIT_TIME;
  121. }
  122. msleep(min(mwait, max_wait));
  123. max_wait -= mwait;
  124. }
  125. }
  126. /**
  127. * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
  128. * @phb: PCI controller
  129. *
  130. * The overall PEs form hierarchy tree. The first layer of the
  131. * hierarchy tree is composed of PHB PEs. The function is used
  132. * to retrieve the corresponding PHB PE according to the given PHB.
  133. */
  134. struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
  135. {
  136. struct eeh_pe *pe;
  137. list_for_each_entry(pe, &eeh_phb_pe, child) {
  138. /*
  139. * Actually, we needn't check the type since
  140. * the PE for PHB has been determined when that
  141. * was created.
  142. */
  143. if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
  144. return pe;
  145. }
  146. return NULL;
  147. }
  148. /**
  149. * eeh_pe_next - Retrieve the next PE in the tree
  150. * @pe: current PE
  151. * @root: root PE
  152. *
  153. * The function is used to retrieve the next PE in the
  154. * hierarchy PE tree.
  155. */
  156. struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
  157. {
  158. struct list_head *next = pe->child_list.next;
  159. if (next == &pe->child_list) {
  160. while (1) {
  161. if (pe == root)
  162. return NULL;
  163. next = pe->child.next;
  164. if (next != &pe->parent->child_list)
  165. break;
  166. pe = pe->parent;
  167. }
  168. }
  169. return list_entry(next, struct eeh_pe, child);
  170. }
  171. /**
  172. * eeh_pe_traverse - Traverse PEs in the specified PHB
  173. * @root: root PE
  174. * @fn: callback
  175. * @flag: extra parameter to callback
  176. *
  177. * The function is used to traverse the specified PE and its
  178. * child PEs. The traversing is to be terminated once the
  179. * callback returns something other than NULL, or no more PEs
  180. * to be traversed.
  181. */
  182. void *eeh_pe_traverse(struct eeh_pe *root,
  183. eeh_pe_traverse_func fn, void *flag)
  184. {
  185. struct eeh_pe *pe;
  186. void *ret;
  187. eeh_for_each_pe(root, pe) {
  188. ret = fn(pe, flag);
  189. if (ret) return ret;
  190. }
  191. return NULL;
  192. }
  193. /**
  194. * eeh_pe_dev_traverse - Traverse the devices from the PE
  195. * @root: EEH PE
  196. * @fn: function callback
  197. * @flag: extra parameter to callback
  198. *
  199. * The function is used to traverse the devices of the specified
  200. * PE and its child PEs.
  201. */
  202. void eeh_pe_dev_traverse(struct eeh_pe *root,
  203. eeh_edev_traverse_func fn, void *flag)
  204. {
  205. struct eeh_pe *pe;
  206. struct eeh_dev *edev, *tmp;
  207. if (!root) {
  208. pr_warn("%s: Invalid PE %p\n",
  209. __func__, root);
  210. return;
  211. }
  212. /* Traverse root PE */
  213. eeh_for_each_pe(root, pe)
  214. eeh_pe_for_each_dev(pe, edev, tmp)
  215. fn(edev, flag);
  216. }
  217. /**
  218. * __eeh_pe_get - Check the PE address
  219. *
  220. * For one particular PE, it can be identified by PE address
  221. * or tranditional BDF address. BDF address is composed of
  222. * Bus/Device/Function number. The extra data referred by flag
  223. * indicates which type of address should be used.
  224. */
  225. static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
  226. {
  227. int *target_pe = flag;
  228. /* PHB PEs are special and should be ignored */
  229. if (pe->type & EEH_PE_PHB)
  230. return NULL;
  231. if (*target_pe == pe->addr)
  232. return pe;
  233. return NULL;
  234. }
  235. /**
  236. * eeh_pe_get - Search PE based on the given address
  237. * @phb: PCI controller
  238. * @pe_no: PE number
  239. *
  240. * Search the corresponding PE based on the specified address which
  241. * is included in the eeh device. The function is used to check if
  242. * the associated PE has been created against the PE address. It's
  243. * notable that the PE address has 2 format: traditional PE address
  244. * which is composed of PCI bus/device/function number, or unified
  245. * PE address.
  246. */
  247. struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no)
  248. {
  249. struct eeh_pe *root = eeh_phb_pe_get(phb);
  250. return eeh_pe_traverse(root, __eeh_pe_get, &pe_no);
  251. }
  252. /**
  253. * eeh_pe_tree_insert - Add EEH device to parent PE
  254. * @edev: EEH device
  255. * @new_pe_parent: PE to create additional PEs under
  256. *
  257. * Add EEH device to the PE in edev->pe_config_addr. If a PE already
  258. * exists with that address then @edev is added to that PE. Otherwise
  259. * a new PE is created and inserted into the PE tree as a child of
  260. * @new_pe_parent.
  261. *
  262. * If @new_pe_parent is NULL then the new PE will be inserted under
  263. * directly under the the PHB.
  264. */
  265. int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent)
  266. {
  267. struct pci_controller *hose = edev->controller;
  268. struct eeh_pe *pe, *parent;
  269. /*
  270. * Search the PE has been existing or not according
  271. * to the PE address. If that has been existing, the
  272. * PE should be composed of PCI bus and its subordinate
  273. * components.
  274. */
  275. pe = eeh_pe_get(hose, edev->pe_config_addr);
  276. if (pe) {
  277. if (pe->type & EEH_PE_INVALID) {
  278. list_add_tail(&edev->entry, &pe->edevs);
  279. edev->pe = pe;
  280. /*
  281. * We're running to here because of PCI hotplug caused by
  282. * EEH recovery. We need clear EEH_PE_INVALID until the top.
  283. */
  284. parent = pe;
  285. while (parent) {
  286. if (!(parent->type & EEH_PE_INVALID))
  287. break;
  288. parent->type &= ~EEH_PE_INVALID;
  289. parent = parent->parent;
  290. }
  291. eeh_edev_dbg(edev, "Added to existing PE (parent: PE#%x)\n",
  292. pe->parent->addr);
  293. } else {
  294. /* Mark the PE as type of PCI bus */
  295. pe->type = EEH_PE_BUS;
  296. edev->pe = pe;
  297. /* Put the edev to PE */
  298. list_add_tail(&edev->entry, &pe->edevs);
  299. eeh_edev_dbg(edev, "Added to bus PE\n");
  300. }
  301. return 0;
  302. }
  303. /* Create a new EEH PE */
  304. if (edev->physfn)
  305. pe = eeh_pe_alloc(hose, EEH_PE_VF);
  306. else
  307. pe = eeh_pe_alloc(hose, EEH_PE_DEVICE);
  308. if (!pe) {
  309. pr_err("%s: out of memory!\n", __func__);
  310. return -ENOMEM;
  311. }
  312. pe->addr = edev->pe_config_addr;
  313. /*
  314. * Put the new EEH PE into hierarchy tree. If the parent
  315. * can't be found, the newly created PE will be attached
  316. * to PHB directly. Otherwise, we have to associate the
  317. * PE with its parent.
  318. */
  319. if (!new_pe_parent) {
  320. new_pe_parent = eeh_phb_pe_get(hose);
  321. if (!new_pe_parent) {
  322. pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
  323. __func__, hose->global_number);
  324. edev->pe = NULL;
  325. kfree(pe);
  326. return -EEXIST;
  327. }
  328. }
  329. /* link new PE into the tree */
  330. pe->parent = new_pe_parent;
  331. list_add_tail(&pe->child, &new_pe_parent->child_list);
  332. /*
  333. * Put the newly created PE into the child list and
  334. * link the EEH device accordingly.
  335. */
  336. list_add_tail(&edev->entry, &pe->edevs);
  337. edev->pe = pe;
  338. eeh_edev_dbg(edev, "Added to new (parent: PE#%x)\n",
  339. new_pe_parent->addr);
  340. return 0;
  341. }
  342. /**
  343. * eeh_pe_tree_remove - Remove one EEH device from the associated PE
  344. * @edev: EEH device
  345. *
  346. * The PE hierarchy tree might be changed when doing PCI hotplug.
  347. * Also, the PCI devices or buses could be removed from the system
  348. * during EEH recovery. So we have to call the function remove the
  349. * corresponding PE accordingly if necessary.
  350. */
  351. int eeh_pe_tree_remove(struct eeh_dev *edev)
  352. {
  353. struct eeh_pe *pe, *parent, *child;
  354. bool keep, recover;
  355. int cnt;
  356. pe = eeh_dev_to_pe(edev);
  357. if (!pe) {
  358. eeh_edev_dbg(edev, "No PE found for device.\n");
  359. return -EEXIST;
  360. }
  361. /* Remove the EEH device */
  362. edev->pe = NULL;
  363. list_del(&edev->entry);
  364. /*
  365. * Check if the parent PE includes any EEH devices.
  366. * If not, we should delete that. Also, we should
  367. * delete the parent PE if it doesn't have associated
  368. * child PEs and EEH devices.
  369. */
  370. while (1) {
  371. parent = pe->parent;
  372. /* PHB PEs should never be removed */
  373. if (pe->type & EEH_PE_PHB)
  374. break;
  375. /*
  376. * XXX: KEEP is set while resetting a PE. I don't think it's
  377. * ever set without RECOVERING also being set. I could
  378. * be wrong though so catch that with a WARN.
  379. */
  380. keep = !!(pe->state & EEH_PE_KEEP);
  381. recover = !!(pe->state & EEH_PE_RECOVERING);
  382. WARN_ON(keep && !recover);
  383. if (!keep && !recover) {
  384. if (list_empty(&pe->edevs) &&
  385. list_empty(&pe->child_list)) {
  386. list_del(&pe->child);
  387. kfree(pe);
  388. } else {
  389. break;
  390. }
  391. } else {
  392. /*
  393. * Mark the PE as invalid. At the end of the recovery
  394. * process any invalid PEs will be garbage collected.
  395. *
  396. * We need to delay the free()ing of them since we can
  397. * remove edev's while traversing the PE tree which
  398. * might trigger the removal of a PE and we can't
  399. * deal with that (yet).
  400. */
  401. if (list_empty(&pe->edevs)) {
  402. cnt = 0;
  403. list_for_each_entry(child, &pe->child_list, child) {
  404. if (!(child->type & EEH_PE_INVALID)) {
  405. cnt++;
  406. break;
  407. }
  408. }
  409. if (!cnt)
  410. pe->type |= EEH_PE_INVALID;
  411. else
  412. break;
  413. }
  414. }
  415. pe = parent;
  416. }
  417. return 0;
  418. }
  419. /**
  420. * eeh_pe_update_time_stamp - Update PE's frozen time stamp
  421. * @pe: EEH PE
  422. *
  423. * We have time stamp for each PE to trace its time of getting
  424. * frozen in last hour. The function should be called to update
  425. * the time stamp on first error of the specific PE. On the other
  426. * handle, we needn't account for errors happened in last hour.
  427. */
  428. void eeh_pe_update_time_stamp(struct eeh_pe *pe)
  429. {
  430. time64_t tstamp;
  431. if (!pe) return;
  432. if (pe->freeze_count <= 0) {
  433. pe->freeze_count = 0;
  434. pe->tstamp = ktime_get_seconds();
  435. } else {
  436. tstamp = ktime_get_seconds();
  437. if (tstamp - pe->tstamp > 3600) {
  438. pe->tstamp = tstamp;
  439. pe->freeze_count = 0;
  440. }
  441. }
  442. }
  443. /**
  444. * eeh_pe_state_mark - Mark specified state for PE and its associated device
  445. * @pe: EEH PE
  446. *
  447. * EEH error affects the current PE and its child PEs. The function
  448. * is used to mark appropriate state for the affected PEs and the
  449. * associated devices.
  450. */
  451. void eeh_pe_state_mark(struct eeh_pe *root, int state)
  452. {
  453. struct eeh_pe *pe;
  454. eeh_for_each_pe(root, pe)
  455. if (!(pe->state & EEH_PE_REMOVED))
  456. pe->state |= state;
  457. }
  458. EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
  459. /**
  460. * eeh_pe_mark_isolated
  461. * @pe: EEH PE
  462. *
  463. * Record that a PE has been isolated by marking the PE and it's children as
  464. * EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
  465. * as pci_channel_io_frozen.
  466. */
  467. void eeh_pe_mark_isolated(struct eeh_pe *root)
  468. {
  469. struct eeh_pe *pe;
  470. struct eeh_dev *edev;
  471. struct pci_dev *pdev;
  472. eeh_pe_state_mark(root, EEH_PE_ISOLATED);
  473. eeh_for_each_pe(root, pe) {
  474. list_for_each_entry(edev, &pe->edevs, entry) {
  475. pdev = eeh_dev_to_pci_dev(edev);
  476. if (pdev)
  477. pdev->error_state = pci_channel_io_frozen;
  478. }
  479. /* Block PCI config access if required */
  480. if (pe->state & EEH_PE_CFG_RESTRICTED)
  481. pe->state |= EEH_PE_CFG_BLOCKED;
  482. }
  483. }
  484. EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated);
  485. static void __eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag)
  486. {
  487. int mode = *((int *)flag);
  488. edev->mode |= mode;
  489. }
  490. /**
  491. * eeh_pe_dev_state_mark - Mark state for all device under the PE
  492. * @pe: EEH PE
  493. *
  494. * Mark specific state for all child devices of the PE.
  495. */
  496. void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
  497. {
  498. eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
  499. }
  500. /**
  501. * eeh_pe_state_clear - Clear state for the PE
  502. * @data: EEH PE
  503. * @state: state
  504. * @include_passed: include passed-through devices?
  505. *
  506. * The function is used to clear the indicated state from the
  507. * given PE. Besides, we also clear the check count of the PE
  508. * as well.
  509. */
  510. void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed)
  511. {
  512. struct eeh_pe *pe;
  513. struct eeh_dev *edev, *tmp;
  514. struct pci_dev *pdev;
  515. eeh_for_each_pe(root, pe) {
  516. /* Keep the state of permanently removed PE intact */
  517. if (pe->state & EEH_PE_REMOVED)
  518. continue;
  519. if (!include_passed && eeh_pe_passed(pe))
  520. continue;
  521. pe->state &= ~state;
  522. /*
  523. * Special treatment on clearing isolated state. Clear
  524. * check count since last isolation and put all affected
  525. * devices to normal state.
  526. */
  527. if (!(state & EEH_PE_ISOLATED))
  528. continue;
  529. pe->check_count = 0;
  530. eeh_pe_for_each_dev(pe, edev, tmp) {
  531. pdev = eeh_dev_to_pci_dev(edev);
  532. if (!pdev)
  533. continue;
  534. pdev->error_state = pci_channel_io_normal;
  535. }
  536. /* Unblock PCI config access if required */
  537. if (pe->state & EEH_PE_CFG_RESTRICTED)
  538. pe->state &= ~EEH_PE_CFG_BLOCKED;
  539. }
  540. }
  541. /*
  542. * Some PCI bridges (e.g. PLX bridges) have primary/secondary
  543. * buses assigned explicitly by firmware, and we probably have
  544. * lost that after reset. So we have to delay the check until
  545. * the PCI-CFG registers have been restored for the parent
  546. * bridge.
  547. *
  548. * Don't use normal PCI-CFG accessors, which probably has been
  549. * blocked on normal path during the stage. So we need utilize
  550. * eeh operations, which is always permitted.
  551. */
  552. static void eeh_bridge_check_link(struct eeh_dev *edev)
  553. {
  554. int cap;
  555. uint32_t val;
  556. int timeout = 0;
  557. /*
  558. * We only check root port and downstream ports of
  559. * PCIe switches
  560. */
  561. if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
  562. return;
  563. eeh_edev_dbg(edev, "Checking PCIe link...\n");
  564. /* Check slot status */
  565. cap = edev->pcie_cap;
  566. eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val);
  567. if (!(val & PCI_EXP_SLTSTA_PDS)) {
  568. eeh_edev_dbg(edev, "No card in the slot (0x%04x) !\n", val);
  569. return;
  570. }
  571. /* Check power status if we have the capability */
  572. eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val);
  573. if (val & PCI_EXP_SLTCAP_PCP) {
  574. eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val);
  575. if (val & PCI_EXP_SLTCTL_PCC) {
  576. eeh_edev_dbg(edev, "In power-off state, power it on ...\n");
  577. val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
  578. val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
  579. eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val);
  580. msleep(2 * 1000);
  581. }
  582. }
  583. /* Enable link */
  584. eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val);
  585. val &= ~PCI_EXP_LNKCTL_LD;
  586. eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val);
  587. /* Check link */
  588. eeh_ops->read_config(edev, cap + PCI_EXP_LNKCAP, 4, &val);
  589. if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
  590. eeh_edev_dbg(edev, "No link reporting capability (0x%08x) \n", val);
  591. msleep(1000);
  592. return;
  593. }
  594. /* Wait the link is up until timeout (5s) */
  595. timeout = 0;
  596. while (timeout < 5000) {
  597. msleep(20);
  598. timeout += 20;
  599. eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val);
  600. if (val & PCI_EXP_LNKSTA_DLLLA)
  601. break;
  602. }
  603. if (val & PCI_EXP_LNKSTA_DLLLA)
  604. eeh_edev_dbg(edev, "Link up (%s)\n",
  605. (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
  606. else
  607. eeh_edev_dbg(edev, "Link not ready (0x%04x)\n", val);
  608. }
  609. #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
  610. #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
  611. static void eeh_restore_bridge_bars(struct eeh_dev *edev)
  612. {
  613. int i;
  614. /*
  615. * Device BARs: 0x10 - 0x18
  616. * Bus numbers and windows: 0x18 - 0x30
  617. */
  618. for (i = 4; i < 13; i++)
  619. eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
  620. /* Rom: 0x38 */
  621. eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]);
  622. /* Cache line & Latency timer: 0xC 0xD */
  623. eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
  624. SAVED_BYTE(PCI_CACHE_LINE_SIZE));
  625. eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
  626. SAVED_BYTE(PCI_LATENCY_TIMER));
  627. /* Max latency, min grant, interrupt ping and line: 0x3C */
  628. eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
  629. /* PCI Command: 0x4 */
  630. eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] |
  631. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  632. /* Check the PCIe link is ready */
  633. eeh_bridge_check_link(edev);
  634. }
  635. static void eeh_restore_device_bars(struct eeh_dev *edev)
  636. {
  637. int i;
  638. u32 cmd;
  639. for (i = 4; i < 10; i++)
  640. eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
  641. /* 12 == Expansion ROM Address */
  642. eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]);
  643. eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
  644. SAVED_BYTE(PCI_CACHE_LINE_SIZE));
  645. eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
  646. SAVED_BYTE(PCI_LATENCY_TIMER));
  647. /* max latency, min grant, interrupt pin and line */
  648. eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
  649. /*
  650. * Restore PERR & SERR bits, some devices require it,
  651. * don't touch the other command bits
  652. */
  653. eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd);
  654. if (edev->config_space[1] & PCI_COMMAND_PARITY)
  655. cmd |= PCI_COMMAND_PARITY;
  656. else
  657. cmd &= ~PCI_COMMAND_PARITY;
  658. if (edev->config_space[1] & PCI_COMMAND_SERR)
  659. cmd |= PCI_COMMAND_SERR;
  660. else
  661. cmd &= ~PCI_COMMAND_SERR;
  662. eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd);
  663. }
  664. /**
  665. * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
  666. * @data: EEH device
  667. * @flag: Unused
  668. *
  669. * Loads the PCI configuration space base address registers,
  670. * the expansion ROM base address, the latency timer, and etc.
  671. * from the saved values in the device node.
  672. */
  673. static void eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag)
  674. {
  675. /* Do special restore for bridges */
  676. if (edev->mode & EEH_DEV_BRIDGE)
  677. eeh_restore_bridge_bars(edev);
  678. else
  679. eeh_restore_device_bars(edev);
  680. if (eeh_ops->restore_config)
  681. eeh_ops->restore_config(edev);
  682. }
  683. /**
  684. * eeh_pe_restore_bars - Restore the PCI config space info
  685. * @pe: EEH PE
  686. *
  687. * This routine performs a recursive walk to the children
  688. * of this device as well.
  689. */
  690. void eeh_pe_restore_bars(struct eeh_pe *pe)
  691. {
  692. /*
  693. * We needn't take the EEH lock since eeh_pe_dev_traverse()
  694. * will take that.
  695. */
  696. eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
  697. }
  698. /**
  699. * eeh_pe_loc_get - Retrieve location code binding to the given PE
  700. * @pe: EEH PE
  701. *
  702. * Retrieve the location code of the given PE. If the primary PE bus
  703. * is root bus, we will grab location code from PHB device tree node
  704. * or root port. Otherwise, the upstream bridge's device tree node
  705. * of the primary PE bus will be checked for the location code.
  706. */
  707. const char *eeh_pe_loc_get(struct eeh_pe *pe)
  708. {
  709. struct pci_bus *bus = eeh_pe_bus_get(pe);
  710. struct device_node *dn;
  711. const char *loc = NULL;
  712. while (bus) {
  713. dn = pci_bus_to_OF_node(bus);
  714. if (!dn) {
  715. bus = bus->parent;
  716. continue;
  717. }
  718. if (pci_is_root_bus(bus))
  719. loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
  720. else
  721. loc = of_get_property(dn, "ibm,slot-location-code",
  722. NULL);
  723. if (loc)
  724. return loc;
  725. bus = bus->parent;
  726. }
  727. return "N/A";
  728. }
  729. /**
  730. * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
  731. * @pe: EEH PE
  732. *
  733. * Retrieve the PCI bus according to the given PE. Basically,
  734. * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
  735. * primary PCI bus will be retrieved. The parent bus will be
  736. * returned for BUS PE. However, we don't have associated PCI
  737. * bus for DEVICE PE.
  738. */
  739. struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
  740. {
  741. struct eeh_dev *edev;
  742. struct pci_dev *pdev;
  743. if (pe->type & EEH_PE_PHB)
  744. return pe->phb->bus;
  745. /* The primary bus might be cached during probe time */
  746. if (pe->state & EEH_PE_PRI_BUS)
  747. return pe->bus;
  748. /* Retrieve the parent PCI bus of first (top) PCI device */
  749. edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
  750. pdev = eeh_dev_to_pci_dev(edev);
  751. if (pdev)
  752. return pdev->bus;
  753. return NULL;
  754. }