eeh.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright IBM Corporation 2001, 2005, 2006
  4. * Copyright Dave Engebretsen & Todd Inglett 2001
  5. * Copyright Linas Vepstas 2005, 2006
  6. * Copyright 2001-2012 IBM Corporation.
  7. *
  8. * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/sched.h>
  12. #include <linux/init.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/iommu.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/rbtree.h>
  18. #include <linux/reboot.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/export.h>
  22. #include <linux/of.h>
  23. #include <linux/atomic.h>
  24. #include <asm/debugfs.h>
  25. #include <asm/eeh.h>
  26. #include <asm/eeh_event.h>
  27. #include <asm/io.h>
  28. #include <asm/iommu.h>
  29. #include <asm/machdep.h>
  30. #include <asm/ppc-pci.h>
  31. #include <asm/rtas.h>
  32. #include <asm/pte-walk.h>
  33. /** Overview:
  34. * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
  35. * dealing with PCI bus errors that can't be dealt with within the
  36. * usual PCI framework, except by check-stopping the CPU. Systems
  37. * that are designed for high-availability/reliability cannot afford
  38. * to crash due to a "mere" PCI error, thus the need for EEH.
  39. * An EEH-capable bridge operates by converting a detected error
  40. * into a "slot freeze", taking the PCI adapter off-line, making
  41. * the slot behave, from the OS'es point of view, as if the slot
  42. * were "empty": all reads return 0xff's and all writes are silently
  43. * ignored. EEH slot isolation events can be triggered by parity
  44. * errors on the address or data busses (e.g. during posted writes),
  45. * which in turn might be caused by low voltage on the bus, dust,
  46. * vibration, humidity, radioactivity or plain-old failed hardware.
  47. *
  48. * Note, however, that one of the leading causes of EEH slot
  49. * freeze events are buggy device drivers, buggy device microcode,
  50. * or buggy device hardware. This is because any attempt by the
  51. * device to bus-master data to a memory address that is not
  52. * assigned to the device will trigger a slot freeze. (The idea
  53. * is to prevent devices-gone-wild from corrupting system memory).
  54. * Buggy hardware/drivers will have a miserable time co-existing
  55. * with EEH.
  56. *
  57. * Ideally, a PCI device driver, when suspecting that an isolation
  58. * event has occurred (e.g. by reading 0xff's), will then ask EEH
  59. * whether this is the case, and then take appropriate steps to
  60. * reset the PCI slot, the PCI device, and then resume operations.
  61. * However, until that day, the checking is done here, with the
  62. * eeh_check_failure() routine embedded in the MMIO macros. If
  63. * the slot is found to be isolated, an "EEH Event" is synthesized
  64. * and sent out for processing.
  65. */
  66. /* If a device driver keeps reading an MMIO register in an interrupt
  67. * handler after a slot isolation event, it might be broken.
  68. * This sets the threshold for how many read attempts we allow
  69. * before printing an error message.
  70. */
  71. #define EEH_MAX_FAILS 2100000
  72. /* Time to wait for a PCI slot to report status, in milliseconds */
  73. #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
  74. /*
  75. * EEH probe mode support, which is part of the flags,
  76. * is to support multiple platforms for EEH. Some platforms
  77. * like pSeries do PCI emunation based on device tree.
  78. * However, other platforms like powernv probe PCI devices
  79. * from hardware. The flag is used to distinguish that.
  80. * In addition, struct eeh_ops::probe would be invoked for
  81. * particular OF node or PCI device so that the corresponding
  82. * PE would be created there.
  83. */
  84. int eeh_subsystem_flags;
  85. EXPORT_SYMBOL(eeh_subsystem_flags);
  86. /*
  87. * EEH allowed maximal frozen times. If one particular PE's
  88. * frozen count in last hour exceeds this limit, the PE will
  89. * be forced to be offline permanently.
  90. */
  91. u32 eeh_max_freezes = 5;
  92. /*
  93. * Controls whether a recovery event should be scheduled when an
  94. * isolated device is discovered. This is only really useful for
  95. * debugging problems with the EEH core.
  96. */
  97. bool eeh_debugfs_no_recover;
  98. /* Platform dependent EEH operations */
  99. struct eeh_ops *eeh_ops = NULL;
  100. /* Lock to avoid races due to multiple reports of an error */
  101. DEFINE_RAW_SPINLOCK(confirm_error_lock);
  102. EXPORT_SYMBOL_GPL(confirm_error_lock);
  103. /* Lock to protect passed flags */
  104. static DEFINE_MUTEX(eeh_dev_mutex);
  105. /* Buffer for reporting pci register dumps. Its here in BSS, and
  106. * not dynamically alloced, so that it ends up in RMO where RTAS
  107. * can access it.
  108. */
  109. #define EEH_PCI_REGS_LOG_LEN 8192
  110. static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
  111. /*
  112. * The struct is used to maintain the EEH global statistic
  113. * information. Besides, the EEH global statistics will be
  114. * exported to user space through procfs
  115. */
  116. struct eeh_stats {
  117. u64 no_device; /* PCI device not found */
  118. u64 no_dn; /* OF node not found */
  119. u64 no_cfg_addr; /* Config address not found */
  120. u64 ignored_check; /* EEH check skipped */
  121. u64 total_mmio_ffs; /* Total EEH checks */
  122. u64 false_positives; /* Unnecessary EEH checks */
  123. u64 slot_resets; /* PE reset */
  124. };
  125. static struct eeh_stats eeh_stats;
  126. static int __init eeh_setup(char *str)
  127. {
  128. if (!strcmp(str, "off"))
  129. eeh_add_flag(EEH_FORCE_DISABLED);
  130. else if (!strcmp(str, "early_log"))
  131. eeh_add_flag(EEH_EARLY_DUMP_LOG);
  132. return 1;
  133. }
  134. __setup("eeh=", eeh_setup);
  135. void eeh_show_enabled(void)
  136. {
  137. if (eeh_has_flag(EEH_FORCE_DISABLED))
  138. pr_info("EEH: Recovery disabled by kernel parameter.\n");
  139. else if (eeh_has_flag(EEH_ENABLED))
  140. pr_info("EEH: Capable adapter found: recovery enabled.\n");
  141. else
  142. pr_info("EEH: No capable adapters found: recovery disabled.\n");
  143. }
  144. /*
  145. * This routine captures assorted PCI configuration space data
  146. * for the indicated PCI device, and puts them into a buffer
  147. * for RTAS error logging.
  148. */
  149. static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
  150. {
  151. u32 cfg;
  152. int cap, i;
  153. int n = 0, l = 0;
  154. char buffer[128];
  155. n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
  156. edev->pe->phb->global_number, edev->bdfn >> 8,
  157. PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
  158. pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
  159. edev->pe->phb->global_number, edev->bdfn >> 8,
  160. PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
  161. eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
  162. n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
  163. pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
  164. eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
  165. n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
  166. pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
  167. /* Gather bridge-specific registers */
  168. if (edev->mode & EEH_DEV_BRIDGE) {
  169. eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
  170. n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
  171. pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
  172. eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
  173. n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
  174. pr_warn("EEH: Bridge control: %04x\n", cfg);
  175. }
  176. /* Dump out the PCI-X command and status regs */
  177. cap = edev->pcix_cap;
  178. if (cap) {
  179. eeh_ops->read_config(edev, cap, 4, &cfg);
  180. n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
  181. pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
  182. eeh_ops->read_config(edev, cap+4, 4, &cfg);
  183. n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
  184. pr_warn("EEH: PCI-X status: %08x\n", cfg);
  185. }
  186. /* If PCI-E capable, dump PCI-E cap 10 */
  187. cap = edev->pcie_cap;
  188. if (cap) {
  189. n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
  190. pr_warn("EEH: PCI-E capabilities and status follow:\n");
  191. for (i=0; i<=8; i++) {
  192. eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
  193. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  194. if ((i % 4) == 0) {
  195. if (i != 0)
  196. pr_warn("%s\n", buffer);
  197. l = scnprintf(buffer, sizeof(buffer),
  198. "EEH: PCI-E %02x: %08x ",
  199. 4*i, cfg);
  200. } else {
  201. l += scnprintf(buffer+l, sizeof(buffer)-l,
  202. "%08x ", cfg);
  203. }
  204. }
  205. pr_warn("%s\n", buffer);
  206. }
  207. /* If AER capable, dump it */
  208. cap = edev->aer_cap;
  209. if (cap) {
  210. n += scnprintf(buf+n, len-n, "pci-e AER:\n");
  211. pr_warn("EEH: PCI-E AER capability register set follows:\n");
  212. for (i=0; i<=13; i++) {
  213. eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
  214. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  215. if ((i % 4) == 0) {
  216. if (i != 0)
  217. pr_warn("%s\n", buffer);
  218. l = scnprintf(buffer, sizeof(buffer),
  219. "EEH: PCI-E AER %02x: %08x ",
  220. 4*i, cfg);
  221. } else {
  222. l += scnprintf(buffer+l, sizeof(buffer)-l,
  223. "%08x ", cfg);
  224. }
  225. }
  226. pr_warn("%s\n", buffer);
  227. }
  228. return n;
  229. }
  230. static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
  231. {
  232. struct eeh_dev *edev, *tmp;
  233. size_t *plen = flag;
  234. eeh_pe_for_each_dev(pe, edev, tmp)
  235. *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
  236. EEH_PCI_REGS_LOG_LEN - *plen);
  237. return NULL;
  238. }
  239. /**
  240. * eeh_slot_error_detail - Generate combined log including driver log and error log
  241. * @pe: EEH PE
  242. * @severity: temporary or permanent error log
  243. *
  244. * This routine should be called to generate the combined log, which
  245. * is comprised of driver log and error log. The driver log is figured
  246. * out from the config space of the corresponding PCI device, while
  247. * the error log is fetched through platform dependent function call.
  248. */
  249. void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
  250. {
  251. size_t loglen = 0;
  252. /*
  253. * When the PHB is fenced or dead, it's pointless to collect
  254. * the data from PCI config space because it should return
  255. * 0xFF's. For ER, we still retrieve the data from the PCI
  256. * config space.
  257. *
  258. * For pHyp, we have to enable IO for log retrieval. Otherwise,
  259. * 0xFF's is always returned from PCI config space.
  260. *
  261. * When the @severity is EEH_LOG_PERM, the PE is going to be
  262. * removed. Prior to that, the drivers for devices included in
  263. * the PE will be closed. The drivers rely on working IO path
  264. * to bring the devices to quiet state. Otherwise, PCI traffic
  265. * from those devices after they are removed is like to cause
  266. * another unexpected EEH error.
  267. */
  268. if (!(pe->type & EEH_PE_PHB)) {
  269. if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
  270. severity == EEH_LOG_PERM)
  271. eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  272. /*
  273. * The config space of some PCI devices can't be accessed
  274. * when their PEs are in frozen state. Otherwise, fenced
  275. * PHB might be seen. Those PEs are identified with flag
  276. * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
  277. * is set automatically when the PE is put to EEH_PE_ISOLATED.
  278. *
  279. * Restoring BARs possibly triggers PCI config access in
  280. * (OPAL) firmware and then causes fenced PHB. If the
  281. * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
  282. * pointless to restore BARs and dump config space.
  283. */
  284. eeh_ops->configure_bridge(pe);
  285. if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
  286. eeh_pe_restore_bars(pe);
  287. pci_regs_buf[0] = 0;
  288. eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
  289. }
  290. }
  291. eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
  292. }
  293. /**
  294. * eeh_token_to_phys - Convert EEH address token to phys address
  295. * @token: I/O token, should be address in the form 0xA....
  296. *
  297. * This routine should be called to convert virtual I/O address
  298. * to physical one.
  299. */
  300. static inline unsigned long eeh_token_to_phys(unsigned long token)
  301. {
  302. pte_t *ptep;
  303. unsigned long pa;
  304. int hugepage_shift;
  305. /*
  306. * We won't find hugepages here(this is iomem). Hence we are not
  307. * worried about _PAGE_SPLITTING/collapse. Also we will not hit
  308. * page table free, because of init_mm.
  309. */
  310. ptep = find_init_mm_pte(token, &hugepage_shift);
  311. if (!ptep)
  312. return token;
  313. pa = pte_pfn(*ptep);
  314. /* On radix we can do hugepage mappings for io, so handle that */
  315. if (!hugepage_shift)
  316. hugepage_shift = PAGE_SHIFT;
  317. pa <<= PAGE_SHIFT;
  318. pa |= token & ((1ul << hugepage_shift) - 1);
  319. return pa;
  320. }
  321. /*
  322. * On PowerNV platform, we might already have fenced PHB there.
  323. * For that case, it's meaningless to recover frozen PE. Intead,
  324. * We have to handle fenced PHB firstly.
  325. */
  326. static int eeh_phb_check_failure(struct eeh_pe *pe)
  327. {
  328. struct eeh_pe *phb_pe;
  329. unsigned long flags;
  330. int ret;
  331. if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
  332. return -EPERM;
  333. /* Find the PHB PE */
  334. phb_pe = eeh_phb_pe_get(pe->phb);
  335. if (!phb_pe) {
  336. pr_warn("%s Can't find PE for PHB#%x\n",
  337. __func__, pe->phb->global_number);
  338. return -EEXIST;
  339. }
  340. /* If the PHB has been in problematic state */
  341. eeh_serialize_lock(&flags);
  342. if (phb_pe->state & EEH_PE_ISOLATED) {
  343. ret = 0;
  344. goto out;
  345. }
  346. /* Check PHB state */
  347. ret = eeh_ops->get_state(phb_pe, NULL);
  348. if ((ret < 0) ||
  349. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  350. ret = 0;
  351. goto out;
  352. }
  353. /* Isolate the PHB and send event */
  354. eeh_pe_mark_isolated(phb_pe);
  355. eeh_serialize_unlock(flags);
  356. pr_debug("EEH: PHB#%x failure detected, location: %s\n",
  357. phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
  358. eeh_send_failure_event(phb_pe);
  359. return 1;
  360. out:
  361. eeh_serialize_unlock(flags);
  362. return ret;
  363. }
  364. /**
  365. * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  366. * @edev: eeh device
  367. *
  368. * Check for an EEH failure for the given device node. Call this
  369. * routine if the result of a read was all 0xff's and you want to
  370. * find out if this is due to an EEH slot freeze. This routine
  371. * will query firmware for the EEH status.
  372. *
  373. * Returns 0 if there has not been an EEH error; otherwise returns
  374. * a non-zero value and queues up a slot isolation event notification.
  375. *
  376. * It is safe to call this routine in an interrupt context.
  377. */
  378. int eeh_dev_check_failure(struct eeh_dev *edev)
  379. {
  380. int ret;
  381. unsigned long flags;
  382. struct device_node *dn;
  383. struct pci_dev *dev;
  384. struct eeh_pe *pe, *parent_pe;
  385. int rc = 0;
  386. const char *location = NULL;
  387. eeh_stats.total_mmio_ffs++;
  388. if (!eeh_enabled())
  389. return 0;
  390. if (!edev) {
  391. eeh_stats.no_dn++;
  392. return 0;
  393. }
  394. dev = eeh_dev_to_pci_dev(edev);
  395. pe = eeh_dev_to_pe(edev);
  396. /* Access to IO BARs might get this far and still not want checking. */
  397. if (!pe) {
  398. eeh_stats.ignored_check++;
  399. eeh_edev_dbg(edev, "Ignored check\n");
  400. return 0;
  401. }
  402. /*
  403. * On PowerNV platform, we might already have fenced PHB
  404. * there and we need take care of that firstly.
  405. */
  406. ret = eeh_phb_check_failure(pe);
  407. if (ret > 0)
  408. return ret;
  409. /*
  410. * If the PE isn't owned by us, we shouldn't check the
  411. * state. Instead, let the owner handle it if the PE has
  412. * been frozen.
  413. */
  414. if (eeh_pe_passed(pe))
  415. return 0;
  416. /* If we already have a pending isolation event for this
  417. * slot, we know it's bad already, we don't need to check.
  418. * Do this checking under a lock; as multiple PCI devices
  419. * in one slot might report errors simultaneously, and we
  420. * only want one error recovery routine running.
  421. */
  422. eeh_serialize_lock(&flags);
  423. rc = 1;
  424. if (pe->state & EEH_PE_ISOLATED) {
  425. pe->check_count++;
  426. if (pe->check_count == EEH_MAX_FAILS) {
  427. dn = pci_device_to_OF_node(dev);
  428. if (dn)
  429. location = of_get_property(dn, "ibm,loc-code",
  430. NULL);
  431. eeh_edev_err(edev, "%d reads ignored for recovering device at location=%s driver=%s\n",
  432. pe->check_count,
  433. location ? location : "unknown",
  434. eeh_driver_name(dev));
  435. eeh_edev_err(edev, "Might be infinite loop in %s driver\n",
  436. eeh_driver_name(dev));
  437. dump_stack();
  438. }
  439. goto dn_unlock;
  440. }
  441. /*
  442. * Now test for an EEH failure. This is VERY expensive.
  443. * Note that the eeh_config_addr may be a parent device
  444. * in the case of a device behind a bridge, or it may be
  445. * function zero of a multi-function device.
  446. * In any case they must share a common PHB.
  447. */
  448. ret = eeh_ops->get_state(pe, NULL);
  449. /* Note that config-io to empty slots may fail;
  450. * they are empty when they don't have children.
  451. * We will punt with the following conditions: Failure to get
  452. * PE's state, EEH not support and Permanently unavailable
  453. * state, PE is in good state.
  454. */
  455. if ((ret < 0) ||
  456. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  457. eeh_stats.false_positives++;
  458. pe->false_positives++;
  459. rc = 0;
  460. goto dn_unlock;
  461. }
  462. /*
  463. * It should be corner case that the parent PE has been
  464. * put into frozen state as well. We should take care
  465. * that at first.
  466. */
  467. parent_pe = pe->parent;
  468. while (parent_pe) {
  469. /* Hit the ceiling ? */
  470. if (parent_pe->type & EEH_PE_PHB)
  471. break;
  472. /* Frozen parent PE ? */
  473. ret = eeh_ops->get_state(parent_pe, NULL);
  474. if (ret > 0 && !eeh_state_active(ret)) {
  475. pe = parent_pe;
  476. pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
  477. pe->phb->global_number, pe->addr,
  478. pe->phb->global_number, parent_pe->addr);
  479. }
  480. /* Next parent level */
  481. parent_pe = parent_pe->parent;
  482. }
  483. eeh_stats.slot_resets++;
  484. /* Avoid repeated reports of this failure, including problems
  485. * with other functions on this device, and functions under
  486. * bridges.
  487. */
  488. eeh_pe_mark_isolated(pe);
  489. eeh_serialize_unlock(flags);
  490. /* Most EEH events are due to device driver bugs. Having
  491. * a stack trace will help the device-driver authors figure
  492. * out what happened. So print that out.
  493. */
  494. pr_debug("EEH: %s: Frozen PHB#%x-PE#%x detected\n",
  495. __func__, pe->phb->global_number, pe->addr);
  496. eeh_send_failure_event(pe);
  497. return 1;
  498. dn_unlock:
  499. eeh_serialize_unlock(flags);
  500. return rc;
  501. }
  502. EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
  503. /**
  504. * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
  505. * @token: I/O address
  506. *
  507. * Check for an EEH failure at the given I/O address. Call this
  508. * routine if the result of a read was all 0xff's and you want to
  509. * find out if this is due to an EEH slot freeze event. This routine
  510. * will query firmware for the EEH status.
  511. *
  512. * Note this routine is safe to call in an interrupt context.
  513. */
  514. int eeh_check_failure(const volatile void __iomem *token)
  515. {
  516. unsigned long addr;
  517. struct eeh_dev *edev;
  518. /* Finding the phys addr + pci device; this is pretty quick. */
  519. addr = eeh_token_to_phys((unsigned long __force) token);
  520. edev = eeh_addr_cache_get_dev(addr);
  521. if (!edev) {
  522. eeh_stats.no_device++;
  523. return 0;
  524. }
  525. return eeh_dev_check_failure(edev);
  526. }
  527. EXPORT_SYMBOL(eeh_check_failure);
  528. /**
  529. * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
  530. * @pe: EEH PE
  531. *
  532. * This routine should be called to reenable frozen MMIO or DMA
  533. * so that it would work correctly again. It's useful while doing
  534. * recovery or log collection on the indicated device.
  535. */
  536. int eeh_pci_enable(struct eeh_pe *pe, int function)
  537. {
  538. int active_flag, rc;
  539. /*
  540. * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
  541. * Also, it's pointless to enable them on unfrozen PE. So
  542. * we have to check before enabling IO or DMA.
  543. */
  544. switch (function) {
  545. case EEH_OPT_THAW_MMIO:
  546. active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
  547. break;
  548. case EEH_OPT_THAW_DMA:
  549. active_flag = EEH_STATE_DMA_ACTIVE;
  550. break;
  551. case EEH_OPT_DISABLE:
  552. case EEH_OPT_ENABLE:
  553. case EEH_OPT_FREEZE_PE:
  554. active_flag = 0;
  555. break;
  556. default:
  557. pr_warn("%s: Invalid function %d\n",
  558. __func__, function);
  559. return -EINVAL;
  560. }
  561. /*
  562. * Check if IO or DMA has been enabled before
  563. * enabling them.
  564. */
  565. if (active_flag) {
  566. rc = eeh_ops->get_state(pe, NULL);
  567. if (rc < 0)
  568. return rc;
  569. /* Needn't enable it at all */
  570. if (rc == EEH_STATE_NOT_SUPPORT)
  571. return 0;
  572. /* It's already enabled */
  573. if (rc & active_flag)
  574. return 0;
  575. }
  576. /* Issue the request */
  577. rc = eeh_ops->set_option(pe, function);
  578. if (rc)
  579. pr_warn("%s: Unexpected state change %d on "
  580. "PHB#%x-PE#%x, err=%d\n",
  581. __func__, function, pe->phb->global_number,
  582. pe->addr, rc);
  583. /* Check if the request is finished successfully */
  584. if (active_flag) {
  585. rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  586. if (rc < 0)
  587. return rc;
  588. if (rc & active_flag)
  589. return 0;
  590. return -EIO;
  591. }
  592. return rc;
  593. }
  594. static void eeh_disable_and_save_dev_state(struct eeh_dev *edev,
  595. void *userdata)
  596. {
  597. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  598. struct pci_dev *dev = userdata;
  599. /*
  600. * The caller should have disabled and saved the
  601. * state for the specified device
  602. */
  603. if (!pdev || pdev == dev)
  604. return;
  605. /* Ensure we have D0 power state */
  606. pci_set_power_state(pdev, PCI_D0);
  607. /* Save device state */
  608. pci_save_state(pdev);
  609. /*
  610. * Disable device to avoid any DMA traffic and
  611. * interrupt from the device
  612. */
  613. pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  614. }
  615. static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
  616. {
  617. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  618. struct pci_dev *dev = userdata;
  619. if (!pdev)
  620. return;
  621. /* Apply customization from firmware */
  622. if (eeh_ops->restore_config)
  623. eeh_ops->restore_config(edev);
  624. /* The caller should restore state for the specified device */
  625. if (pdev != dev)
  626. pci_restore_state(pdev);
  627. }
  628. /**
  629. * pcibios_set_pcie_reset_state - Set PCI-E reset state
  630. * @dev: pci device struct
  631. * @state: reset state to enter
  632. *
  633. * Return value:
  634. * 0 if success
  635. */
  636. int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  637. {
  638. struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
  639. struct eeh_pe *pe = eeh_dev_to_pe(edev);
  640. if (!pe) {
  641. pr_err("%s: No PE found on PCI device %s\n",
  642. __func__, pci_name(dev));
  643. return -EINVAL;
  644. }
  645. switch (state) {
  646. case pcie_deassert_reset:
  647. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  648. eeh_unfreeze_pe(pe);
  649. if (!(pe->type & EEH_PE_VF))
  650. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  651. eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
  652. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
  653. break;
  654. case pcie_hot_reset:
  655. eeh_pe_mark_isolated(pe);
  656. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  657. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  658. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  659. if (!(pe->type & EEH_PE_VF))
  660. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  661. eeh_ops->reset(pe, EEH_RESET_HOT);
  662. break;
  663. case pcie_warm_reset:
  664. eeh_pe_mark_isolated(pe);
  665. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  666. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  667. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  668. if (!(pe->type & EEH_PE_VF))
  669. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  670. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  671. break;
  672. default:
  673. eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
  674. return -EINVAL;
  675. };
  676. return 0;
  677. }
  678. /**
  679. * eeh_set_pe_freset - Check the required reset for the indicated device
  680. * @data: EEH device
  681. * @flag: return value
  682. *
  683. * Each device might have its preferred reset type: fundamental or
  684. * hot reset. The routine is used to collected the information for
  685. * the indicated device and its children so that the bunch of the
  686. * devices could be reset properly.
  687. */
  688. static void eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
  689. {
  690. struct pci_dev *dev;
  691. unsigned int *freset = (unsigned int *)flag;
  692. dev = eeh_dev_to_pci_dev(edev);
  693. if (dev)
  694. *freset |= dev->needs_freset;
  695. }
  696. static void eeh_pe_refreeze_passed(struct eeh_pe *root)
  697. {
  698. struct eeh_pe *pe;
  699. int state;
  700. eeh_for_each_pe(root, pe) {
  701. if (eeh_pe_passed(pe)) {
  702. state = eeh_ops->get_state(pe, NULL);
  703. if (state &
  704. (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) {
  705. pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n",
  706. pe->phb->global_number, pe->addr);
  707. eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
  708. }
  709. }
  710. }
  711. }
  712. /**
  713. * eeh_pe_reset_full - Complete a full reset process on the indicated PE
  714. * @pe: EEH PE
  715. *
  716. * This function executes a full reset procedure on a PE, including setting
  717. * the appropriate flags, performing a fundamental or hot reset, and then
  718. * deactivating the reset status. It is designed to be used within the EEH
  719. * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
  720. * only performs a single operation at a time.
  721. *
  722. * This function will attempt to reset a PE three times before failing.
  723. */
  724. int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
  725. {
  726. int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
  727. int type = EEH_RESET_HOT;
  728. unsigned int freset = 0;
  729. int i, state = 0, ret;
  730. /*
  731. * Determine the type of reset to perform - hot or fundamental.
  732. * Hot reset is the default operation, unless any device under the
  733. * PE requires a fundamental reset.
  734. */
  735. eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
  736. if (freset)
  737. type = EEH_RESET_FUNDAMENTAL;
  738. /* Mark the PE as in reset state and block config space accesses */
  739. eeh_pe_state_mark(pe, reset_state);
  740. /* Make three attempts at resetting the bus */
  741. for (i = 0; i < 3; i++) {
  742. ret = eeh_pe_reset(pe, type, include_passed);
  743. if (!ret)
  744. ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
  745. include_passed);
  746. if (ret) {
  747. ret = -EIO;
  748. pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n",
  749. state, pe->phb->global_number, pe->addr, i + 1);
  750. continue;
  751. }
  752. if (i)
  753. pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n",
  754. pe->phb->global_number, pe->addr, i + 1);
  755. /* Wait until the PE is in a functioning state */
  756. state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  757. if (state < 0) {
  758. pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x",
  759. pe->phb->global_number, pe->addr);
  760. ret = -ENOTRECOVERABLE;
  761. break;
  762. }
  763. if (eeh_state_active(state))
  764. break;
  765. else
  766. pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n",
  767. pe->phb->global_number, pe->addr, state, i + 1);
  768. }
  769. /* Resetting the PE may have unfrozen child PEs. If those PEs have been
  770. * (potentially) passed through to a guest, re-freeze them:
  771. */
  772. if (!include_passed)
  773. eeh_pe_refreeze_passed(pe);
  774. eeh_pe_state_clear(pe, reset_state, true);
  775. return ret;
  776. }
  777. /**
  778. * eeh_save_bars - Save device bars
  779. * @edev: PCI device associated EEH device
  780. *
  781. * Save the values of the device bars. Unlike the restore
  782. * routine, this routine is *not* recursive. This is because
  783. * PCI devices are added individually; but, for the restore,
  784. * an entire slot is reset at a time.
  785. */
  786. void eeh_save_bars(struct eeh_dev *edev)
  787. {
  788. int i;
  789. if (!edev)
  790. return;
  791. for (i = 0; i < 16; i++)
  792. eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
  793. /*
  794. * For PCI bridges including root port, we need enable bus
  795. * master explicitly. Otherwise, it can't fetch IODA table
  796. * entries correctly. So we cache the bit in advance so that
  797. * we can restore it after reset, either PHB range or PE range.
  798. */
  799. if (edev->mode & EEH_DEV_BRIDGE)
  800. edev->config_space[1] |= PCI_COMMAND_MASTER;
  801. }
  802. static int eeh_reboot_notifier(struct notifier_block *nb,
  803. unsigned long action, void *unused)
  804. {
  805. eeh_clear_flag(EEH_ENABLED);
  806. return NOTIFY_DONE;
  807. }
  808. static struct notifier_block eeh_reboot_nb = {
  809. .notifier_call = eeh_reboot_notifier,
  810. };
  811. static int eeh_device_notifier(struct notifier_block *nb,
  812. unsigned long action, void *data)
  813. {
  814. struct device *dev = data;
  815. switch (action) {
  816. /*
  817. * Note: It's not possible to perform EEH device addition (i.e.
  818. * {pseries,pnv}_pcibios_bus_add_device()) here because it depends on
  819. * the device's resources, which have not yet been set up.
  820. */
  821. case BUS_NOTIFY_DEL_DEVICE:
  822. eeh_remove_device(to_pci_dev(dev));
  823. break;
  824. default:
  825. break;
  826. }
  827. return NOTIFY_DONE;
  828. }
  829. static struct notifier_block eeh_device_nb = {
  830. .notifier_call = eeh_device_notifier,
  831. };
  832. /**
  833. * eeh_init - System wide EEH initialization
  834. *
  835. * It's the platform's job to call this from an arch_initcall().
  836. */
  837. int eeh_init(struct eeh_ops *ops)
  838. {
  839. struct pci_controller *hose, *tmp;
  840. int ret = 0;
  841. /* the platform should only initialise EEH once */
  842. if (WARN_ON(eeh_ops))
  843. return -EEXIST;
  844. if (WARN_ON(!ops))
  845. return -ENOENT;
  846. eeh_ops = ops;
  847. /* Register reboot notifier */
  848. ret = register_reboot_notifier(&eeh_reboot_nb);
  849. if (ret) {
  850. pr_warn("%s: Failed to register reboot notifier (%d)\n",
  851. __func__, ret);
  852. return ret;
  853. }
  854. ret = bus_register_notifier(&pci_bus_type, &eeh_device_nb);
  855. if (ret) {
  856. pr_warn("%s: Failed to register bus notifier (%d)\n",
  857. __func__, ret);
  858. return ret;
  859. }
  860. /* Initialize PHB PEs */
  861. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  862. eeh_phb_pe_create(hose);
  863. eeh_addr_cache_init();
  864. /* Initialize EEH event */
  865. return eeh_event_init();
  866. }
  867. /**
  868. * eeh_probe_device() - Perform EEH initialization for the indicated pci device
  869. * @dev: pci device for which to set up EEH
  870. *
  871. * This routine must be used to complete EEH initialization for PCI
  872. * devices that were added after system boot (e.g. hotplug, dlpar).
  873. */
  874. void eeh_probe_device(struct pci_dev *dev)
  875. {
  876. struct eeh_dev *edev;
  877. pr_debug("EEH: Adding device %s\n", pci_name(dev));
  878. /*
  879. * pci_dev_to_eeh_dev() can only work if eeh_probe_dev() was
  880. * already called for this device.
  881. */
  882. if (WARN_ON_ONCE(pci_dev_to_eeh_dev(dev))) {
  883. pci_dbg(dev, "Already bound to an eeh_dev!\n");
  884. return;
  885. }
  886. edev = eeh_ops->probe(dev);
  887. if (!edev) {
  888. pr_debug("EEH: Adding device failed\n");
  889. return;
  890. }
  891. /*
  892. * FIXME: We rely on pcibios_release_device() to remove the
  893. * existing EEH state. The release function is only called if
  894. * the pci_dev's refcount drops to zero so if something is
  895. * keeping a ref to a device (e.g. a filesystem) we need to
  896. * remove the old EEH state.
  897. *
  898. * FIXME: HEY MA, LOOK AT ME, NO LOCKING!
  899. */
  900. if (edev->pdev && edev->pdev != dev) {
  901. eeh_pe_tree_remove(edev);
  902. eeh_addr_cache_rmv_dev(edev->pdev);
  903. eeh_sysfs_remove_device(edev->pdev);
  904. /*
  905. * We definitely should have the PCI device removed
  906. * though it wasn't correctly. So we needn't call
  907. * into error handler afterwards.
  908. */
  909. edev->mode |= EEH_DEV_NO_HANDLER;
  910. }
  911. /* bind the pdev and the edev together */
  912. edev->pdev = dev;
  913. dev->dev.archdata.edev = edev;
  914. eeh_addr_cache_insert_dev(dev);
  915. eeh_sysfs_add_device(dev);
  916. }
  917. /**
  918. * eeh_remove_device - Undo EEH setup for the indicated pci device
  919. * @dev: pci device to be removed
  920. *
  921. * This routine should be called when a device is removed from
  922. * a running system (e.g. by hotplug or dlpar). It unregisters
  923. * the PCI device from the EEH subsystem. I/O errors affecting
  924. * this device will no longer be detected after this call; thus,
  925. * i/o errors affecting this slot may leave this device unusable.
  926. */
  927. void eeh_remove_device(struct pci_dev *dev)
  928. {
  929. struct eeh_dev *edev;
  930. if (!dev || !eeh_enabled())
  931. return;
  932. edev = pci_dev_to_eeh_dev(dev);
  933. /* Unregister the device with the EEH/PCI address search system */
  934. dev_dbg(&dev->dev, "EEH: Removing device\n");
  935. if (!edev || !edev->pdev || !edev->pe) {
  936. dev_dbg(&dev->dev, "EEH: Device not referenced!\n");
  937. return;
  938. }
  939. /*
  940. * During the hotplug for EEH error recovery, we need the EEH
  941. * device attached to the parent PE in order for BAR restore
  942. * a bit later. So we keep it for BAR restore and remove it
  943. * from the parent PE during the BAR resotre.
  944. */
  945. edev->pdev = NULL;
  946. /*
  947. * eeh_sysfs_remove_device() uses pci_dev_to_eeh_dev() so we need to
  948. * remove the sysfs files before clearing dev.archdata.edev
  949. */
  950. if (edev->mode & EEH_DEV_SYSFS)
  951. eeh_sysfs_remove_device(dev);
  952. /*
  953. * We're removing from the PCI subsystem, that means
  954. * the PCI device driver can't support EEH or not
  955. * well. So we rely on hotplug completely to do recovery
  956. * for the specific PCI device.
  957. */
  958. edev->mode |= EEH_DEV_NO_HANDLER;
  959. eeh_addr_cache_rmv_dev(dev);
  960. /*
  961. * The flag "in_error" is used to trace EEH devices for VFs
  962. * in error state or not. It's set in eeh_report_error(). If
  963. * it's not set, eeh_report_{reset,resume}() won't be called
  964. * for the VF EEH device.
  965. */
  966. edev->in_error = false;
  967. dev->dev.archdata.edev = NULL;
  968. if (!(edev->pe->state & EEH_PE_KEEP))
  969. eeh_pe_tree_remove(edev);
  970. else
  971. edev->mode |= EEH_DEV_DISCONNECTED;
  972. }
  973. int eeh_unfreeze_pe(struct eeh_pe *pe)
  974. {
  975. int ret;
  976. ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  977. if (ret) {
  978. pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
  979. __func__, ret, pe->phb->global_number, pe->addr);
  980. return ret;
  981. }
  982. ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
  983. if (ret) {
  984. pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
  985. __func__, ret, pe->phb->global_number, pe->addr);
  986. return ret;
  987. }
  988. return ret;
  989. }
  990. static struct pci_device_id eeh_reset_ids[] = {
  991. { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
  992. { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
  993. { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
  994. { 0 }
  995. };
  996. static int eeh_pe_change_owner(struct eeh_pe *pe)
  997. {
  998. struct eeh_dev *edev, *tmp;
  999. struct pci_dev *pdev;
  1000. struct pci_device_id *id;
  1001. int ret;
  1002. /* Check PE state */
  1003. ret = eeh_ops->get_state(pe, NULL);
  1004. if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
  1005. return 0;
  1006. /* Unfrozen PE, nothing to do */
  1007. if (eeh_state_active(ret))
  1008. return 0;
  1009. /* Frozen PE, check if it needs PE level reset */
  1010. eeh_pe_for_each_dev(pe, edev, tmp) {
  1011. pdev = eeh_dev_to_pci_dev(edev);
  1012. if (!pdev)
  1013. continue;
  1014. for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
  1015. if (id->vendor != PCI_ANY_ID &&
  1016. id->vendor != pdev->vendor)
  1017. continue;
  1018. if (id->device != PCI_ANY_ID &&
  1019. id->device != pdev->device)
  1020. continue;
  1021. if (id->subvendor != PCI_ANY_ID &&
  1022. id->subvendor != pdev->subsystem_vendor)
  1023. continue;
  1024. if (id->subdevice != PCI_ANY_ID &&
  1025. id->subdevice != pdev->subsystem_device)
  1026. continue;
  1027. return eeh_pe_reset_and_recover(pe);
  1028. }
  1029. }
  1030. ret = eeh_unfreeze_pe(pe);
  1031. if (!ret)
  1032. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
  1033. return ret;
  1034. }
  1035. /**
  1036. * eeh_dev_open - Increase count of pass through devices for PE
  1037. * @pdev: PCI device
  1038. *
  1039. * Increase count of passed through devices for the indicated
  1040. * PE. In the result, the EEH errors detected on the PE won't be
  1041. * reported. The PE owner will be responsible for detection
  1042. * and recovery.
  1043. */
  1044. int eeh_dev_open(struct pci_dev *pdev)
  1045. {
  1046. struct eeh_dev *edev;
  1047. int ret = -ENODEV;
  1048. mutex_lock(&eeh_dev_mutex);
  1049. /* No PCI device ? */
  1050. if (!pdev)
  1051. goto out;
  1052. /* No EEH device or PE ? */
  1053. edev = pci_dev_to_eeh_dev(pdev);
  1054. if (!edev || !edev->pe)
  1055. goto out;
  1056. /*
  1057. * The PE might have been put into frozen state, but we
  1058. * didn't detect that yet. The passed through PCI devices
  1059. * in frozen PE won't work properly. Clear the frozen state
  1060. * in advance.
  1061. */
  1062. ret = eeh_pe_change_owner(edev->pe);
  1063. if (ret)
  1064. goto out;
  1065. /* Increase PE's pass through count */
  1066. atomic_inc(&edev->pe->pass_dev_cnt);
  1067. mutex_unlock(&eeh_dev_mutex);
  1068. return 0;
  1069. out:
  1070. mutex_unlock(&eeh_dev_mutex);
  1071. return ret;
  1072. }
  1073. EXPORT_SYMBOL_GPL(eeh_dev_open);
  1074. /**
  1075. * eeh_dev_release - Decrease count of pass through devices for PE
  1076. * @pdev: PCI device
  1077. *
  1078. * Decrease count of pass through devices for the indicated PE. If
  1079. * there is no passed through device in PE, the EEH errors detected
  1080. * on the PE will be reported and handled as usual.
  1081. */
  1082. void eeh_dev_release(struct pci_dev *pdev)
  1083. {
  1084. struct eeh_dev *edev;
  1085. mutex_lock(&eeh_dev_mutex);
  1086. /* No PCI device ? */
  1087. if (!pdev)
  1088. goto out;
  1089. /* No EEH device ? */
  1090. edev = pci_dev_to_eeh_dev(pdev);
  1091. if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
  1092. goto out;
  1093. /* Decrease PE's pass through count */
  1094. WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
  1095. eeh_pe_change_owner(edev->pe);
  1096. out:
  1097. mutex_unlock(&eeh_dev_mutex);
  1098. }
  1099. EXPORT_SYMBOL(eeh_dev_release);
  1100. #ifdef CONFIG_IOMMU_API
  1101. static int dev_has_iommu_table(struct device *dev, void *data)
  1102. {
  1103. struct pci_dev *pdev = to_pci_dev(dev);
  1104. struct pci_dev **ppdev = data;
  1105. if (!dev)
  1106. return 0;
  1107. if (device_iommu_mapped(dev)) {
  1108. *ppdev = pdev;
  1109. return 1;
  1110. }
  1111. return 0;
  1112. }
  1113. /**
  1114. * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
  1115. * @group: IOMMU group
  1116. *
  1117. * The routine is called to convert IOMMU group to EEH PE.
  1118. */
  1119. struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
  1120. {
  1121. struct pci_dev *pdev = NULL;
  1122. struct eeh_dev *edev;
  1123. int ret;
  1124. /* No IOMMU group ? */
  1125. if (!group)
  1126. return NULL;
  1127. ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
  1128. if (!ret || !pdev)
  1129. return NULL;
  1130. /* No EEH device or PE ? */
  1131. edev = pci_dev_to_eeh_dev(pdev);
  1132. if (!edev || !edev->pe)
  1133. return NULL;
  1134. return edev->pe;
  1135. }
  1136. EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
  1137. #endif /* CONFIG_IOMMU_API */
  1138. /**
  1139. * eeh_pe_set_option - Set options for the indicated PE
  1140. * @pe: EEH PE
  1141. * @option: requested option
  1142. *
  1143. * The routine is called to enable or disable EEH functionality
  1144. * on the indicated PE, to enable IO or DMA for the frozen PE.
  1145. */
  1146. int eeh_pe_set_option(struct eeh_pe *pe, int option)
  1147. {
  1148. int ret = 0;
  1149. /* Invalid PE ? */
  1150. if (!pe)
  1151. return -ENODEV;
  1152. /*
  1153. * EEH functionality could possibly be disabled, just
  1154. * return error for the case. And the EEH functinality
  1155. * isn't expected to be disabled on one specific PE.
  1156. */
  1157. switch (option) {
  1158. case EEH_OPT_ENABLE:
  1159. if (eeh_enabled()) {
  1160. ret = eeh_pe_change_owner(pe);
  1161. break;
  1162. }
  1163. ret = -EIO;
  1164. break;
  1165. case EEH_OPT_DISABLE:
  1166. break;
  1167. case EEH_OPT_THAW_MMIO:
  1168. case EEH_OPT_THAW_DMA:
  1169. case EEH_OPT_FREEZE_PE:
  1170. if (!eeh_ops || !eeh_ops->set_option) {
  1171. ret = -ENOENT;
  1172. break;
  1173. }
  1174. ret = eeh_pci_enable(pe, option);
  1175. break;
  1176. default:
  1177. pr_debug("%s: Option %d out of range (%d, %d)\n",
  1178. __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
  1179. ret = -EINVAL;
  1180. }
  1181. return ret;
  1182. }
  1183. EXPORT_SYMBOL_GPL(eeh_pe_set_option);
  1184. /**
  1185. * eeh_pe_get_state - Retrieve PE's state
  1186. * @pe: EEH PE
  1187. *
  1188. * Retrieve the PE's state, which includes 3 aspects: enabled
  1189. * DMA, enabled IO and asserted reset.
  1190. */
  1191. int eeh_pe_get_state(struct eeh_pe *pe)
  1192. {
  1193. int result, ret = 0;
  1194. bool rst_active, dma_en, mmio_en;
  1195. /* Existing PE ? */
  1196. if (!pe)
  1197. return -ENODEV;
  1198. if (!eeh_ops || !eeh_ops->get_state)
  1199. return -ENOENT;
  1200. /*
  1201. * If the parent PE is owned by the host kernel and is undergoing
  1202. * error recovery, we should return the PE state as temporarily
  1203. * unavailable so that the error recovery on the guest is suspended
  1204. * until the recovery completes on the host.
  1205. */
  1206. if (pe->parent &&
  1207. !(pe->state & EEH_PE_REMOVED) &&
  1208. (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
  1209. return EEH_PE_STATE_UNAVAIL;
  1210. result = eeh_ops->get_state(pe, NULL);
  1211. rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
  1212. dma_en = !!(result & EEH_STATE_DMA_ENABLED);
  1213. mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
  1214. if (rst_active)
  1215. ret = EEH_PE_STATE_RESET;
  1216. else if (dma_en && mmio_en)
  1217. ret = EEH_PE_STATE_NORMAL;
  1218. else if (!dma_en && !mmio_en)
  1219. ret = EEH_PE_STATE_STOPPED_IO_DMA;
  1220. else if (!dma_en && mmio_en)
  1221. ret = EEH_PE_STATE_STOPPED_DMA;
  1222. else
  1223. ret = EEH_PE_STATE_UNAVAIL;
  1224. return ret;
  1225. }
  1226. EXPORT_SYMBOL_GPL(eeh_pe_get_state);
  1227. static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
  1228. {
  1229. struct eeh_dev *edev, *tmp;
  1230. struct pci_dev *pdev;
  1231. int ret = 0;
  1232. eeh_pe_restore_bars(pe);
  1233. /*
  1234. * Reenable PCI devices as the devices passed
  1235. * through are always enabled before the reset.
  1236. */
  1237. eeh_pe_for_each_dev(pe, edev, tmp) {
  1238. pdev = eeh_dev_to_pci_dev(edev);
  1239. if (!pdev)
  1240. continue;
  1241. ret = pci_reenable_device(pdev);
  1242. if (ret) {
  1243. pr_warn("%s: Failure %d reenabling %s\n",
  1244. __func__, ret, pci_name(pdev));
  1245. return ret;
  1246. }
  1247. }
  1248. /* The PE is still in frozen state */
  1249. if (include_passed || !eeh_pe_passed(pe)) {
  1250. ret = eeh_unfreeze_pe(pe);
  1251. } else
  1252. pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n",
  1253. pe->phb->global_number, pe->addr);
  1254. if (!ret)
  1255. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
  1256. return ret;
  1257. }
  1258. /**
  1259. * eeh_pe_reset - Issue PE reset according to specified type
  1260. * @pe: EEH PE
  1261. * @option: reset type
  1262. *
  1263. * The routine is called to reset the specified PE with the
  1264. * indicated type, either fundamental reset or hot reset.
  1265. * PE reset is the most important part for error recovery.
  1266. */
  1267. int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
  1268. {
  1269. int ret = 0;
  1270. /* Invalid PE ? */
  1271. if (!pe)
  1272. return -ENODEV;
  1273. if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
  1274. return -ENOENT;
  1275. switch (option) {
  1276. case EEH_RESET_DEACTIVATE:
  1277. ret = eeh_ops->reset(pe, option);
  1278. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
  1279. if (ret)
  1280. break;
  1281. ret = eeh_pe_reenable_devices(pe, include_passed);
  1282. break;
  1283. case EEH_RESET_HOT:
  1284. case EEH_RESET_FUNDAMENTAL:
  1285. /*
  1286. * Proactively freeze the PE to drop all MMIO access
  1287. * during reset, which should be banned as it's always
  1288. * cause recursive EEH error.
  1289. */
  1290. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  1291. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  1292. ret = eeh_ops->reset(pe, option);
  1293. break;
  1294. default:
  1295. pr_debug("%s: Unsupported option %d\n",
  1296. __func__, option);
  1297. ret = -EINVAL;
  1298. }
  1299. return ret;
  1300. }
  1301. EXPORT_SYMBOL_GPL(eeh_pe_reset);
  1302. /**
  1303. * eeh_pe_configure - Configure PCI bridges after PE reset
  1304. * @pe: EEH PE
  1305. *
  1306. * The routine is called to restore the PCI config space for
  1307. * those PCI devices, especially PCI bridges affected by PE
  1308. * reset issued previously.
  1309. */
  1310. int eeh_pe_configure(struct eeh_pe *pe)
  1311. {
  1312. int ret = 0;
  1313. /* Invalid PE ? */
  1314. if (!pe)
  1315. return -ENODEV;
  1316. return ret;
  1317. }
  1318. EXPORT_SYMBOL_GPL(eeh_pe_configure);
  1319. /**
  1320. * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
  1321. * @pe: the indicated PE
  1322. * @type: error type
  1323. * @function: error function
  1324. * @addr: address
  1325. * @mask: address mask
  1326. *
  1327. * The routine is called to inject the specified PCI error, which
  1328. * is determined by @type and @function, to the indicated PE for
  1329. * testing purpose.
  1330. */
  1331. int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
  1332. unsigned long addr, unsigned long mask)
  1333. {
  1334. /* Invalid PE ? */
  1335. if (!pe)
  1336. return -ENODEV;
  1337. /* Unsupported operation ? */
  1338. if (!eeh_ops || !eeh_ops->err_inject)
  1339. return -ENOENT;
  1340. /* Check on PCI error type */
  1341. if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
  1342. return -EINVAL;
  1343. /* Check on PCI error function */
  1344. if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
  1345. return -EINVAL;
  1346. return eeh_ops->err_inject(pe, type, func, addr, mask);
  1347. }
  1348. EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
  1349. static int proc_eeh_show(struct seq_file *m, void *v)
  1350. {
  1351. if (!eeh_enabled()) {
  1352. seq_printf(m, "EEH Subsystem is globally disabled\n");
  1353. seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
  1354. } else {
  1355. seq_printf(m, "EEH Subsystem is enabled\n");
  1356. seq_printf(m,
  1357. "no device=%llu\n"
  1358. "no device node=%llu\n"
  1359. "no config address=%llu\n"
  1360. "check not wanted=%llu\n"
  1361. "eeh_total_mmio_ffs=%llu\n"
  1362. "eeh_false_positives=%llu\n"
  1363. "eeh_slot_resets=%llu\n",
  1364. eeh_stats.no_device,
  1365. eeh_stats.no_dn,
  1366. eeh_stats.no_cfg_addr,
  1367. eeh_stats.ignored_check,
  1368. eeh_stats.total_mmio_ffs,
  1369. eeh_stats.false_positives,
  1370. eeh_stats.slot_resets);
  1371. }
  1372. return 0;
  1373. }
  1374. #ifdef CONFIG_DEBUG_FS
  1375. static int eeh_enable_dbgfs_set(void *data, u64 val)
  1376. {
  1377. if (val)
  1378. eeh_clear_flag(EEH_FORCE_DISABLED);
  1379. else
  1380. eeh_add_flag(EEH_FORCE_DISABLED);
  1381. return 0;
  1382. }
  1383. static int eeh_enable_dbgfs_get(void *data, u64 *val)
  1384. {
  1385. if (eeh_enabled())
  1386. *val = 0x1ul;
  1387. else
  1388. *val = 0x0ul;
  1389. return 0;
  1390. }
  1391. DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
  1392. eeh_enable_dbgfs_set, "0x%llx\n");
  1393. static ssize_t eeh_force_recover_write(struct file *filp,
  1394. const char __user *user_buf,
  1395. size_t count, loff_t *ppos)
  1396. {
  1397. struct pci_controller *hose;
  1398. uint32_t phbid, pe_no;
  1399. struct eeh_pe *pe;
  1400. char buf[20];
  1401. int ret;
  1402. ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
  1403. if (!ret)
  1404. return -EFAULT;
  1405. /*
  1406. * When PE is NULL the event is a "special" event. Rather than
  1407. * recovering a specific PE it forces the EEH core to scan for failed
  1408. * PHBs and recovers each. This needs to be done before any device
  1409. * recoveries can occur.
  1410. */
  1411. if (!strncmp(buf, "hwcheck", 7)) {
  1412. __eeh_send_failure_event(NULL);
  1413. return count;
  1414. }
  1415. ret = sscanf(buf, "%x:%x", &phbid, &pe_no);
  1416. if (ret != 2)
  1417. return -EINVAL;
  1418. hose = pci_find_controller_for_domain(phbid);
  1419. if (!hose)
  1420. return -ENODEV;
  1421. /* Retrieve PE */
  1422. pe = eeh_pe_get(hose, pe_no);
  1423. if (!pe)
  1424. return -ENODEV;
  1425. /*
  1426. * We don't do any state checking here since the detection
  1427. * process is async to the recovery process. The recovery
  1428. * thread *should* not break even if we schedule a recovery
  1429. * from an odd state (e.g. PE removed, or recovery of a
  1430. * non-isolated PE)
  1431. */
  1432. __eeh_send_failure_event(pe);
  1433. return ret < 0 ? ret : count;
  1434. }
  1435. static const struct file_operations eeh_force_recover_fops = {
  1436. .open = simple_open,
  1437. .llseek = no_llseek,
  1438. .write = eeh_force_recover_write,
  1439. };
  1440. static ssize_t eeh_debugfs_dev_usage(struct file *filp,
  1441. char __user *user_buf,
  1442. size_t count, loff_t *ppos)
  1443. {
  1444. static const char usage[] = "input format: <domain>:<bus>:<dev>.<fn>\n";
  1445. return simple_read_from_buffer(user_buf, count, ppos,
  1446. usage, sizeof(usage) - 1);
  1447. }
  1448. static ssize_t eeh_dev_check_write(struct file *filp,
  1449. const char __user *user_buf,
  1450. size_t count, loff_t *ppos)
  1451. {
  1452. uint32_t domain, bus, dev, fn;
  1453. struct pci_dev *pdev;
  1454. struct eeh_dev *edev;
  1455. char buf[20];
  1456. int ret;
  1457. memset(buf, 0, sizeof(buf));
  1458. ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
  1459. if (!ret)
  1460. return -EFAULT;
  1461. ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
  1462. if (ret != 4) {
  1463. pr_err("%s: expected 4 args, got %d\n", __func__, ret);
  1464. return -EINVAL;
  1465. }
  1466. pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
  1467. if (!pdev)
  1468. return -ENODEV;
  1469. edev = pci_dev_to_eeh_dev(pdev);
  1470. if (!edev) {
  1471. pci_err(pdev, "No eeh_dev for this device!\n");
  1472. pci_dev_put(pdev);
  1473. return -ENODEV;
  1474. }
  1475. ret = eeh_dev_check_failure(edev);
  1476. pci_info(pdev, "eeh_dev_check_failure(%04x:%02x:%02x.%01x) = %d\n",
  1477. domain, bus, dev, fn, ret);
  1478. pci_dev_put(pdev);
  1479. return count;
  1480. }
  1481. static const struct file_operations eeh_dev_check_fops = {
  1482. .open = simple_open,
  1483. .llseek = no_llseek,
  1484. .write = eeh_dev_check_write,
  1485. .read = eeh_debugfs_dev_usage,
  1486. };
  1487. static int eeh_debugfs_break_device(struct pci_dev *pdev)
  1488. {
  1489. struct resource *bar = NULL;
  1490. void __iomem *mapped;
  1491. u16 old, bit;
  1492. int i, pos;
  1493. /* Do we have an MMIO BAR to disable? */
  1494. for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
  1495. struct resource *r = &pdev->resource[i];
  1496. if (!r->flags || !r->start)
  1497. continue;
  1498. if (r->flags & IORESOURCE_IO)
  1499. continue;
  1500. if (r->flags & IORESOURCE_UNSET)
  1501. continue;
  1502. bar = r;
  1503. break;
  1504. }
  1505. if (!bar) {
  1506. pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n");
  1507. return -ENXIO;
  1508. }
  1509. pci_err(pdev, "Going to break: %pR\n", bar);
  1510. if (pdev->is_virtfn) {
  1511. #ifndef CONFIG_PCI_IOV
  1512. return -ENXIO;
  1513. #else
  1514. /*
  1515. * VFs don't have a per-function COMMAND register, so the best
  1516. * we can do is clear the Memory Space Enable bit in the PF's
  1517. * SRIOV control reg.
  1518. *
  1519. * Unfortunately, this requires that we have a PF (i.e doesn't
  1520. * work for a passed-through VF) and it has the potential side
  1521. * effect of also causing an EEH on every other VF under the
  1522. * PF. Oh well.
  1523. */
  1524. pdev = pdev->physfn;
  1525. if (!pdev)
  1526. return -ENXIO; /* passed through VFs have no PF */
  1527. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1528. pos += PCI_SRIOV_CTRL;
  1529. bit = PCI_SRIOV_CTRL_MSE;
  1530. #endif /* !CONFIG_PCI_IOV */
  1531. } else {
  1532. bit = PCI_COMMAND_MEMORY;
  1533. pos = PCI_COMMAND;
  1534. }
  1535. /*
  1536. * Process here is:
  1537. *
  1538. * 1. Disable Memory space.
  1539. *
  1540. * 2. Perform an MMIO to the device. This should result in an error
  1541. * (CA / UR) being raised by the device which results in an EEH
  1542. * PE freeze. Using the in_8() accessor skips the eeh detection hook
  1543. * so the freeze hook so the EEH Detection machinery won't be
  1544. * triggered here. This is to match the usual behaviour of EEH
  1545. * where the HW will asyncronously freeze a PE and it's up to
  1546. * the kernel to notice and deal with it.
  1547. *
  1548. * 3. Turn Memory space back on. This is more important for VFs
  1549. * since recovery will probably fail if we don't. For normal
  1550. * the COMMAND register is reset as a part of re-initialising
  1551. * the device.
  1552. *
  1553. * Breaking stuff is the point so who cares if it's racy ;)
  1554. */
  1555. pci_read_config_word(pdev, pos, &old);
  1556. mapped = ioremap(bar->start, PAGE_SIZE);
  1557. if (!mapped) {
  1558. pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar);
  1559. return -ENXIO;
  1560. }
  1561. pci_write_config_word(pdev, pos, old & ~bit);
  1562. in_8(mapped);
  1563. pci_write_config_word(pdev, pos, old);
  1564. iounmap(mapped);
  1565. return 0;
  1566. }
  1567. static ssize_t eeh_dev_break_write(struct file *filp,
  1568. const char __user *user_buf,
  1569. size_t count, loff_t *ppos)
  1570. {
  1571. uint32_t domain, bus, dev, fn;
  1572. struct pci_dev *pdev;
  1573. char buf[20];
  1574. int ret;
  1575. memset(buf, 0, sizeof(buf));
  1576. ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
  1577. if (!ret)
  1578. return -EFAULT;
  1579. ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
  1580. if (ret != 4) {
  1581. pr_err("%s: expected 4 args, got %d\n", __func__, ret);
  1582. return -EINVAL;
  1583. }
  1584. pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
  1585. if (!pdev)
  1586. return -ENODEV;
  1587. ret = eeh_debugfs_break_device(pdev);
  1588. pci_dev_put(pdev);
  1589. if (ret < 0)
  1590. return ret;
  1591. return count;
  1592. }
  1593. static const struct file_operations eeh_dev_break_fops = {
  1594. .open = simple_open,
  1595. .llseek = no_llseek,
  1596. .write = eeh_dev_break_write,
  1597. .read = eeh_debugfs_dev_usage,
  1598. };
  1599. #endif
  1600. static int __init eeh_init_proc(void)
  1601. {
  1602. if (machine_is(pseries) || machine_is(powernv)) {
  1603. proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
  1604. #ifdef CONFIG_DEBUG_FS
  1605. debugfs_create_file_unsafe("eeh_enable", 0600,
  1606. powerpc_debugfs_root, NULL,
  1607. &eeh_enable_dbgfs_ops);
  1608. debugfs_create_u32("eeh_max_freezes", 0600,
  1609. powerpc_debugfs_root, &eeh_max_freezes);
  1610. debugfs_create_bool("eeh_disable_recovery", 0600,
  1611. powerpc_debugfs_root,
  1612. &eeh_debugfs_no_recover);
  1613. debugfs_create_file_unsafe("eeh_dev_check", 0600,
  1614. powerpc_debugfs_root, NULL,
  1615. &eeh_dev_check_fops);
  1616. debugfs_create_file_unsafe("eeh_dev_break", 0600,
  1617. powerpc_debugfs_root, NULL,
  1618. &eeh_dev_break_fops);
  1619. debugfs_create_file_unsafe("eeh_force_recover", 0600,
  1620. powerpc_debugfs_root, NULL,
  1621. &eeh_force_recover_fops);
  1622. eeh_cache_debugfs_init();
  1623. #endif
  1624. }
  1625. return 0;
  1626. }
  1627. __initcall(eeh_init_proc);