cpu_setup_power.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2020, Jordan Niethe, IBM Corporation.
  4. *
  5. * This file contains low level CPU setup functions.
  6. * Originally written in assembly by Benjamin Herrenschmidt & various other
  7. * authors.
  8. */
  9. #include <asm/reg.h>
  10. #include <asm/synch.h>
  11. #include <linux/bitops.h>
  12. #include <asm/cputable.h>
  13. #include <asm/cpu_setup_power.h>
  14. /* Disable CPU_FTR_HVMODE and return false if MSR:HV is not set */
  15. static bool init_hvmode_206(struct cpu_spec *t)
  16. {
  17. u64 msr;
  18. msr = mfmsr();
  19. if (msr & MSR_HV)
  20. return true;
  21. t->cpu_features &= ~(CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST);
  22. return false;
  23. }
  24. static void init_LPCR_ISA300(u64 lpcr, u64 lpes)
  25. {
  26. /* POWER9 has no VRMASD */
  27. lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES;
  28. lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2;
  29. lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD;
  30. lpcr &= ~LPCR_HDICE; /* clear HDICE */
  31. lpcr |= (4ull << LPCR_VC_SH);
  32. mtspr(SPRN_LPCR, lpcr);
  33. isync();
  34. }
  35. /*
  36. * Setup a sane LPCR:
  37. * Called with initial LPCR and desired LPES 2-bit value
  38. *
  39. * LPES = 0b01 (HSRR0/1 used for 0x500)
  40. * PECE = 0b111
  41. * DPFD = 4
  42. * HDICE = 0
  43. * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  44. * VRMASD = 0b10000 (L=1, LP=00)
  45. *
  46. * Other bits untouched for now
  47. */
  48. static void init_LPCR_ISA206(u64 lpcr, u64 lpes)
  49. {
  50. lpcr |= (0x10ull << LPCR_VRMASD_SH) & LPCR_VRMASD;
  51. init_LPCR_ISA300(lpcr, lpes);
  52. }
  53. static void init_FSCR(void)
  54. {
  55. u64 fscr;
  56. fscr = mfspr(SPRN_FSCR);
  57. fscr |= FSCR_TAR|FSCR_EBB;
  58. mtspr(SPRN_FSCR, fscr);
  59. }
  60. static void init_FSCR_power9(void)
  61. {
  62. u64 fscr;
  63. fscr = mfspr(SPRN_FSCR);
  64. fscr |= FSCR_SCV;
  65. mtspr(SPRN_FSCR, fscr);
  66. init_FSCR();
  67. }
  68. static void init_FSCR_power10(void)
  69. {
  70. u64 fscr;
  71. fscr = mfspr(SPRN_FSCR);
  72. fscr |= FSCR_PREFIX;
  73. mtspr(SPRN_FSCR, fscr);
  74. init_FSCR_power9();
  75. }
  76. static void init_HFSCR(void)
  77. {
  78. u64 hfscr;
  79. hfscr = mfspr(SPRN_HFSCR);
  80. hfscr |= HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|HFSCR_DSCR|\
  81. HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP;
  82. mtspr(SPRN_HFSCR, hfscr);
  83. }
  84. static void init_PMU_HV(void)
  85. {
  86. mtspr(SPRN_MMCRC, 0);
  87. }
  88. static void init_PMU_HV_ISA207(void)
  89. {
  90. mtspr(SPRN_MMCRH, 0);
  91. }
  92. static void init_PMU(void)
  93. {
  94. mtspr(SPRN_MMCRA, 0);
  95. mtspr(SPRN_MMCR0, 0);
  96. mtspr(SPRN_MMCR1, 0);
  97. mtspr(SPRN_MMCR2, 0);
  98. }
  99. static void init_PMU_ISA207(void)
  100. {
  101. mtspr(SPRN_MMCRS, 0);
  102. }
  103. static void init_PMU_ISA31(void)
  104. {
  105. mtspr(SPRN_MMCR3, 0);
  106. mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
  107. mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
  108. }
  109. /*
  110. * Note that we can be called twice of pseudo-PVRs.
  111. * The parameter offset is not used.
  112. */
  113. void __setup_cpu_power7(unsigned long offset, struct cpu_spec *t)
  114. {
  115. if (!init_hvmode_206(t))
  116. return;
  117. mtspr(SPRN_LPID, 0);
  118. mtspr(SPRN_PCR, PCR_MASK);
  119. init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
  120. }
  121. void __restore_cpu_power7(void)
  122. {
  123. u64 msr;
  124. msr = mfmsr();
  125. if (!(msr & MSR_HV))
  126. return;
  127. mtspr(SPRN_LPID, 0);
  128. mtspr(SPRN_PCR, PCR_MASK);
  129. init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
  130. }
  131. void __setup_cpu_power8(unsigned long offset, struct cpu_spec *t)
  132. {
  133. init_FSCR();
  134. init_PMU();
  135. init_PMU_ISA207();
  136. if (!init_hvmode_206(t))
  137. return;
  138. mtspr(SPRN_LPID, 0);
  139. mtspr(SPRN_PCR, PCR_MASK);
  140. init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
  141. init_HFSCR();
  142. init_PMU_HV();
  143. init_PMU_HV_ISA207();
  144. }
  145. void __restore_cpu_power8(void)
  146. {
  147. u64 msr;
  148. init_FSCR();
  149. init_PMU();
  150. init_PMU_ISA207();
  151. msr = mfmsr();
  152. if (!(msr & MSR_HV))
  153. return;
  154. mtspr(SPRN_LPID, 0);
  155. mtspr(SPRN_PCR, PCR_MASK);
  156. init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
  157. init_HFSCR();
  158. init_PMU_HV();
  159. init_PMU_HV_ISA207();
  160. }
  161. void __setup_cpu_power9(unsigned long offset, struct cpu_spec *t)
  162. {
  163. init_FSCR_power9();
  164. init_PMU();
  165. if (!init_hvmode_206(t))
  166. return;
  167. mtspr(SPRN_PSSCR, 0);
  168. mtspr(SPRN_LPID, 0);
  169. mtspr(SPRN_PID, 0);
  170. mtspr(SPRN_PCR, PCR_MASK);
  171. init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
  172. LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
  173. init_HFSCR();
  174. init_PMU_HV();
  175. }
  176. void __restore_cpu_power9(void)
  177. {
  178. u64 msr;
  179. init_FSCR_power9();
  180. init_PMU();
  181. msr = mfmsr();
  182. if (!(msr & MSR_HV))
  183. return;
  184. mtspr(SPRN_PSSCR, 0);
  185. mtspr(SPRN_LPID, 0);
  186. mtspr(SPRN_PID, 0);
  187. mtspr(SPRN_PCR, PCR_MASK);
  188. init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
  189. LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
  190. init_HFSCR();
  191. init_PMU_HV();
  192. }
  193. void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t)
  194. {
  195. init_FSCR_power10();
  196. init_PMU();
  197. init_PMU_ISA31();
  198. if (!init_hvmode_206(t))
  199. return;
  200. mtspr(SPRN_PSSCR, 0);
  201. mtspr(SPRN_LPID, 0);
  202. mtspr(SPRN_PID, 0);
  203. mtspr(SPRN_PCR, PCR_MASK);
  204. init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
  205. LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
  206. init_HFSCR();
  207. init_PMU_HV();
  208. }
  209. void __restore_cpu_power10(void)
  210. {
  211. u64 msr;
  212. init_FSCR_power10();
  213. init_PMU();
  214. init_PMU_ISA31();
  215. msr = mfmsr();
  216. if (!(msr & MSR_HV))
  217. return;
  218. mtspr(SPRN_PSSCR, 0);
  219. mtspr(SPRN_LPID, 0);
  220. mtspr(SPRN_PID, 0);
  221. mtspr(SPRN_PCR, PCR_MASK);
  222. init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
  223. LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
  224. init_HFSCR();
  225. init_PMU_HV();
  226. }