cpu_setup_fsl_booke.S 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * This file contains low level CPU setup functions.
  4. * Kumar Gala <galak@kernel.crashing.org>
  5. * Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * Based on cpu_setup_6xx code by
  8. * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  9. */
  10. #include <asm/page.h>
  11. #include <asm/processor.h>
  12. #include <asm/cputable.h>
  13. #include <asm/ppc_asm.h>
  14. #include <asm/nohash/mmu-book3e.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/mpc85xx.h>
  17. _GLOBAL(__e500_icache_setup)
  18. mfspr r0, SPRN_L1CSR1
  19. andi. r3, r0, L1CSR1_ICE
  20. bnelr /* Already enabled */
  21. oris r0, r0, L1CSR1_CPE@h
  22. ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
  23. mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
  24. isync
  25. blr
  26. _GLOBAL(__e500_dcache_setup)
  27. mfspr r0, SPRN_L1CSR0
  28. andi. r3, r0, L1CSR0_DCE
  29. bnelr /* Already enabled */
  30. msync
  31. isync
  32. li r0, 0
  33. mtspr SPRN_L1CSR0, r0 /* Disable */
  34. msync
  35. isync
  36. li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
  37. mtspr SPRN_L1CSR0, r0 /* Invalidate */
  38. isync
  39. 1: mfspr r0, SPRN_L1CSR0
  40. andi. r3, r0, L1CSR0_CLFC
  41. bne+ 1b /* Wait for lock bits reset */
  42. oris r0, r0, L1CSR0_CPE@h
  43. ori r0, r0, L1CSR0_DCE
  44. msync
  45. isync
  46. mtspr SPRN_L1CSR0, r0 /* Enable */
  47. isync
  48. blr
  49. /*
  50. * FIXME - we haven't yet done testing to determine a reasonable default
  51. * value for PW20_WAIT_IDLE_BIT.
  52. */
  53. #define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
  54. _GLOBAL(setup_pw20_idle)
  55. mfspr r3, SPRN_PWRMGTCR0
  56. /* Set PW20_WAIT bit, enable pw20 state*/
  57. ori r3, r3, PWRMGTCR0_PW20_WAIT
  58. li r11, PW20_WAIT_IDLE_BIT
  59. /* Set Automatic PW20 Core Idle Count */
  60. rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
  61. mtspr SPRN_PWRMGTCR0, r3
  62. blr
  63. /*
  64. * FIXME - we haven't yet done testing to determine a reasonable default
  65. * value for AV_WAIT_IDLE_BIT.
  66. */
  67. #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
  68. _GLOBAL(setup_altivec_idle)
  69. mfspr r3, SPRN_PWRMGTCR0
  70. /* Enable Altivec Idle */
  71. oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
  72. li r11, AV_WAIT_IDLE_BIT
  73. /* Set Automatic AltiVec Idle Count */
  74. rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
  75. mtspr SPRN_PWRMGTCR0, r3
  76. blr
  77. #ifdef CONFIG_PPC_E500MC
  78. _GLOBAL(__setup_cpu_e6500)
  79. mflr r6
  80. #ifdef CONFIG_PPC64
  81. bl setup_altivec_ivors
  82. /* Touch IVOR42 only if the CPU supports E.HV category */
  83. mfspr r10,SPRN_MMUCFG
  84. rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
  85. beq 1f
  86. bl setup_lrat_ivor
  87. 1:
  88. #endif
  89. bl setup_pw20_idle
  90. bl setup_altivec_idle
  91. bl __setup_cpu_e5500
  92. mtlr r6
  93. blr
  94. #endif /* CONFIG_PPC_E500MC */
  95. #ifdef CONFIG_PPC32
  96. #ifdef CONFIG_E200
  97. _GLOBAL(__setup_cpu_e200)
  98. /* enable dedicated debug exception handling resources (Debug APU) */
  99. mfspr r3,SPRN_HID0
  100. ori r3,r3,HID0_DAPUEN@l
  101. mtspr SPRN_HID0,r3
  102. b __setup_e200_ivors
  103. #endif /* CONFIG_E200 */
  104. #ifdef CONFIG_E500
  105. #ifndef CONFIG_PPC_E500MC
  106. _GLOBAL(__setup_cpu_e500v1)
  107. _GLOBAL(__setup_cpu_e500v2)
  108. mflr r4
  109. bl __e500_icache_setup
  110. bl __e500_dcache_setup
  111. bl __setup_e500_ivors
  112. #if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
  113. /* Ensure that RFXE is set */
  114. mfspr r3,SPRN_HID1
  115. oris r3,r3,HID1_RFXE@h
  116. mtspr SPRN_HID1,r3
  117. #endif
  118. mtlr r4
  119. blr
  120. #else /* CONFIG_PPC_E500MC */
  121. _GLOBAL(__setup_cpu_e500mc)
  122. _GLOBAL(__setup_cpu_e5500)
  123. mflr r5
  124. bl __e500_icache_setup
  125. bl __e500_dcache_setup
  126. bl __setup_e500mc_ivors
  127. /*
  128. * We only want to touch IVOR38-41 if we're running on hardware
  129. * that supports category E.HV. The architectural way to determine
  130. * this is MMUCFG[LPIDSIZE].
  131. */
  132. mfspr r3, SPRN_MMUCFG
  133. rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
  134. beq 1f
  135. bl __setup_ehv_ivors
  136. b 2f
  137. 1:
  138. lwz r3, CPU_SPEC_FEATURES(r4)
  139. /* We need this check as cpu_setup is also called for
  140. * the secondary cores. So, if we have already cleared
  141. * the feature on the primary core, avoid doing it on the
  142. * secondary core.
  143. */
  144. andi. r6, r3, CPU_FTR_EMB_HV
  145. beq 2f
  146. rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
  147. stw r3, CPU_SPEC_FEATURES(r4)
  148. 2:
  149. mtlr r5
  150. blr
  151. #endif /* CONFIG_PPC_E500MC */
  152. #endif /* CONFIG_E500 */
  153. #endif /* CONFIG_PPC32 */
  154. #ifdef CONFIG_PPC_BOOK3E_64
  155. _GLOBAL(__restore_cpu_e6500)
  156. mflr r5
  157. bl setup_altivec_ivors
  158. /* Touch IVOR42 only if the CPU supports E.HV category */
  159. mfspr r10,SPRN_MMUCFG
  160. rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
  161. beq 1f
  162. bl setup_lrat_ivor
  163. 1:
  164. bl setup_pw20_idle
  165. bl setup_altivec_idle
  166. bl __restore_cpu_e5500
  167. mtlr r5
  168. blr
  169. _GLOBAL(__restore_cpu_e5500)
  170. mflr r4
  171. bl __e500_icache_setup
  172. bl __e500_dcache_setup
  173. bl __setup_base_ivors
  174. bl setup_perfmon_ivor
  175. bl setup_doorbell_ivors
  176. /*
  177. * We only want to touch IVOR38-41 if we're running on hardware
  178. * that supports category E.HV. The architectural way to determine
  179. * this is MMUCFG[LPIDSIZE].
  180. */
  181. mfspr r10,SPRN_MMUCFG
  182. rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
  183. beq 1f
  184. bl setup_ehv_ivors
  185. 1:
  186. mtlr r4
  187. blr
  188. _GLOBAL(__setup_cpu_e5500)
  189. mflr r5
  190. bl __e500_icache_setup
  191. bl __e500_dcache_setup
  192. bl __setup_base_ivors
  193. bl setup_perfmon_ivor
  194. bl setup_doorbell_ivors
  195. /*
  196. * We only want to touch IVOR38-41 if we're running on hardware
  197. * that supports category E.HV. The architectural way to determine
  198. * this is MMUCFG[LPIDSIZE].
  199. */
  200. mfspr r10,SPRN_MMUCFG
  201. rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
  202. beq 1f
  203. bl setup_ehv_ivors
  204. b 2f
  205. 1:
  206. ld r10,CPU_SPEC_FEATURES(r4)
  207. LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
  208. andc r10,r10,r9
  209. std r10,CPU_SPEC_FEATURES(r4)
  210. 2:
  211. mtlr r5
  212. blr
  213. #endif
  214. /* flush L1 data cache, it can apply to e500v2, e500mc and e5500 */
  215. _GLOBAL(flush_dcache_L1)
  216. mfmsr r10
  217. wrteei 0
  218. mfspr r3,SPRN_L1CFG0
  219. rlwinm r5,r3,9,3 /* Extract cache block size */
  220. twlgti r5,1 /* Only 32 and 64 byte cache blocks
  221. * are currently defined.
  222. */
  223. li r4,32
  224. subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
  225. * log2(number of ways)
  226. */
  227. slw r5,r4,r5 /* r5 = cache block size */
  228. rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
  229. mulli r7,r7,13 /* An 8-way cache will require 13
  230. * loads per set.
  231. */
  232. slw r7,r7,r6
  233. /* save off HID0 and set DCFA */
  234. mfspr r8,SPRN_HID0
  235. ori r9,r8,HID0_DCFA@l
  236. mtspr SPRN_HID0,r9
  237. isync
  238. LOAD_REG_IMMEDIATE(r6, KERNELBASE)
  239. mr r4, r6
  240. mtctr r7
  241. 1: lwz r3,0(r4) /* Load... */
  242. add r4,r4,r5
  243. bdnz 1b
  244. msync
  245. mr r4, r6
  246. mtctr r7
  247. 1: dcbf 0,r4 /* ...and flush. */
  248. add r4,r4,r5
  249. bdnz 1b
  250. /* restore HID0 */
  251. mtspr SPRN_HID0,r8
  252. isync
  253. wrtee r10
  254. blr
  255. has_L2_cache:
  256. /* skip L2 cache on P2040/P2040E as they have no L2 cache */
  257. mfspr r3, SPRN_SVR
  258. /* shift right by 8 bits and clear E bit of SVR */
  259. rlwinm r4, r3, 24, ~0x800
  260. lis r3, SVR_P2040@h
  261. ori r3, r3, SVR_P2040@l
  262. cmpw r4, r3
  263. beq 1f
  264. li r3, 1
  265. blr
  266. 1:
  267. li r3, 0
  268. blr
  269. /* flush backside L2 cache */
  270. flush_backside_L2_cache:
  271. mflr r10
  272. bl has_L2_cache
  273. mtlr r10
  274. cmpwi r3, 0
  275. beq 2f
  276. /* Flush the L2 cache */
  277. mfspr r3, SPRN_L2CSR0
  278. ori r3, r3, L2CSR0_L2FL@l
  279. msync
  280. isync
  281. mtspr SPRN_L2CSR0,r3
  282. isync
  283. /* check if it is complete */
  284. 1: mfspr r3,SPRN_L2CSR0
  285. andi. r3, r3, L2CSR0_L2FL@l
  286. bne 1b
  287. 2:
  288. blr
  289. _GLOBAL(cpu_down_flush_e500v2)
  290. mflr r0
  291. bl flush_dcache_L1
  292. mtlr r0
  293. blr
  294. _GLOBAL(cpu_down_flush_e500mc)
  295. _GLOBAL(cpu_down_flush_e5500)
  296. mflr r0
  297. bl flush_dcache_L1
  298. bl flush_backside_L2_cache
  299. mtlr r0
  300. blr
  301. /* L1 Data Cache of e6500 contains no modified data, no flush is required */
  302. _GLOBAL(cpu_down_flush_e6500)
  303. blr