wii-head.S 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * arch/powerpc/boot/wii-head.S
  4. *
  5. * Nintendo Wii bootwrapper entry.
  6. * Copyright (C) 2008-2009 The GameCube Linux Team
  7. * Copyright (C) 2008,2009 Albert Herranz
  8. */
  9. #include "ppc_asm.h"
  10. /*
  11. * The entry code does no assumptions regarding:
  12. * - if the data and instruction caches are enabled or not
  13. * - if the MMU is enabled or not
  14. * - if the high BATs are enabled or not
  15. *
  16. * We enable the high BATs, enable the caches if not already enabled,
  17. * enable the MMU with an identity mapping scheme and jump to the start code.
  18. */
  19. .text
  20. .globl _zimage_start
  21. _zimage_start:
  22. /* turn the MMU off */
  23. mfmsr 9
  24. rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
  25. bcl 20, 31, 1f
  26. 1:
  27. mflr 8
  28. clrlwi 8, 8, 3 /* convert to a real address */
  29. addi 8, 8, _mmu_off - 1b
  30. mtsrr0 8
  31. mtsrr1 9
  32. rfi
  33. _mmu_off:
  34. /* MMU disabled */
  35. /* setup BATs */
  36. isync
  37. li 8, 0
  38. mtspr 0x210, 8 /* IBAT0U */
  39. mtspr 0x212, 8 /* IBAT1U */
  40. mtspr 0x214, 8 /* IBAT2U */
  41. mtspr 0x216, 8 /* IBAT3U */
  42. mtspr 0x218, 8 /* DBAT0U */
  43. mtspr 0x21a, 8 /* DBAT1U */
  44. mtspr 0x21c, 8 /* DBAT2U */
  45. mtspr 0x21e, 8 /* DBAT3U */
  46. mtspr 0x230, 8 /* IBAT4U */
  47. mtspr 0x232, 8 /* IBAT5U */
  48. mtspr 0x234, 8 /* IBAT6U */
  49. mtspr 0x236, 8 /* IBAT7U */
  50. mtspr 0x238, 8 /* DBAT4U */
  51. mtspr 0x23a, 8 /* DBAT5U */
  52. mtspr 0x23c, 8 /* DBAT6U */
  53. mtspr 0x23e, 8 /* DBAT7U */
  54. li 8, 0x01ff /* first 16MiB */
  55. li 9, 0x0002 /* rw */
  56. mtspr 0x211, 9 /* IBAT0L */
  57. mtspr 0x210, 8 /* IBAT0U */
  58. mtspr 0x219, 9 /* DBAT0L */
  59. mtspr 0x218, 8 /* DBAT0U */
  60. lis 8, 0x0c00 /* I/O mem */
  61. ori 8, 8, 0x3ff /* 32MiB */
  62. lis 9, 0x0c00
  63. ori 9, 9, 0x002a /* uncached, guarded, rw */
  64. mtspr 0x21b, 9 /* DBAT1L */
  65. mtspr 0x21a, 8 /* DBAT1U */
  66. lis 8, 0x0100 /* next 8MiB */
  67. ori 8, 8, 0x00ff /* 8MiB */
  68. lis 9, 0x0100
  69. ori 9, 9, 0x0002 /* rw */
  70. mtspr 0x215, 9 /* IBAT2L */
  71. mtspr 0x214, 8 /* IBAT2U */
  72. mtspr 0x21d, 9 /* DBAT2L */
  73. mtspr 0x21c, 8 /* DBAT2U */
  74. lis 8, 0x1000 /* MEM2 */
  75. ori 8, 8, 0x07ff /* 64MiB */
  76. lis 9, 0x1000
  77. ori 9, 9, 0x0002 /* rw */
  78. mtspr 0x216, 8 /* IBAT3U */
  79. mtspr 0x217, 9 /* IBAT3L */
  80. mtspr 0x21e, 8 /* DBAT3U */
  81. mtspr 0x21f, 9 /* DBAT3L */
  82. /* enable the high BATs */
  83. mfspr 8, 0x3f3 /* HID4 */
  84. oris 8, 8, 0x0200
  85. mtspr 0x3f3, 8 /* HID4 */
  86. /* enable and invalidate the caches if not already enabled */
  87. mfspr 8, 0x3f0 /* HID0 */
  88. andi. 0, 8, (1<<15) /* HID0_ICE */
  89. bne 1f
  90. ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
  91. 1:
  92. andi. 0, 8, (1<<14) /* HID0_DCE */
  93. bne 1f
  94. ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
  95. 1:
  96. mtspr 0x3f0, 8 /* HID0 */
  97. isync
  98. /* initialize arguments */
  99. li 3, 0
  100. li 4, 0
  101. li 5, 0
  102. /* turn the MMU on */
  103. bcl 20, 31, 1f
  104. 1:
  105. mflr 8
  106. addi 8, 8, _mmu_on - 1b
  107. mfmsr 9
  108. ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
  109. mtsrr0 8
  110. mtsrr1 9
  111. sync
  112. rfi
  113. _mmu_on:
  114. /* turn on the front blue led (aka: yay! we got here!) */
  115. lis 8, 0x0d00
  116. ori 8, 8, 0x00c0
  117. lwz 9, 0(8)
  118. ori 9, 9, 0x20
  119. stw 9, 0(8)
  120. b _zimage_start_lib