dcr.h 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _PPC_BOOT_DCR_H_
  3. #define _PPC_BOOT_DCR_H_
  4. #define mfdcr(rn) \
  5. ({ \
  6. unsigned long rval; \
  7. asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
  8. rval; \
  9. })
  10. #define mtdcr(rn, val) \
  11. asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
  12. #define mfdcrx(rn) \
  13. ({ \
  14. unsigned long rval; \
  15. asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
  16. rval; \
  17. })
  18. #define mtdcrx(rn, val) \
  19. ({ \
  20. asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
  21. })
  22. /* 440GP/440GX SDRAM controller DCRs */
  23. #define DCRN_SDRAM0_CFGADDR 0x010
  24. #define DCRN_SDRAM0_CFGDATA 0x011
  25. #define SDRAM0_READ(offset) ({\
  26. mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
  27. mfdcr(DCRN_SDRAM0_CFGDATA); })
  28. #define SDRAM0_WRITE(offset, data) ({\
  29. mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
  30. mtdcr(DCRN_SDRAM0_CFGDATA, data); })
  31. #define SDRAM0_B0CR 0x40
  32. #define SDRAM0_B1CR 0x44
  33. #define SDRAM0_B2CR 0x48
  34. #define SDRAM0_B3CR 0x4c
  35. static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
  36. SDRAM0_B2CR, SDRAM0_B3CR };
  37. #define SDRAM_CONFIG_BANK_ENABLE 0x00000001
  38. #define SDRAM_CONFIG_SIZE_MASK 0x000e0000
  39. #define SDRAM_CONFIG_BANK_SIZE(reg) \
  40. (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
  41. /* 440GP External Bus Controller (EBC) */
  42. #define DCRN_EBC0_CFGADDR 0x012
  43. #define DCRN_EBC0_CFGDATA 0x013
  44. #define EBC_NUM_BANKS 8
  45. #define EBC_B0CR 0x00
  46. #define EBC_B1CR 0x01
  47. #define EBC_B2CR 0x02
  48. #define EBC_B3CR 0x03
  49. #define EBC_B4CR 0x04
  50. #define EBC_B5CR 0x05
  51. #define EBC_B6CR 0x06
  52. #define EBC_B7CR 0x07
  53. #define EBC_BXCR(n) (n)
  54. #define EBC_BXCR_BAS 0xfff00000
  55. #define EBC_BXCR_BS 0x000e0000
  56. #define EBC_BXCR_BANK_SIZE(reg) \
  57. (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
  58. #define EBC_BXCR_BU 0x00018000
  59. #define EBC_BXCR_BU_OFF 0x00000000
  60. #define EBC_BXCR_BU_RO 0x00008000
  61. #define EBC_BXCR_BU_WO 0x00010000
  62. #define EBC_BXCR_BU_RW 0x00018000
  63. #define EBC_BXCR_BW 0x00006000
  64. #define EBC_B0AP 0x10
  65. #define EBC_B1AP 0x11
  66. #define EBC_B2AP 0x12
  67. #define EBC_B3AP 0x13
  68. #define EBC_B4AP 0x14
  69. #define EBC_B5AP 0x15
  70. #define EBC_B6AP 0x16
  71. #define EBC_B7AP 0x17
  72. #define EBC_BXAP(n) (0x10+(n))
  73. #define EBC_BEAR 0x20
  74. #define EBC_BESR 0x21
  75. #define EBC_CFG 0x23
  76. #define EBC_CID 0x24
  77. /* 440GP Clock, PM, chip control */
  78. #define DCRN_CPC0_SR 0x0b0
  79. #define DCRN_CPC0_ER 0x0b1
  80. #define DCRN_CPC0_FR 0x0b2
  81. #define DCRN_CPC0_SYS0 0x0e0
  82. #define CPC0_SYS0_TUNE 0xffc00000
  83. #define CPC0_SYS0_FBDV_MASK 0x003c0000
  84. #define CPC0_SYS0_FWDVA_MASK 0x00038000
  85. #define CPC0_SYS0_FWDVB_MASK 0x00007000
  86. #define CPC0_SYS0_OPDV_MASK 0x00000c00
  87. #define CPC0_SYS0_EPDV_MASK 0x00000300
  88. /* Helper macros to compute the actual clock divider values from the
  89. * encodings in the CPC0 register */
  90. #define CPC0_SYS0_FBDV(reg) \
  91. ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
  92. #define CPC0_SYS0_FWDVA(reg) \
  93. (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
  94. #define CPC0_SYS0_FWDVB(reg) \
  95. (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
  96. #define CPC0_SYS0_OPDV(reg) \
  97. ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
  98. #define CPC0_SYS0_EPDV(reg) \
  99. ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
  100. #define CPC0_SYS0_EXTSL 0x00000080
  101. #define CPC0_SYS0_RW_MASK 0x00000060
  102. #define CPC0_SYS0_RL 0x00000010
  103. #define CPC0_SYS0_ZMIISL_MASK 0x0000000c
  104. #define CPC0_SYS0_BYPASS 0x00000002
  105. #define CPC0_SYS0_NTO1 0x00000001
  106. #define DCRN_CPC0_SYS1 0x0e1
  107. #define DCRN_CPC0_CUST0 0x0e2
  108. #define DCRN_CPC0_CUST1 0x0e3
  109. #define DCRN_CPC0_STRP0 0x0e4
  110. #define DCRN_CPC0_STRP1 0x0e5
  111. #define DCRN_CPC0_STRP2 0x0e6
  112. #define DCRN_CPC0_STRP3 0x0e7
  113. #define DCRN_CPC0_GPIO 0x0e8
  114. #define DCRN_CPC0_PLB 0x0e9
  115. #define DCRN_CPC0_CR1 0x0ea
  116. #define DCRN_CPC0_CR0 0x0eb
  117. #define CPC0_CR0_SWE 0x80000000
  118. #define CPC0_CR0_CETE 0x40000000
  119. #define CPC0_CR0_U1FCS 0x20000000
  120. #define CPC0_CR0_U0DTE 0x10000000
  121. #define CPC0_CR0_U0DRE 0x08000000
  122. #define CPC0_CR0_U0DC 0x04000000
  123. #define CPC0_CR0_U1DTE 0x02000000
  124. #define CPC0_CR0_U1DRE 0x01000000
  125. #define CPC0_CR0_U1DC 0x00800000
  126. #define CPC0_CR0_U0EC 0x00400000
  127. #define CPC0_CR0_U1EC 0x00200000
  128. #define CPC0_CR0_UDIV_MASK 0x001f0000
  129. #define CPC0_CR0_UDIV(reg) \
  130. ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
  131. #define DCRN_CPC0_MIRQ0 0x0ec
  132. #define DCRN_CPC0_MIRQ1 0x0ed
  133. #define DCRN_CPC0_JTAGID 0x0ef
  134. #define DCRN_MAL0_CFG 0x180
  135. #define MAL_RESET 0x80000000
  136. /* 440EP Clock/Power-on Reset regs */
  137. #define DCRN_CPR0_ADDR 0xc
  138. #define DCRN_CPR0_DATA 0xd
  139. #define CPR0_PLLD0 0x60
  140. #define CPR0_OPBD0 0xc0
  141. #define CPR0_PERD0 0xe0
  142. #define CPR0_PRIMBD0 0xa0
  143. #define CPR0_SCPID 0x120
  144. #define CPR0_PLLC0 0x40
  145. /* 405GP Clocking/Power Management/Chip Control regs */
  146. #define DCRN_CPC0_PLLMR 0xb0
  147. #define DCRN_405_CPC0_CR0 0xb1
  148. #define DCRN_405_CPC0_CR1 0xb2
  149. #define DCRN_405_CPC0_PSR 0xb4
  150. /* 405EP Clocking/Power Management/Chip Control regs */
  151. #define DCRN_CPC0_PLLMR0 0xf0
  152. #define DCRN_CPC0_PLLMR1 0xf4
  153. #define DCRN_CPC0_UCR 0xf5
  154. /* 440GX/405EX Clock Control reg */
  155. #define DCRN_CPR0_CLKUPD 0x020
  156. #define DCRN_CPR0_PLLC 0x040
  157. #define DCRN_CPR0_PLLD 0x060
  158. #define DCRN_CPR0_PRIMAD 0x080
  159. #define DCRN_CPR0_PRIMBD 0x0a0
  160. #define DCRN_CPR0_OPBD 0x0c0
  161. #define DCRN_CPR0_PERD 0x0e0
  162. #define DCRN_CPR0_MALD 0x100
  163. #define DCRN_SDR0_CONFIG_ADDR 0xe
  164. #define DCRN_SDR0_CONFIG_DATA 0xf
  165. /* SDR read/write helper macros */
  166. #define SDR0_READ(offset) ({\
  167. mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
  168. mfdcr(DCRN_SDR0_CONFIG_DATA); })
  169. #define SDR0_WRITE(offset, data) ({\
  170. mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
  171. mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
  172. #define DCRN_SDR0_UART0 0x0120
  173. #define DCRN_SDR0_UART1 0x0121
  174. #define DCRN_SDR0_UART2 0x0122
  175. #define DCRN_SDR0_UART3 0x0123
  176. /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
  177. #define DCRN_CPR0_CFGADDR 0xc
  178. #define DCRN_CPR0_CFGDATA 0xd
  179. #define CPR0_READ(offset) ({\
  180. mtdcr(DCRN_CPR0_CFGADDR, offset); \
  181. mfdcr(DCRN_CPR0_CFGDATA); })
  182. #define CPR0_WRITE(offset, data) ({\
  183. mtdcr(DCRN_CPR0_CFGADDR, offset); \
  184. mtdcr(DCRN_CPR0_CFGDATA, data); })
  185. #endif /* _PPC_BOOT_DCR_H_ */