cuboot-pq2.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Old U-boot compatibility for PowerQUICC II
  4. * (a.k.a. 82xx with CPM, not the 8240 family of chips)
  5. *
  6. * Author: Scott Wood <scottwood@freescale.com>
  7. *
  8. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  9. */
  10. #include "ops.h"
  11. #include "stdio.h"
  12. #include "cuboot.h"
  13. #include "io.h"
  14. #include "fsl-soc.h"
  15. #define TARGET_CPM2
  16. #define TARGET_HAS_ETH1
  17. #include "ppcboot.h"
  18. static bd_t bd;
  19. struct cs_range {
  20. u32 csnum;
  21. u32 base; /* must be zero */
  22. u32 addr;
  23. u32 size;
  24. };
  25. struct pci_range {
  26. u32 flags;
  27. u32 pci_addr[2];
  28. u32 phys_addr;
  29. u32 size[2];
  30. };
  31. struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
  32. struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
  33. /* Different versions of u-boot put the BCSR in different places, and
  34. * some don't set up the PCI PIC at all, so we assume the device tree is
  35. * sane and update the BRx registers appropriately.
  36. *
  37. * For any node defined as compatible with fsl,pq2-localbus,
  38. * #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
  39. * Ranges must be for whole chip selects.
  40. */
  41. static void update_cs_ranges(void)
  42. {
  43. void *bus_node, *parent_node;
  44. u32 *ctrl_addr;
  45. unsigned long ctrl_size;
  46. u32 naddr, nsize;
  47. int len;
  48. int i;
  49. bus_node = finddevice("/localbus");
  50. if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
  51. return;
  52. dt_get_reg_format(bus_node, &naddr, &nsize);
  53. if (naddr != 2 || nsize != 1)
  54. goto err;
  55. parent_node = get_parent(bus_node);
  56. if (!parent_node)
  57. goto err;
  58. dt_get_reg_format(parent_node, &naddr, &nsize);
  59. if (naddr != 1 || nsize != 1)
  60. goto err;
  61. if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
  62. &ctrl_size))
  63. goto err;
  64. len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
  65. for (i = 0; i < len / sizeof(struct cs_range); i++) {
  66. u32 base, option;
  67. int cs = cs_ranges_buf[i].csnum;
  68. if (cs >= ctrl_size / 8)
  69. goto err;
  70. if (cs_ranges_buf[i].base != 0)
  71. goto err;
  72. base = in_be32(&ctrl_addr[cs * 2]);
  73. /* If CS is already valid, use the existing flags.
  74. * Otherwise, guess a sane default.
  75. */
  76. if (base & 1) {
  77. base &= 0x7fff;
  78. option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
  79. } else {
  80. base = 0x1801;
  81. option = 0x10;
  82. }
  83. out_be32(&ctrl_addr[cs * 2], 0);
  84. out_be32(&ctrl_addr[cs * 2 + 1],
  85. option | ~(cs_ranges_buf[i].size - 1));
  86. out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
  87. }
  88. return;
  89. err:
  90. printf("Bad /localbus node\r\n");
  91. }
  92. /* Older u-boots don't set PCI up properly. Update the hardware to match
  93. * the device tree. The prefetch mem region and non-prefetch mem region
  94. * must be contiguous in the host bus. As required by the PCI binding,
  95. * PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
  96. * 32-bit PCI is supported. All three region types (prefetchable mem,
  97. * non-prefetchable mem, and I/O) must be present.
  98. */
  99. static void fixup_pci(void)
  100. {
  101. struct pci_range *mem = NULL, *mmio = NULL,
  102. *io = NULL, *mem_base = NULL;
  103. u32 *pci_regs[3];
  104. u8 *soc_regs;
  105. int i, len;
  106. void *node, *parent_node;
  107. u32 naddr, nsize, mem_pow2, mem_mask;
  108. node = finddevice("/pci");
  109. if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
  110. return;
  111. for (i = 0; i < 3; i++)
  112. if (!dt_xlate_reg(node, i,
  113. (unsigned long *)&pci_regs[i], NULL))
  114. goto err;
  115. soc_regs = (u8 *)fsl_get_immr();
  116. if (!soc_regs)
  117. goto unhandled;
  118. dt_get_reg_format(node, &naddr, &nsize);
  119. if (naddr != 3 || nsize != 2)
  120. goto err;
  121. parent_node = get_parent(node);
  122. if (!parent_node)
  123. goto err;
  124. dt_get_reg_format(parent_node, &naddr, &nsize);
  125. if (naddr != 1 || nsize != 1)
  126. goto unhandled;
  127. len = getprop(node, "ranges", pci_ranges_buf,
  128. sizeof(pci_ranges_buf));
  129. for (i = 0; i < len / sizeof(struct pci_range); i++) {
  130. u32 flags = pci_ranges_buf[i].flags & 0x43000000;
  131. if (flags == 0x42000000)
  132. mem = &pci_ranges_buf[i];
  133. else if (flags == 0x02000000)
  134. mmio = &pci_ranges_buf[i];
  135. else if (flags == 0x01000000)
  136. io = &pci_ranges_buf[i];
  137. }
  138. if (!mem || !mmio || !io)
  139. goto unhandled;
  140. if (mem->size[1] != mmio->size[1])
  141. goto unhandled;
  142. if (mem->size[1] & (mem->size[1] - 1))
  143. goto unhandled;
  144. if (io->size[1] & (io->size[1] - 1))
  145. goto unhandled;
  146. if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
  147. mem_base = mem;
  148. else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
  149. mem_base = mmio;
  150. else
  151. goto unhandled;
  152. out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
  153. out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
  154. out_be32(&pci_regs[1][1], io->phys_addr | 1);
  155. out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
  156. out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
  157. out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
  158. out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
  159. out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
  160. out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
  161. out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
  162. out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
  163. out_le32(&pci_regs[0][14], io->phys_addr >> 12);
  164. out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
  165. /* Inbound translation */
  166. out_le32(&pci_regs[0][58], 0);
  167. out_le32(&pci_regs[0][60], 0);
  168. mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
  169. mem_mask = ~(mem_pow2 - 1) >> 12;
  170. out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
  171. /* If PCI is disabled, drive RST high to enable. */
  172. if (!(in_le32(&pci_regs[0][32]) & 1)) {
  173. /* Tpvrh (Power valid to RST# high) 100 ms */
  174. udelay(100000);
  175. out_le32(&pci_regs[0][32], 1);
  176. /* Trhfa (RST# high to first cfg access) 2^25 clocks */
  177. udelay(1020000);
  178. }
  179. /* Enable bus master and memory access */
  180. out_le32(&pci_regs[0][64], 0x80000004);
  181. out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
  182. /* Park the bus on PCI, and elevate PCI's arbitration priority,
  183. * as required by section 9.6 of the user's manual.
  184. */
  185. out_8(&soc_regs[0x10028], 3);
  186. out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
  187. return;
  188. err:
  189. printf("Bad PCI node -- using existing firmware setup.\r\n");
  190. return;
  191. unhandled:
  192. printf("Unsupported PCI node -- using existing firmware setup.\r\n");
  193. }
  194. static void pq2_platform_fixups(void)
  195. {
  196. void *node;
  197. dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
  198. dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
  199. dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
  200. node = finddevice("/soc/cpm");
  201. if (node)
  202. setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
  203. node = finddevice("/soc/cpm/brg");
  204. if (node)
  205. setprop(node, "clock-frequency", &bd.bi_brgfreq, 4);
  206. update_cs_ranges();
  207. fixup_pci();
  208. }
  209. void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  210. unsigned long r6, unsigned long r7)
  211. {
  212. CUBOOT_INIT();
  213. fdt_init(_dtb_start);
  214. serial_console_init();
  215. platform_ops.fixups = pq2_platform_fixups;
  216. }