cuboot-acadia.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Old U-boot compatibility for Acadia
  4. *
  5. * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
  6. *
  7. * Copyright 2008 IBM Corporation
  8. */
  9. #include "ops.h"
  10. #include "io.h"
  11. #include "dcr.h"
  12. #include "stdio.h"
  13. #include "4xx.h"
  14. #include "44x.h"
  15. #include "cuboot.h"
  16. #define TARGET_4xx
  17. #include "ppcboot.h"
  18. static bd_t bd;
  19. #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
  20. #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
  21. #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
  22. #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
  23. #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
  24. #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
  25. #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
  26. #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
  27. #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
  28. #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
  29. #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
  30. #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
  31. #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
  32. static void get_clocks(void)
  33. {
  34. unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
  35. unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
  36. unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
  37. unsigned long div; /* total divisor udiv * bdiv */
  38. unsigned long umin; /* minimum udiv */
  39. unsigned short diff; /* smallest diff */
  40. unsigned long udiv; /* best udiv */
  41. unsigned short idiff; /* current diff */
  42. unsigned short ibdiv; /* current bdiv */
  43. unsigned long est; /* current estimate */
  44. unsigned long baud;
  45. void *np;
  46. /* read the sysclk value from the CPLD */
  47. sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
  48. /*
  49. * Read PLL Mode registers
  50. */
  51. cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
  52. cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
  53. /*
  54. * Determine forward divider A
  55. */
  56. pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
  57. /*
  58. * Determine forward divider B
  59. */
  60. pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
  61. if (pllFwdDivB == 0)
  62. pllFwdDivB = 8;
  63. /*
  64. * Determine FBK_DIV.
  65. */
  66. pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
  67. if (pllFbkDiv == 0)
  68. pllFbkDiv = 256;
  69. /*
  70. * Read CPR_PRIMAD register
  71. */
  72. cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
  73. /*
  74. * Determine PLB_DIV.
  75. */
  76. pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
  77. if (pllPlbDiv == 0)
  78. pllPlbDiv = 16;
  79. /*
  80. * Determine EXTBUS_DIV.
  81. */
  82. pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
  83. if (pllExtBusDiv == 0)
  84. pllExtBusDiv = 16;
  85. /*
  86. * Determine OPB_DIV.
  87. */
  88. pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
  89. if (pllOpbDiv == 0)
  90. pllOpbDiv = 16;
  91. /* There is a bug in U-Boot that prevents us from using
  92. * bd.bi_opbfreq because U-Boot doesn't populate it for
  93. * 405EZ. We get to calculate it, yay!
  94. */
  95. freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
  96. freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
  97. plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
  98. pllFwdDivB : pllFwdDiv) *
  99. pllFbkDiv) / pllFwdDivB);
  100. np = find_node_by_alias("serial0");
  101. if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
  102. fatal("no current-speed property\n\r");
  103. udiv = 256; /* Assume lowest possible serial clk */
  104. div = plloutb / (16 * baud); /* total divisor */
  105. umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */
  106. diff = 256; /* highest possible */
  107. /* i is the test udiv value -- start with the largest
  108. * possible (256) to minimize serial clock and constrain
  109. * search to umin.
  110. */
  111. for (i = 256; i > umin; i--) {
  112. ibdiv = div / i;
  113. est = i * ibdiv;
  114. idiff = (est > div) ? (est-div) : (div-est);
  115. if (idiff == 0) {
  116. udiv = i;
  117. break; /* can't do better */
  118. } else if (idiff < diff) {
  119. udiv = i; /* best so far */
  120. diff = idiff; /* update lowest diff*/
  121. }
  122. }
  123. freqUART = plloutb / udiv;
  124. dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
  125. dt_fixup_clock("/plb/ebc", freqEBC);
  126. dt_fixup_clock("/plb/opb", freqOPB);
  127. dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
  128. dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
  129. }
  130. static void acadia_fixups(void)
  131. {
  132. dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
  133. get_clocks();
  134. dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
  135. }
  136. void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  137. unsigned long r6, unsigned long r7)
  138. {
  139. CUBOOT_INIT();
  140. platform_ops.fixups = acadia_fixups;
  141. platform_ops.exit = ibm40x_dbcr_reset;
  142. fdt_init(_dtb_start);
  143. serial_console_init();
  144. }