4xx.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2007 David Gibson, IBM Corporation.
  4. *
  5. * Based on earlier code:
  6. * Matt Porter <mporter@kernel.crashing.org>
  7. * Copyright 2002-2005 MontaVista Software Inc.
  8. *
  9. * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10. * Copyright (c) 2003, 2004 Zultys Technologies
  11. *
  12. * Copyright (C) 2009 Wind River Systems, Inc.
  13. * Updated for supporting PPC405EX on Kilauea.
  14. * Tiejun Chen <tiejun.chen@windriver.com>
  15. */
  16. #include <stddef.h>
  17. #include "types.h"
  18. #include "string.h"
  19. #include "stdio.h"
  20. #include "ops.h"
  21. #include "reg.h"
  22. #include "dcr.h"
  23. static unsigned long chip_11_errata(unsigned long memsize)
  24. {
  25. unsigned long pvr;
  26. pvr = mfpvr();
  27. switch (pvr & 0xf0000ff0) {
  28. case 0x40000850:
  29. case 0x400008d0:
  30. case 0x200008d0:
  31. memsize -= 4096;
  32. break;
  33. default:
  34. break;
  35. }
  36. return memsize;
  37. }
  38. /* Read the 4xx SDRAM controller to get size of system memory. */
  39. void ibm4xx_sdram_fixup_memsize(void)
  40. {
  41. int i;
  42. unsigned long memsize, bank_config;
  43. memsize = 0;
  44. for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
  45. bank_config = SDRAM0_READ(sdram_bxcr[i]);
  46. if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
  47. memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
  48. }
  49. memsize = chip_11_errata(memsize);
  50. dt_fixup_memory(0, memsize);
  51. }
  52. /* Read the 440SPe MQ controller to get size of system memory. */
  53. #define DCRN_MQ0_B0BAS 0x40
  54. #define DCRN_MQ0_B1BAS 0x41
  55. #define DCRN_MQ0_B2BAS 0x42
  56. #define DCRN_MQ0_B3BAS 0x43
  57. static u64 ibm440spe_decode_bas(u32 bas)
  58. {
  59. u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
  60. /* open coded because I'm paranoid about invalid values */
  61. switch ((bas >> 4) & 0xFFF) {
  62. case 0:
  63. return 0;
  64. case 0xffc:
  65. return base + 0x000800000ull;
  66. case 0xff8:
  67. return base + 0x001000000ull;
  68. case 0xff0:
  69. return base + 0x002000000ull;
  70. case 0xfe0:
  71. return base + 0x004000000ull;
  72. case 0xfc0:
  73. return base + 0x008000000ull;
  74. case 0xf80:
  75. return base + 0x010000000ull;
  76. case 0xf00:
  77. return base + 0x020000000ull;
  78. case 0xe00:
  79. return base + 0x040000000ull;
  80. case 0xc00:
  81. return base + 0x080000000ull;
  82. case 0x800:
  83. return base + 0x100000000ull;
  84. }
  85. printf("Memory BAS value 0x%08x unsupported !\n", bas);
  86. return 0;
  87. }
  88. void ibm440spe_fixup_memsize(void)
  89. {
  90. u64 banktop, memsize = 0;
  91. /* Ultimately, we should directly construct the memory node
  92. * so we are able to handle holes in the memory address space
  93. */
  94. banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
  95. if (banktop > memsize)
  96. memsize = banktop;
  97. banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
  98. if (banktop > memsize)
  99. memsize = banktop;
  100. banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
  101. if (banktop > memsize)
  102. memsize = banktop;
  103. banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
  104. if (banktop > memsize)
  105. memsize = banktop;
  106. dt_fixup_memory(0, memsize);
  107. }
  108. /* 4xx DDR1/2 Denali memory controller support */
  109. /* DDR0 registers */
  110. #define DDR0_02 2
  111. #define DDR0_08 8
  112. #define DDR0_10 10
  113. #define DDR0_14 14
  114. #define DDR0_42 42
  115. #define DDR0_43 43
  116. /* DDR0_02 */
  117. #define DDR_START 0x1
  118. #define DDR_START_SHIFT 0
  119. #define DDR_MAX_CS_REG 0x3
  120. #define DDR_MAX_CS_REG_SHIFT 24
  121. #define DDR_MAX_COL_REG 0xf
  122. #define DDR_MAX_COL_REG_SHIFT 16
  123. #define DDR_MAX_ROW_REG 0xf
  124. #define DDR_MAX_ROW_REG_SHIFT 8
  125. /* DDR0_08 */
  126. #define DDR_DDR2_MODE 0x1
  127. #define DDR_DDR2_MODE_SHIFT 0
  128. /* DDR0_10 */
  129. #define DDR_CS_MAP 0x3
  130. #define DDR_CS_MAP_SHIFT 8
  131. /* DDR0_14 */
  132. #define DDR_REDUC 0x1
  133. #define DDR_REDUC_SHIFT 16
  134. /* DDR0_42 */
  135. #define DDR_APIN 0x7
  136. #define DDR_APIN_SHIFT 24
  137. /* DDR0_43 */
  138. #define DDR_COL_SZ 0x7
  139. #define DDR_COL_SZ_SHIFT 8
  140. #define DDR_BANK8 0x1
  141. #define DDR_BANK8_SHIFT 0
  142. #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
  143. /*
  144. * Some U-Boot versions set the number of chipselects to two
  145. * for Sequoia/Rainier boards while they only have one chipselect
  146. * hardwired. Hardcode the number of chipselects to one
  147. * for sequioa/rainer board models or read the actual value
  148. * from the memory controller register DDR0_10 otherwise.
  149. */
  150. static inline u32 ibm4xx_denali_get_cs(void)
  151. {
  152. void *devp;
  153. char model[64];
  154. u32 val, cs;
  155. devp = finddevice("/");
  156. if (!devp)
  157. goto read_cs;
  158. if (getprop(devp, "model", model, sizeof(model)) <= 0)
  159. goto read_cs;
  160. model[sizeof(model)-1] = 0;
  161. if (!strcmp(model, "amcc,sequoia") ||
  162. !strcmp(model, "amcc,rainier"))
  163. return 1;
  164. read_cs:
  165. /* get CS value */
  166. val = SDRAM0_READ(DDR0_10);
  167. val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
  168. cs = 0;
  169. while (val) {
  170. if (val & 0x1)
  171. cs++;
  172. val = val >> 1;
  173. }
  174. return cs;
  175. }
  176. void ibm4xx_denali_fixup_memsize(void)
  177. {
  178. u32 val, max_cs, max_col, max_row;
  179. u32 cs, col, row, bank, dpath;
  180. unsigned long memsize;
  181. val = SDRAM0_READ(DDR0_02);
  182. if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
  183. fatal("DDR controller is not initialized\n");
  184. /* get maximum cs col and row values */
  185. max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
  186. max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
  187. max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
  188. cs = ibm4xx_denali_get_cs();
  189. if (!cs)
  190. fatal("No memory installed\n");
  191. if (cs > max_cs)
  192. fatal("DDR wrong CS configuration\n");
  193. /* get data path bytes */
  194. val = SDRAM0_READ(DDR0_14);
  195. if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
  196. dpath = 4; /* 32 bits */
  197. else
  198. dpath = 8; /* 64 bits */
  199. /* get address pins (rows) */
  200. val = SDRAM0_READ(DDR0_42);
  201. row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
  202. if (row > max_row)
  203. fatal("DDR wrong APIN configuration\n");
  204. row = max_row - row;
  205. /* get collomn size and banks */
  206. val = SDRAM0_READ(DDR0_43);
  207. col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
  208. if (col > max_col)
  209. fatal("DDR wrong COL configuration\n");
  210. col = max_col - col;
  211. if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
  212. bank = 8; /* 8 banks */
  213. else
  214. bank = 4; /* 4 banks */
  215. memsize = cs * (1 << (col+row)) * bank * dpath;
  216. memsize = chip_11_errata(memsize);
  217. dt_fixup_memory(0, memsize);
  218. }
  219. #define SPRN_DBCR0_40X 0x3F2
  220. #define SPRN_DBCR0_44X 0x134
  221. #define DBCR0_RST_SYSTEM 0x30000000
  222. void ibm44x_dbcr_reset(void)
  223. {
  224. unsigned long tmp;
  225. asm volatile (
  226. "mfspr %0,%1\n"
  227. "oris %0,%0,%2@h\n"
  228. "mtspr %1,%0"
  229. : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
  230. );
  231. }
  232. void ibm40x_dbcr_reset(void)
  233. {
  234. unsigned long tmp;
  235. asm volatile (
  236. "mfspr %0,%1\n"
  237. "oris %0,%0,%2@h\n"
  238. "mtspr %1,%0"
  239. : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
  240. );
  241. }
  242. #define EMAC_RESET 0x20000000
  243. void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
  244. {
  245. /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
  246. * do this for us
  247. */
  248. if (emac0)
  249. *emac0 = EMAC_RESET;
  250. if (emac1)
  251. *emac1 = EMAC_RESET;
  252. mtdcr(DCRN_MAL0_CFG, MAL_RESET);
  253. while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
  254. ; /* loop until reset takes effect */
  255. }
  256. /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
  257. * banks into the OPB address space */
  258. void ibm4xx_fixup_ebc_ranges(const char *ebc)
  259. {
  260. void *devp;
  261. u32 bxcr;
  262. u32 ranges[EBC_NUM_BANKS*4];
  263. u32 *p = ranges;
  264. int i;
  265. for (i = 0; i < EBC_NUM_BANKS; i++) {
  266. mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
  267. bxcr = mfdcr(DCRN_EBC0_CFGDATA);
  268. if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
  269. *p++ = i;
  270. *p++ = 0;
  271. *p++ = bxcr & EBC_BXCR_BAS;
  272. *p++ = EBC_BXCR_BANK_SIZE(bxcr);
  273. }
  274. }
  275. devp = finddevice(ebc);
  276. if (! devp)
  277. fatal("Couldn't locate EBC node %s\n\r", ebc);
  278. setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
  279. }
  280. /* Calculate 440GP clocks */
  281. void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
  282. {
  283. u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
  284. u32 cr0 = mfdcr(DCRN_CPC0_CR0);
  285. u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
  286. u32 opdv = CPC0_SYS0_OPDV(sys0);
  287. u32 epdv = CPC0_SYS0_EPDV(sys0);
  288. if (sys0 & CPC0_SYS0_BYPASS) {
  289. /* Bypass system PLL */
  290. cpu = plb = sys_clk;
  291. } else {
  292. if (sys0 & CPC0_SYS0_EXTSL)
  293. /* PerClk */
  294. m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
  295. else
  296. /* CPU clock */
  297. m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
  298. cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
  299. plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
  300. }
  301. opb = plb / opdv;
  302. ebc = opb / epdv;
  303. /* FIXME: Check if this is for all 440GP, or just Ebony */
  304. if ((mfpvr() & 0xf0000fff) == 0x40000440)
  305. /* Rev. B 440GP, use external system clock */
  306. tb = sys_clk;
  307. else
  308. /* Rev. C 440GP, errata force us to use internal clock */
  309. tb = cpu;
  310. if (cr0 & CPC0_CR0_U0EC)
  311. /* External UART clock */
  312. uart0 = ser_clk;
  313. else
  314. /* Internal UART clock */
  315. uart0 = plb / CPC0_CR0_UDIV(cr0);
  316. if (cr0 & CPC0_CR0_U1EC)
  317. /* External UART clock */
  318. uart1 = ser_clk;
  319. else
  320. /* Internal UART clock */
  321. uart1 = plb / CPC0_CR0_UDIV(cr0);
  322. printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
  323. (sys_clk + 500000) / 1000000, sys_clk);
  324. dt_fixup_cpu_clocks(cpu, tb, 0);
  325. dt_fixup_clock("/plb", plb);
  326. dt_fixup_clock("/plb/opb", opb);
  327. dt_fixup_clock("/plb/opb/ebc", ebc);
  328. dt_fixup_clock("/plb/opb/serial@40000200", uart0);
  329. dt_fixup_clock("/plb/opb/serial@40000300", uart1);
  330. }
  331. #define SPRN_CCR1 0x378
  332. static inline u32 __fix_zero(u32 v, u32 def)
  333. {
  334. return v ? v : def;
  335. }
  336. static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
  337. unsigned int tmr_clk,
  338. int per_clk_from_opb)
  339. {
  340. /* PLL config */
  341. u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
  342. u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
  343. /* Dividers */
  344. u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
  345. u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
  346. u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
  347. u32 lfbdv = __fix_zero(plld & 0x3f, 64);
  348. u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
  349. u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
  350. u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
  351. u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
  352. /* Input clocks for primary dividers */
  353. u32 clk_a, clk_b;
  354. /* Resulting clocks */
  355. u32 cpu, plb, opb, ebc, vco;
  356. /* Timebase */
  357. u32 ccr1, tb = tmr_clk;
  358. if (pllc & 0x40000000) {
  359. u32 m;
  360. /* Feedback path */
  361. switch ((pllc >> 24) & 7) {
  362. case 0:
  363. /* PLLOUTx */
  364. m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
  365. break;
  366. case 1:
  367. /* CPU */
  368. m = fwdva * pradv0;
  369. break;
  370. case 5:
  371. /* PERClk */
  372. m = fwdvb * prbdv0 * opbdv0 * perdv0;
  373. break;
  374. default:
  375. printf("WARNING ! Invalid PLL feedback source !\n");
  376. goto bypass;
  377. }
  378. m *= fbdv;
  379. vco = sys_clk * m;
  380. clk_a = vco / fwdva;
  381. clk_b = vco / fwdvb;
  382. } else {
  383. bypass:
  384. /* Bypass system PLL */
  385. vco = 0;
  386. clk_a = clk_b = sys_clk;
  387. }
  388. cpu = clk_a / pradv0;
  389. plb = clk_b / prbdv0;
  390. opb = plb / opbdv0;
  391. ebc = (per_clk_from_opb ? opb : plb) / perdv0;
  392. /* Figure out timebase. Either CPU or default TmrClk */
  393. ccr1 = mfspr(SPRN_CCR1);
  394. /* If passed a 0 tmr_clk, force CPU clock */
  395. if (tb == 0) {
  396. ccr1 &= ~0x80u;
  397. mtspr(SPRN_CCR1, ccr1);
  398. }
  399. if ((ccr1 & 0x0080) == 0)
  400. tb = cpu;
  401. dt_fixup_cpu_clocks(cpu, tb, 0);
  402. dt_fixup_clock("/plb", plb);
  403. dt_fixup_clock("/plb/opb", opb);
  404. dt_fixup_clock("/plb/opb/ebc", ebc);
  405. return plb;
  406. }
  407. static void eplike_fixup_uart_clk(int index, const char *path,
  408. unsigned int ser_clk,
  409. unsigned int plb_clk)
  410. {
  411. unsigned int sdr;
  412. unsigned int clock;
  413. switch (index) {
  414. case 0:
  415. sdr = SDR0_READ(DCRN_SDR0_UART0);
  416. break;
  417. case 1:
  418. sdr = SDR0_READ(DCRN_SDR0_UART1);
  419. break;
  420. case 2:
  421. sdr = SDR0_READ(DCRN_SDR0_UART2);
  422. break;
  423. case 3:
  424. sdr = SDR0_READ(DCRN_SDR0_UART3);
  425. break;
  426. default:
  427. return;
  428. }
  429. if (sdr & 0x00800000u)
  430. clock = ser_clk;
  431. else
  432. clock = plb_clk / __fix_zero(sdr & 0xff, 256);
  433. dt_fixup_clock(path, clock);
  434. }
  435. void ibm440ep_fixup_clocks(unsigned int sys_clk,
  436. unsigned int ser_clk,
  437. unsigned int tmr_clk)
  438. {
  439. unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
  440. /* serial clocks need fixup based on int/ext */
  441. eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
  442. eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
  443. eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
  444. eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
  445. }
  446. void ibm440gx_fixup_clocks(unsigned int sys_clk,
  447. unsigned int ser_clk,
  448. unsigned int tmr_clk)
  449. {
  450. unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
  451. /* serial clocks need fixup based on int/ext */
  452. eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
  453. eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
  454. }
  455. void ibm440spe_fixup_clocks(unsigned int sys_clk,
  456. unsigned int ser_clk,
  457. unsigned int tmr_clk)
  458. {
  459. unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
  460. /* serial clocks need fixup based on int/ext */
  461. eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
  462. eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
  463. eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
  464. }
  465. void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
  466. {
  467. u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
  468. u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
  469. u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
  470. u32 psr = mfdcr(DCRN_405_CPC0_PSR);
  471. u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
  472. u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
  473. fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
  474. fbdv = (pllmr & 0x1e000000) >> 25;
  475. if (fbdv == 0)
  476. fbdv = 16;
  477. cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
  478. opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
  479. ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */
  480. epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
  481. udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
  482. /* check for 405GPr */
  483. if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
  484. fwdvb = 8 - (pllmr & 0x00000007);
  485. if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
  486. if (psr & 0x00000020) /* New mode enable */
  487. m = fwdvb * 2 * ppdv;
  488. else
  489. m = fwdvb * cbdv * ppdv;
  490. else if (psr & 0x00000020) /* New mode enable */
  491. if (psr & 0x00000800) /* PerClk synch mode */
  492. m = fwdvb * 2 * epdv;
  493. else
  494. m = fbdv * fwdv;
  495. else if (epdv == fbdv)
  496. m = fbdv * cbdv * epdv;
  497. else
  498. m = fbdv * fwdvb * cbdv;
  499. cpu = sys_clk * m / fwdv;
  500. plb = sys_clk * m / (fwdvb * cbdv);
  501. } else {
  502. m = fwdv * fbdv * cbdv;
  503. cpu = sys_clk * m / fwdv;
  504. plb = cpu / cbdv;
  505. }
  506. opb = plb / opdv;
  507. ebc = plb / epdv;
  508. if (cpc0_cr0 & 0x80)
  509. /* uart0 uses the external clock */
  510. uart0 = ser_clk;
  511. else
  512. uart0 = cpu / udiv;
  513. if (cpc0_cr0 & 0x40)
  514. /* uart1 uses the external clock */
  515. uart1 = ser_clk;
  516. else
  517. uart1 = cpu / udiv;
  518. /* setup the timebase clock to tick at the cpu frequency */
  519. cpc0_cr1 = cpc0_cr1 & ~0x00800000;
  520. mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
  521. tb = cpu;
  522. dt_fixup_cpu_clocks(cpu, tb, 0);
  523. dt_fixup_clock("/plb", plb);
  524. dt_fixup_clock("/plb/opb", opb);
  525. dt_fixup_clock("/plb/ebc", ebc);
  526. dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
  527. dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
  528. }
  529. void ibm405ep_fixup_clocks(unsigned int sys_clk)
  530. {
  531. u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
  532. u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
  533. u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
  534. u32 cpu, plb, opb, ebc, uart0, uart1;
  535. u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
  536. u32 pllmr0_ccdv, tb, m;
  537. fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
  538. fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
  539. fbdv = (pllmr1 & 0x00f00000) >> 20;
  540. if (fbdv == 0)
  541. fbdv = 16;
  542. cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
  543. epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
  544. opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
  545. m = fbdv * fwdvb;
  546. pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
  547. if (pllmr1 & 0x80000000)
  548. cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
  549. else
  550. cpu = sys_clk / pllmr0_ccdv;
  551. plb = cpu / cbdv;
  552. opb = plb / opdv;
  553. ebc = plb / epdv;
  554. tb = cpu;
  555. uart0 = cpu / (cpc0_ucr & 0x0000007f);
  556. uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
  557. dt_fixup_cpu_clocks(cpu, tb, 0);
  558. dt_fixup_clock("/plb", plb);
  559. dt_fixup_clock("/plb/opb", opb);
  560. dt_fixup_clock("/plb/ebc", ebc);
  561. dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
  562. dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
  563. }
  564. static u8 ibm405ex_fwdv_multi_bits[] = {
  565. /* values for: 1 - 16 */
  566. 0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
  567. 0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
  568. };
  569. u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
  570. {
  571. u32 index;
  572. for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
  573. if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
  574. return index + 1;
  575. return 0;
  576. }
  577. static u8 ibm405ex_fbdv_multi_bits[] = {
  578. /* values for: 1 - 100 */
  579. 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
  580. 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
  581. 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
  582. 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
  583. 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
  584. 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
  585. 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
  586. 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
  587. 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
  588. 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
  589. /* values for: 101 - 200 */
  590. 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
  591. 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
  592. 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
  593. 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
  594. 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
  595. 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
  596. 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
  597. 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
  598. 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
  599. 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
  600. /* values for: 201 - 255 */
  601. 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
  602. 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
  603. 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
  604. 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
  605. 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
  606. 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
  607. };
  608. u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
  609. {
  610. u32 index;
  611. for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
  612. if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
  613. return index + 1;
  614. return 0;
  615. }
  616. void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
  617. {
  618. /* PLL config */
  619. u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
  620. u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
  621. u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
  622. u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
  623. u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
  624. u32 perd = CPR0_READ(DCRN_CPR0_PERD);
  625. /* Dividers */
  626. u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
  627. u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
  628. u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
  629. /* PLBDV0 is hardwared to 010. */
  630. u32 plbdv0 = 2;
  631. u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
  632. u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
  633. u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
  634. /* Resulting clocks */
  635. u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
  636. /* PLL's VCO is the source for primary forward ? */
  637. if (pllc & 0x40000000) {
  638. u32 m;
  639. /* Feedback path */
  640. switch ((pllc >> 24) & 7) {
  641. case 0:
  642. /* PLLOUTx */
  643. m = fbdv;
  644. break;
  645. case 1:
  646. /* CPU */
  647. m = fbdv * fwdva * cpudv0;
  648. break;
  649. case 5:
  650. /* PERClk */
  651. m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
  652. break;
  653. default:
  654. printf("WARNING ! Invalid PLL feedback source !\n");
  655. goto bypass;
  656. }
  657. vco = (unsigned int)(sys_clk * m);
  658. } else {
  659. bypass:
  660. /* Bypass system PLL */
  661. vco = 0;
  662. }
  663. /* CPU = VCO / ( FWDVA x CPUDV0) */
  664. cpu = vco / (fwdva * cpudv0);
  665. /* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
  666. plb = vco / (fwdva * plb2xdv0 * plbdv0);
  667. /* OPB = PLB / OPBDV0 */
  668. opb = plb / opbdv0;
  669. /* EBC = OPB / PERDV0 */
  670. ebc = opb / perdv0;
  671. tb = cpu;
  672. uart0 = uart1 = uart_clk;
  673. dt_fixup_cpu_clocks(cpu, tb, 0);
  674. dt_fixup_clock("/plb", plb);
  675. dt_fixup_clock("/plb/opb", opb);
  676. dt_fixup_clock("/plb/opb/ebc", ebc);
  677. dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
  678. dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
  679. }