decode_exc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Linux/PA-RISC Project (http://www.parisc-linux.org/)
  4. *
  5. * Floating-point emulation code
  6. * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
  7. */
  8. /*
  9. * BEGIN_DESC
  10. *
  11. * File:
  12. * @(#) pa/fp/decode_exc.c $ Revision: $
  13. *
  14. * Purpose:
  15. * <<please update with a synopsis of the functionality provided by this file>>
  16. *
  17. * External Interfaces:
  18. * <<the following list was autogenerated, please review>>
  19. * decode_fpu(Fpu_register, trap_counts)
  20. *
  21. * Internal Interfaces:
  22. * <<please update>>
  23. *
  24. * Theory:
  25. * <<please update with a overview of the operation of this file>>
  26. *
  27. * END_DESC
  28. */
  29. #include <linux/kernel.h>
  30. #include "float.h"
  31. #include "sgl_float.h"
  32. #include "dbl_float.h"
  33. #include "cnv_float.h"
  34. /* #include "types.h" */
  35. #include <asm/signal.h>
  36. #include <asm/siginfo.h>
  37. /* #include <machine/sys/mdep_private.h> */
  38. #undef Fpustatus_register
  39. #define Fpustatus_register Fpu_register[0]
  40. /* General definitions */
  41. #define DOESTRAP 1
  42. #define NOTRAP 0
  43. #define SIGNALCODE(signal, code) ((signal) << 24 | (code))
  44. #define copropbit 1<<31-2 /* bit position 2 */
  45. #define opclass 9 /* bits 21 & 22 */
  46. #define fmt 11 /* bits 19 & 20 */
  47. #define df 13 /* bits 17 & 18 */
  48. #define twobits 3 /* mask low-order 2 bits */
  49. #define fivebits 31 /* mask low-order 5 bits */
  50. #define MAX_EXCP_REG 7 /* number of excpeption registers to check */
  51. /* Exception register definitions */
  52. #define Excp_type(index) Exceptiontype(Fpu_register[index])
  53. #define Excp_instr(index) Instructionfield(Fpu_register[index])
  54. #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
  55. #define Excp_format() \
  56. (current_ir >> ((current_ir>>opclass & twobits)==1 ? df : fmt) & twobits)
  57. /* Miscellaneous definitions */
  58. #define Fpu_sgl(index) Fpu_register[index*2]
  59. #define Fpu_dblp1(index) Fpu_register[index*2]
  60. #define Fpu_dblp2(index) Fpu_register[(index*2)+1]
  61. #define Fpu_quadp1(index) Fpu_register[index*2]
  62. #define Fpu_quadp2(index) Fpu_register[(index*2)+1]
  63. #define Fpu_quadp3(index) Fpu_register[(index*2)+2]
  64. #define Fpu_quadp4(index) Fpu_register[(index*2)+3]
  65. /* Single precision floating-point definitions */
  66. #ifndef Sgl_decrement
  67. # define Sgl_decrement(sgl_value) Sall(sgl_value)--
  68. #endif
  69. /* Double precision floating-point definitions */
  70. #ifndef Dbl_decrement
  71. # define Dbl_decrement(dbl_valuep1,dbl_valuep2) \
  72. if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
  73. #endif
  74. #define update_trap_counts(Fpu_register, aflags, bflags, trap_counts) { \
  75. aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
  76. Fpu_register[0] |= bflags; \
  77. }
  78. u_int
  79. decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[])
  80. {
  81. unsigned int current_ir, excp;
  82. int target, exception_index = 1;
  83. boolean inexact;
  84. unsigned int aflags;
  85. unsigned int bflags;
  86. unsigned int excptype;
  87. /* Keep stats on how many floating point exceptions (based on type)
  88. * that happen. Want to keep this overhead low, but still provide
  89. * some information to the customer. All exits from this routine
  90. * need to restore Fpu_register[0]
  91. */
  92. bflags=(Fpu_register[0] & 0xf8000000);
  93. Fpu_register[0] &= 0x07ffffff;
  94. /* exception_index is used to index the exception register queue. It
  95. * always points at the last register that contains a valid exception. A
  96. * zero value implies no exceptions (also the initialized value). Setting
  97. * the T-bit resets the exception_index to zero.
  98. */
  99. /*
  100. * Check for reserved-op exception. A reserved-op exception does not
  101. * set any exception registers nor does it set the T-bit. If the T-bit
  102. * is not set then a reserved-op exception occurred.
  103. *
  104. * At some point, we may want to report reserved op exceptions as
  105. * illegal instructions.
  106. */
  107. if (!Is_tbit_set()) {
  108. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  109. return SIGNALCODE(SIGILL, ILL_COPROC);
  110. }
  111. /*
  112. * Is a coprocessor op.
  113. *
  114. * Now we need to determine what type of exception occurred.
  115. */
  116. for (exception_index=1; exception_index<=MAX_EXCP_REG; exception_index++) {
  117. current_ir = Excp_instr(exception_index);
  118. /*
  119. * On PA89: there are 5 different unimplemented exception
  120. * codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds
  121. * another, 0x2b. Only these have the low order bit set.
  122. */
  123. excptype = Excp_type(exception_index);
  124. if (excptype & UNIMPLEMENTEDEXCEPTION) {
  125. /*
  126. * Clear T-bit and exception register so that
  127. * we can tell if a trap really occurs while
  128. * emulating the instruction.
  129. */
  130. Clear_tbit();
  131. Clear_excp_register(exception_index);
  132. /*
  133. * Now emulate this instruction. If a trap occurs,
  134. * fpudispatch will return a non-zero number
  135. */
  136. excp = fpudispatch(current_ir,excptype,0,Fpu_register);
  137. /* accumulate the status flags, don't lose them as in hpux */
  138. if (excp) {
  139. /*
  140. * We now need to make sure that the T-bit and the
  141. * exception register contain the correct values
  142. * before continuing.
  143. */
  144. /*
  145. * Set t-bit since it might still be needed for a
  146. * subsequent real trap (I don't understand fully -PB)
  147. */
  148. Set_tbit();
  149. /* some of the following code uses
  150. * Excp_type(exception_index) so fix that up */
  151. Set_exceptiontype_and_instr_field(excp,current_ir,
  152. Fpu_register[exception_index]);
  153. if (excp == UNIMPLEMENTEDEXCEPTION) {
  154. /*
  155. * it is really unimplemented, so restore the
  156. * TIMEX extended unimplemented exception code
  157. */
  158. excp = excptype;
  159. update_trap_counts(Fpu_register, aflags, bflags,
  160. trap_counts);
  161. return SIGNALCODE(SIGILL, ILL_COPROC);
  162. }
  163. /* some of the following code uses excptype, so
  164. * fix that up too */
  165. excptype = excp;
  166. }
  167. /* handle exceptions other than the real UNIMPLIMENTED the
  168. * same way as if the hardware had caused them */
  169. if (excp == NOEXCEPTION)
  170. /* For now use 'break', should technically be 'continue' */
  171. break;
  172. }
  173. /*
  174. * In PA89, the underflow exception has been extended to encode
  175. * additional information. The exception looks like pp01x0,
  176. * where x is 1 if inexact and pp represent the inexact bit (I)
  177. * and the round away bit (RA)
  178. */
  179. if (excptype & UNDERFLOWEXCEPTION) {
  180. /* check for underflow trap enabled */
  181. if (Is_underflowtrap_enabled()) {
  182. update_trap_counts(Fpu_register, aflags, bflags,
  183. trap_counts);
  184. return SIGNALCODE(SIGFPE, FPE_FLTUND);
  185. } else {
  186. /*
  187. * Isn't a real trap; we need to
  188. * return the default value.
  189. */
  190. target = current_ir & fivebits;
  191. #ifndef lint
  192. if (Ibit(Fpu_register[exception_index])) inexact = TRUE;
  193. else inexact = FALSE;
  194. #endif
  195. switch (Excp_format()) {
  196. case SGL:
  197. /*
  198. * If ra (round-away) is set, will
  199. * want to undo the rounding done
  200. * by the hardware.
  201. */
  202. if (Rabit(Fpu_register[exception_index]))
  203. Sgl_decrement(Fpu_sgl(target));
  204. /* now denormalize */
  205. sgl_denormalize(&Fpu_sgl(target),&inexact,Rounding_mode());
  206. break;
  207. case DBL:
  208. /*
  209. * If ra (round-away) is set, will
  210. * want to undo the rounding done
  211. * by the hardware.
  212. */
  213. if (Rabit(Fpu_register[exception_index]))
  214. Dbl_decrement(Fpu_dblp1(target),Fpu_dblp2(target));
  215. /* now denormalize */
  216. dbl_denormalize(&Fpu_dblp1(target),&Fpu_dblp2(target),
  217. &inexact,Rounding_mode());
  218. break;
  219. }
  220. if (inexact) Set_underflowflag();
  221. /*
  222. * Underflow can generate an inexact
  223. * exception. If inexact trap is enabled,
  224. * want to do an inexact trap, otherwise
  225. * set inexact flag.
  226. */
  227. if (inexact && Is_inexacttrap_enabled()) {
  228. /*
  229. * Set exception field of exception register
  230. * to inexact, parm field to zero.
  231. * Underflow bit should be cleared.
  232. */
  233. Set_exceptiontype(Fpu_register[exception_index],
  234. INEXACTEXCEPTION);
  235. Set_parmfield(Fpu_register[exception_index],0);
  236. update_trap_counts(Fpu_register, aflags, bflags,
  237. trap_counts);
  238. return SIGNALCODE(SIGFPE, FPE_FLTRES);
  239. }
  240. else {
  241. /*
  242. * Exception register needs to be cleared.
  243. * Inexact flag needs to be set if inexact.
  244. */
  245. Clear_excp_register(exception_index);
  246. if (inexact) Set_inexactflag();
  247. }
  248. }
  249. continue;
  250. }
  251. switch(Excp_type(exception_index)) {
  252. case OVERFLOWEXCEPTION:
  253. case OVERFLOWEXCEPTION | INEXACTEXCEPTION:
  254. /* check for overflow trap enabled */
  255. update_trap_counts(Fpu_register, aflags, bflags,
  256. trap_counts);
  257. if (Is_overflowtrap_enabled()) {
  258. update_trap_counts(Fpu_register, aflags, bflags,
  259. trap_counts);
  260. return SIGNALCODE(SIGFPE, FPE_FLTOVF);
  261. } else {
  262. /*
  263. * Isn't a real trap; we need to
  264. * return the default value.
  265. */
  266. target = current_ir & fivebits;
  267. switch (Excp_format()) {
  268. case SGL:
  269. Sgl_setoverflow(Fpu_sgl(target));
  270. break;
  271. case DBL:
  272. Dbl_setoverflow(Fpu_dblp1(target),Fpu_dblp2(target));
  273. break;
  274. }
  275. Set_overflowflag();
  276. /*
  277. * Overflow always generates an inexact
  278. * exception. If inexact trap is enabled,
  279. * want to do an inexact trap, otherwise
  280. * set inexact flag.
  281. */
  282. if (Is_inexacttrap_enabled()) {
  283. /*
  284. * Set exception field of exception
  285. * register to inexact. Overflow
  286. * bit should be cleared.
  287. */
  288. Set_exceptiontype(Fpu_register[exception_index],
  289. INEXACTEXCEPTION);
  290. update_trap_counts(Fpu_register, aflags, bflags,
  291. trap_counts);
  292. return SIGNALCODE(SIGFPE, FPE_FLTRES);
  293. }
  294. else {
  295. /*
  296. * Exception register needs to be cleared.
  297. * Inexact flag needs to be set.
  298. */
  299. Clear_excp_register(exception_index);
  300. Set_inexactflag();
  301. }
  302. }
  303. break;
  304. case INVALIDEXCEPTION:
  305. case OPC_2E_INVALIDEXCEPTION:
  306. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  307. return SIGNALCODE(SIGFPE, FPE_FLTINV);
  308. case DIVISIONBYZEROEXCEPTION:
  309. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  310. Clear_excp_register(exception_index);
  311. return SIGNALCODE(SIGFPE, FPE_FLTDIV);
  312. case INEXACTEXCEPTION:
  313. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  314. return SIGNALCODE(SIGFPE, FPE_FLTRES);
  315. default:
  316. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  317. printk("%s(%d) Unknown FPU exception 0x%x\n", __FILE__,
  318. __LINE__, Excp_type(exception_index));
  319. return SIGNALCODE(SIGILL, ILL_COPROC);
  320. case NOEXCEPTION: /* no exception */
  321. /*
  322. * Clear exception register in case
  323. * other fields are non-zero.
  324. */
  325. Clear_excp_register(exception_index);
  326. break;
  327. }
  328. }
  329. /*
  330. * No real exceptions occurred.
  331. */
  332. Clear_tbit();
  333. update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
  334. return(NOTRAP);
  335. }