unaligned.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Unaligned memory access handler
  4. *
  5. * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
  6. * Significantly tweaked by LaMont Jones <lamont@debian.org>
  7. */
  8. #include <linux/jiffies.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/sched/signal.h>
  12. #include <linux/sched/debug.h>
  13. #include <linux/signal.h>
  14. #include <linux/ratelimit.h>
  15. #include <linux/uaccess.h>
  16. #include <asm/hardirq.h>
  17. #include <asm/traps.h>
  18. /* #define DEBUG_UNALIGNED 1 */
  19. #ifdef DEBUG_UNALIGNED
  20. #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
  21. #else
  22. #define DPRINTF(fmt, args...)
  23. #endif
  24. #ifdef CONFIG_64BIT
  25. #define RFMT "%016lx"
  26. #else
  27. #define RFMT "%08lx"
  28. #endif
  29. #define FIXUP_BRANCH(lbl) \
  30. "\tldil L%%" #lbl ", %%r1\n" \
  31. "\tldo R%%" #lbl "(%%r1), %%r1\n" \
  32. "\tbv,n %%r0(%%r1)\n"
  33. /* If you use FIXUP_BRANCH, then you must list this clobber */
  34. #define FIXUP_BRANCH_CLOBBER "r1"
  35. /* 1111 1100 0000 0000 0001 0011 1100 0000 */
  36. #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
  37. #define OPCODE2(a,b) ((a)<<26|(b)<<1)
  38. #define OPCODE3(a,b) ((a)<<26|(b)<<2)
  39. #define OPCODE4(a) ((a)<<26)
  40. #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
  41. #define OPCODE2_MASK OPCODE2(0x3f,1)
  42. #define OPCODE3_MASK OPCODE3(0x3f,1)
  43. #define OPCODE4_MASK OPCODE4(0x3f)
  44. /* skip LDB - never unaligned (index) */
  45. #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
  46. #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
  47. #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
  48. #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
  49. #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
  50. #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
  51. #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
  52. /* skip LDB - never unaligned (short) */
  53. #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
  54. #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
  55. #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
  56. #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
  57. #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
  58. #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
  59. #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
  60. /* skip STB - never unaligned */
  61. #define OPCODE_STH OPCODE1(0x03,1,0x9)
  62. #define OPCODE_STW OPCODE1(0x03,1,0xa)
  63. #define OPCODE_STD OPCODE1(0x03,1,0xb)
  64. /* skip STBY - never unaligned */
  65. /* skip STDBY - never unaligned */
  66. #define OPCODE_STWA OPCODE1(0x03,1,0xe)
  67. #define OPCODE_STDA OPCODE1(0x03,1,0xf)
  68. #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
  69. #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
  70. #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
  71. #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
  72. #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
  73. #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
  74. #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
  75. #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
  76. #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
  77. #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
  78. #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
  79. #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
  80. #define OPCODE_LDD_L OPCODE2(0x14,0)
  81. #define OPCODE_FLDD_L OPCODE2(0x14,1)
  82. #define OPCODE_STD_L OPCODE2(0x1c,0)
  83. #define OPCODE_FSTD_L OPCODE2(0x1c,1)
  84. #define OPCODE_LDW_M OPCODE3(0x17,1)
  85. #define OPCODE_FLDW_L OPCODE3(0x17,0)
  86. #define OPCODE_FSTW_L OPCODE3(0x1f,0)
  87. #define OPCODE_STW_M OPCODE3(0x1f,1)
  88. #define OPCODE_LDH_L OPCODE4(0x11)
  89. #define OPCODE_LDW_L OPCODE4(0x12)
  90. #define OPCODE_LDWM OPCODE4(0x13)
  91. #define OPCODE_STH_L OPCODE4(0x19)
  92. #define OPCODE_STW_L OPCODE4(0x1A)
  93. #define OPCODE_STWM OPCODE4(0x1B)
  94. #define MAJOR_OP(i) (((i)>>26)&0x3f)
  95. #define R1(i) (((i)>>21)&0x1f)
  96. #define R2(i) (((i)>>16)&0x1f)
  97. #define R3(i) ((i)&0x1f)
  98. #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
  99. #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
  100. #define IM5_2(i) IM((i)>>16,5)
  101. #define IM5_3(i) IM((i),5)
  102. #define IM14(i) IM((i),14)
  103. #define ERR_NOTHANDLED -1
  104. #define ERR_PAGEFAULT -2
  105. int unaligned_enabled __read_mostly = 1;
  106. static int emulate_ldh(struct pt_regs *regs, int toreg)
  107. {
  108. unsigned long saddr = regs->ior;
  109. unsigned long val = 0;
  110. int ret;
  111. DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
  112. regs->isr, regs->ior, toreg);
  113. __asm__ __volatile__ (
  114. " mtsp %4, %%sr1\n"
  115. "1: ldbs 0(%%sr1,%3), %%r20\n"
  116. "2: ldbs 1(%%sr1,%3), %0\n"
  117. " depw %%r20, 23, 24, %0\n"
  118. " copy %%r0, %1\n"
  119. "3: \n"
  120. " .section .fixup,\"ax\"\n"
  121. "4: ldi -2, %1\n"
  122. FIXUP_BRANCH(3b)
  123. " .previous\n"
  124. ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
  125. ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
  126. : "=r" (val), "=r" (ret)
  127. : "0" (val), "r" (saddr), "r" (regs->isr)
  128. : "r20", FIXUP_BRANCH_CLOBBER );
  129. DPRINTF("val = 0x" RFMT "\n", val);
  130. if (toreg)
  131. regs->gr[toreg] = val;
  132. return ret;
  133. }
  134. static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
  135. {
  136. unsigned long saddr = regs->ior;
  137. unsigned long val = 0;
  138. int ret;
  139. DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
  140. regs->isr, regs->ior, toreg);
  141. __asm__ __volatile__ (
  142. " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */
  143. " mtsp %4, %%sr1\n"
  144. " depw %%r0,31,2,%3\n"
  145. "1: ldw 0(%%sr1,%3),%0\n"
  146. "2: ldw 4(%%sr1,%3),%%r20\n"
  147. " subi 32,%%r19,%%r19\n"
  148. " mtctl %%r19,11\n"
  149. " vshd %0,%%r20,%0\n"
  150. " copy %%r0, %1\n"
  151. "3: \n"
  152. " .section .fixup,\"ax\"\n"
  153. "4: ldi -2, %1\n"
  154. FIXUP_BRANCH(3b)
  155. " .previous\n"
  156. ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
  157. ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
  158. : "=r" (val), "=r" (ret)
  159. : "0" (val), "r" (saddr), "r" (regs->isr)
  160. : "r19", "r20", FIXUP_BRANCH_CLOBBER );
  161. DPRINTF("val = 0x" RFMT "\n", val);
  162. if (flop)
  163. ((__u32*)(regs->fr))[toreg] = val;
  164. else if (toreg)
  165. regs->gr[toreg] = val;
  166. return ret;
  167. }
  168. static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
  169. {
  170. unsigned long saddr = regs->ior;
  171. __u64 val = 0;
  172. int ret;
  173. DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
  174. regs->isr, regs->ior, toreg);
  175. #ifdef CONFIG_PA20
  176. #ifndef CONFIG_64BIT
  177. if (!flop)
  178. return -1;
  179. #endif
  180. __asm__ __volatile__ (
  181. " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
  182. " mtsp %4, %%sr1\n"
  183. " depd %%r0,63,3,%3\n"
  184. "1: ldd 0(%%sr1,%3),%0\n"
  185. "2: ldd 8(%%sr1,%3),%%r20\n"
  186. " subi 64,%%r19,%%r19\n"
  187. " mtsar %%r19\n"
  188. " shrpd %0,%%r20,%%sar,%0\n"
  189. " copy %%r0, %1\n"
  190. "3: \n"
  191. " .section .fixup,\"ax\"\n"
  192. "4: ldi -2, %1\n"
  193. FIXUP_BRANCH(3b)
  194. " .previous\n"
  195. ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
  196. ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
  197. : "=r" (val), "=r" (ret)
  198. : "0" (val), "r" (saddr), "r" (regs->isr)
  199. : "r19", "r20", FIXUP_BRANCH_CLOBBER );
  200. #else
  201. {
  202. unsigned long valh=0,vall=0;
  203. __asm__ __volatile__ (
  204. " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */
  205. " mtsp %6, %%sr1\n"
  206. " dep %%r0,31,2,%5\n"
  207. "1: ldw 0(%%sr1,%5),%0\n"
  208. "2: ldw 4(%%sr1,%5),%1\n"
  209. "3: ldw 8(%%sr1,%5),%%r20\n"
  210. " subi 32,%%r19,%%r19\n"
  211. " mtsar %%r19\n"
  212. " vshd %0,%1,%0\n"
  213. " vshd %1,%%r20,%1\n"
  214. " copy %%r0, %2\n"
  215. "4: \n"
  216. " .section .fixup,\"ax\"\n"
  217. "5: ldi -2, %2\n"
  218. FIXUP_BRANCH(4b)
  219. " .previous\n"
  220. ASM_EXCEPTIONTABLE_ENTRY(1b,5b)
  221. ASM_EXCEPTIONTABLE_ENTRY(2b,5b)
  222. ASM_EXCEPTIONTABLE_ENTRY(3b,5b)
  223. : "=r" (valh), "=r" (vall), "=r" (ret)
  224. : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
  225. : "r19", "r20", FIXUP_BRANCH_CLOBBER );
  226. val=((__u64)valh<<32)|(__u64)vall;
  227. }
  228. #endif
  229. DPRINTF("val = 0x%llx\n", val);
  230. if (flop)
  231. regs->fr[toreg] = val;
  232. else if (toreg)
  233. regs->gr[toreg] = val;
  234. return ret;
  235. }
  236. static int emulate_sth(struct pt_regs *regs, int frreg)
  237. {
  238. unsigned long val = regs->gr[frreg];
  239. int ret;
  240. if (!frreg)
  241. val = 0;
  242. DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
  243. val, regs->isr, regs->ior);
  244. __asm__ __volatile__ (
  245. " mtsp %3, %%sr1\n"
  246. " extrw,u %1, 23, 8, %%r19\n"
  247. "1: stb %1, 1(%%sr1, %2)\n"
  248. "2: stb %%r19, 0(%%sr1, %2)\n"
  249. " copy %%r0, %0\n"
  250. "3: \n"
  251. " .section .fixup,\"ax\"\n"
  252. "4: ldi -2, %0\n"
  253. FIXUP_BRANCH(3b)
  254. " .previous\n"
  255. ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
  256. ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
  257. : "=r" (ret)
  258. : "r" (val), "r" (regs->ior), "r" (regs->isr)
  259. : "r19", FIXUP_BRANCH_CLOBBER );
  260. return ret;
  261. }
  262. static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
  263. {
  264. unsigned long val;
  265. int ret;
  266. if (flop)
  267. val = ((__u32*)(regs->fr))[frreg];
  268. else if (frreg)
  269. val = regs->gr[frreg];
  270. else
  271. val = 0;
  272. DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
  273. val, regs->isr, regs->ior);
  274. __asm__ __volatile__ (
  275. " mtsp %3, %%sr1\n"
  276. " zdep %2, 28, 2, %%r19\n"
  277. " dep %%r0, 31, 2, %2\n"
  278. " mtsar %%r19\n"
  279. " depwi,z -2, %%sar, 32, %%r19\n"
  280. "1: ldw 0(%%sr1,%2),%%r20\n"
  281. "2: ldw 4(%%sr1,%2),%%r21\n"
  282. " vshd %%r0, %1, %%r22\n"
  283. " vshd %1, %%r0, %%r1\n"
  284. " and %%r20, %%r19, %%r20\n"
  285. " andcm %%r21, %%r19, %%r21\n"
  286. " or %%r22, %%r20, %%r20\n"
  287. " or %%r1, %%r21, %%r21\n"
  288. " stw %%r20,0(%%sr1,%2)\n"
  289. " stw %%r21,4(%%sr1,%2)\n"
  290. " copy %%r0, %0\n"
  291. "3: \n"
  292. " .section .fixup,\"ax\"\n"
  293. "4: ldi -2, %0\n"
  294. FIXUP_BRANCH(3b)
  295. " .previous\n"
  296. ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
  297. ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
  298. : "=r" (ret)
  299. : "r" (val), "r" (regs->ior), "r" (regs->isr)
  300. : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
  301. return ret;
  302. }
  303. static int emulate_std(struct pt_regs *regs, int frreg, int flop)
  304. {
  305. __u64 val;
  306. int ret;
  307. if (flop)
  308. val = regs->fr[frreg];
  309. else if (frreg)
  310. val = regs->gr[frreg];
  311. else
  312. val = 0;
  313. DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
  314. val, regs->isr, regs->ior);
  315. #ifdef CONFIG_PA20
  316. #ifndef CONFIG_64BIT
  317. if (!flop)
  318. return -1;
  319. #endif
  320. __asm__ __volatile__ (
  321. " mtsp %3, %%sr1\n"
  322. " depd,z %2, 60, 3, %%r19\n"
  323. " depd %%r0, 63, 3, %2\n"
  324. " mtsar %%r19\n"
  325. " depdi,z -2, %%sar, 64, %%r19\n"
  326. "1: ldd 0(%%sr1,%2),%%r20\n"
  327. "2: ldd 8(%%sr1,%2),%%r21\n"
  328. " shrpd %%r0, %1, %%sar, %%r22\n"
  329. " shrpd %1, %%r0, %%sar, %%r1\n"
  330. " and %%r20, %%r19, %%r20\n"
  331. " andcm %%r21, %%r19, %%r21\n"
  332. " or %%r22, %%r20, %%r20\n"
  333. " or %%r1, %%r21, %%r21\n"
  334. "3: std %%r20,0(%%sr1,%2)\n"
  335. "4: std %%r21,8(%%sr1,%2)\n"
  336. " copy %%r0, %0\n"
  337. "5: \n"
  338. " .section .fixup,\"ax\"\n"
  339. "6: ldi -2, %0\n"
  340. FIXUP_BRANCH(5b)
  341. " .previous\n"
  342. ASM_EXCEPTIONTABLE_ENTRY(1b,6b)
  343. ASM_EXCEPTIONTABLE_ENTRY(2b,6b)
  344. ASM_EXCEPTIONTABLE_ENTRY(3b,6b)
  345. ASM_EXCEPTIONTABLE_ENTRY(4b,6b)
  346. : "=r" (ret)
  347. : "r" (val), "r" (regs->ior), "r" (regs->isr)
  348. : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
  349. #else
  350. {
  351. unsigned long valh=(val>>32),vall=(val&0xffffffffl);
  352. __asm__ __volatile__ (
  353. " mtsp %4, %%sr1\n"
  354. " zdep %2, 29, 2, %%r19\n"
  355. " dep %%r0, 31, 2, %3\n"
  356. " mtsar %%r19\n"
  357. " zvdepi -2, 32, %%r19\n"
  358. "1: ldw 0(%%sr1,%3),%%r20\n"
  359. "2: ldw 8(%%sr1,%3),%%r21\n"
  360. " vshd %1, %2, %%r1\n"
  361. " vshd %%r0, %1, %1\n"
  362. " vshd %2, %%r0, %2\n"
  363. " and %%r20, %%r19, %%r20\n"
  364. " andcm %%r21, %%r19, %%r21\n"
  365. " or %1, %%r20, %1\n"
  366. " or %2, %%r21, %2\n"
  367. "3: stw %1,0(%%sr1,%3)\n"
  368. "4: stw %%r1,4(%%sr1,%3)\n"
  369. "5: stw %2,8(%%sr1,%3)\n"
  370. " copy %%r0, %0\n"
  371. "6: \n"
  372. " .section .fixup,\"ax\"\n"
  373. "7: ldi -2, %0\n"
  374. FIXUP_BRANCH(6b)
  375. " .previous\n"
  376. ASM_EXCEPTIONTABLE_ENTRY(1b,7b)
  377. ASM_EXCEPTIONTABLE_ENTRY(2b,7b)
  378. ASM_EXCEPTIONTABLE_ENTRY(3b,7b)
  379. ASM_EXCEPTIONTABLE_ENTRY(4b,7b)
  380. ASM_EXCEPTIONTABLE_ENTRY(5b,7b)
  381. : "=r" (ret)
  382. : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
  383. : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER );
  384. }
  385. #endif
  386. return ret;
  387. }
  388. void handle_unaligned(struct pt_regs *regs)
  389. {
  390. static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
  391. unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
  392. int modify = 0;
  393. int ret = ERR_NOTHANDLED;
  394. register int flop=0; /* true if this is a flop */
  395. __inc_irq_stat(irq_unaligned_count);
  396. /* log a message with pacing */
  397. if (user_mode(regs)) {
  398. if (current->thread.flags & PARISC_UAC_SIGBUS) {
  399. goto force_sigbus;
  400. }
  401. if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
  402. __ratelimit(&ratelimit)) {
  403. char buf[256];
  404. sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
  405. current->comm, task_pid_nr(current), regs->ior, regs->iaoq[0]);
  406. printk(KERN_WARNING "%s", buf);
  407. #ifdef DEBUG_UNALIGNED
  408. show_regs(regs);
  409. #endif
  410. }
  411. if (!unaligned_enabled)
  412. goto force_sigbus;
  413. }
  414. /* handle modification - OK, it's ugly, see the instruction manual */
  415. switch (MAJOR_OP(regs->iir))
  416. {
  417. case 0x03:
  418. case 0x09:
  419. case 0x0b:
  420. if (regs->iir&0x20)
  421. {
  422. modify = 1;
  423. if (regs->iir&0x1000) /* short loads */
  424. if (regs->iir&0x200)
  425. newbase += IM5_3(regs->iir);
  426. else
  427. newbase += IM5_2(regs->iir);
  428. else if (regs->iir&0x2000) /* scaled indexed */
  429. {
  430. int shift=0;
  431. switch (regs->iir & OPCODE1_MASK)
  432. {
  433. case OPCODE_LDH_I:
  434. shift= 1; break;
  435. case OPCODE_LDW_I:
  436. shift= 2; break;
  437. case OPCODE_LDD_I:
  438. case OPCODE_LDDA_I:
  439. shift= 3; break;
  440. }
  441. newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
  442. } else /* simple indexed */
  443. newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
  444. }
  445. break;
  446. case 0x13:
  447. case 0x1b:
  448. modify = 1;
  449. newbase += IM14(regs->iir);
  450. break;
  451. case 0x14:
  452. case 0x1c:
  453. if (regs->iir&8)
  454. {
  455. modify = 1;
  456. newbase += IM14(regs->iir&~0xe);
  457. }
  458. break;
  459. case 0x16:
  460. case 0x1e:
  461. modify = 1;
  462. newbase += IM14(regs->iir&6);
  463. break;
  464. case 0x17:
  465. case 0x1f:
  466. if (regs->iir&4)
  467. {
  468. modify = 1;
  469. newbase += IM14(regs->iir&~4);
  470. }
  471. break;
  472. }
  473. /* TODO: make this cleaner... */
  474. switch (regs->iir & OPCODE1_MASK)
  475. {
  476. case OPCODE_LDH_I:
  477. case OPCODE_LDH_S:
  478. ret = emulate_ldh(regs, R3(regs->iir));
  479. break;
  480. case OPCODE_LDW_I:
  481. case OPCODE_LDWA_I:
  482. case OPCODE_LDW_S:
  483. case OPCODE_LDWA_S:
  484. ret = emulate_ldw(regs, R3(regs->iir),0);
  485. break;
  486. case OPCODE_STH:
  487. ret = emulate_sth(regs, R2(regs->iir));
  488. break;
  489. case OPCODE_STW:
  490. case OPCODE_STWA:
  491. ret = emulate_stw(regs, R2(regs->iir),0);
  492. break;
  493. #ifdef CONFIG_PA20
  494. case OPCODE_LDD_I:
  495. case OPCODE_LDDA_I:
  496. case OPCODE_LDD_S:
  497. case OPCODE_LDDA_S:
  498. ret = emulate_ldd(regs, R3(regs->iir),0);
  499. break;
  500. case OPCODE_STD:
  501. case OPCODE_STDA:
  502. ret = emulate_std(regs, R2(regs->iir),0);
  503. break;
  504. #endif
  505. case OPCODE_FLDWX:
  506. case OPCODE_FLDWS:
  507. case OPCODE_FLDWXR:
  508. case OPCODE_FLDWSR:
  509. flop=1;
  510. ret = emulate_ldw(regs,FR3(regs->iir),1);
  511. break;
  512. case OPCODE_FLDDX:
  513. case OPCODE_FLDDS:
  514. flop=1;
  515. ret = emulate_ldd(regs,R3(regs->iir),1);
  516. break;
  517. case OPCODE_FSTWX:
  518. case OPCODE_FSTWS:
  519. case OPCODE_FSTWXR:
  520. case OPCODE_FSTWSR:
  521. flop=1;
  522. ret = emulate_stw(regs,FR3(regs->iir),1);
  523. break;
  524. case OPCODE_FSTDX:
  525. case OPCODE_FSTDS:
  526. flop=1;
  527. ret = emulate_std(regs,R3(regs->iir),1);
  528. break;
  529. case OPCODE_LDCD_I:
  530. case OPCODE_LDCW_I:
  531. case OPCODE_LDCD_S:
  532. case OPCODE_LDCW_S:
  533. ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
  534. break;
  535. }
  536. switch (regs->iir & OPCODE2_MASK)
  537. {
  538. case OPCODE_FLDD_L:
  539. flop=1;
  540. ret = emulate_ldd(regs,R2(regs->iir),1);
  541. break;
  542. case OPCODE_FSTD_L:
  543. flop=1;
  544. ret = emulate_std(regs, R2(regs->iir),1);
  545. break;
  546. #ifdef CONFIG_PA20
  547. case OPCODE_LDD_L:
  548. ret = emulate_ldd(regs, R2(regs->iir),0);
  549. break;
  550. case OPCODE_STD_L:
  551. ret = emulate_std(regs, R2(regs->iir),0);
  552. break;
  553. #endif
  554. }
  555. switch (regs->iir & OPCODE3_MASK)
  556. {
  557. case OPCODE_FLDW_L:
  558. flop=1;
  559. ret = emulate_ldw(regs, R2(regs->iir), 1);
  560. break;
  561. case OPCODE_LDW_M:
  562. ret = emulate_ldw(regs, R2(regs->iir), 0);
  563. break;
  564. case OPCODE_FSTW_L:
  565. flop=1;
  566. ret = emulate_stw(regs, R2(regs->iir),1);
  567. break;
  568. case OPCODE_STW_M:
  569. ret = emulate_stw(regs, R2(regs->iir),0);
  570. break;
  571. }
  572. switch (regs->iir & OPCODE4_MASK)
  573. {
  574. case OPCODE_LDH_L:
  575. ret = emulate_ldh(regs, R2(regs->iir));
  576. break;
  577. case OPCODE_LDW_L:
  578. case OPCODE_LDWM:
  579. ret = emulate_ldw(regs, R2(regs->iir),0);
  580. break;
  581. case OPCODE_STH_L:
  582. ret = emulate_sth(regs, R2(regs->iir));
  583. break;
  584. case OPCODE_STW_L:
  585. case OPCODE_STWM:
  586. ret = emulate_stw(regs, R2(regs->iir),0);
  587. break;
  588. }
  589. if (ret == 0 && modify && R1(regs->iir))
  590. regs->gr[R1(regs->iir)] = newbase;
  591. if (ret == ERR_NOTHANDLED)
  592. printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
  593. DPRINTF("ret = %d\n", ret);
  594. if (ret)
  595. {
  596. /*
  597. * The unaligned handler failed.
  598. * If we were called by __get_user() or __put_user() jump
  599. * to it's exception fixup handler instead of crashing.
  600. */
  601. if (!user_mode(regs) && fixup_exception(regs))
  602. return;
  603. printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
  604. die_if_kernel("Unaligned data reference", regs, 28);
  605. if (ret == ERR_PAGEFAULT)
  606. {
  607. force_sig_fault(SIGSEGV, SEGV_MAPERR,
  608. (void __user *)regs->ior);
  609. }
  610. else
  611. {
  612. force_sigbus:
  613. /* couldn't handle it ... */
  614. force_sig_fault(SIGBUS, BUS_ADRALN,
  615. (void __user *)regs->ior);
  616. }
  617. return;
  618. }
  619. /* else we handled it, let life go on. */
  620. regs->gr[0]|=PSW_N;
  621. }
  622. /*
  623. * NB: check_unaligned() is only used for PCXS processors right
  624. * now, so we only check for PA1.1 encodings at this point.
  625. */
  626. int
  627. check_unaligned(struct pt_regs *regs)
  628. {
  629. unsigned long align_mask;
  630. /* Get alignment mask */
  631. align_mask = 0UL;
  632. switch (regs->iir & OPCODE1_MASK) {
  633. case OPCODE_LDH_I:
  634. case OPCODE_LDH_S:
  635. case OPCODE_STH:
  636. align_mask = 1UL;
  637. break;
  638. case OPCODE_LDW_I:
  639. case OPCODE_LDWA_I:
  640. case OPCODE_LDW_S:
  641. case OPCODE_LDWA_S:
  642. case OPCODE_STW:
  643. case OPCODE_STWA:
  644. align_mask = 3UL;
  645. break;
  646. default:
  647. switch (regs->iir & OPCODE4_MASK) {
  648. case OPCODE_LDH_L:
  649. case OPCODE_STH_L:
  650. align_mask = 1UL;
  651. break;
  652. case OPCODE_LDW_L:
  653. case OPCODE_LDWM:
  654. case OPCODE_STW_L:
  655. case OPCODE_STWM:
  656. align_mask = 3UL;
  657. break;
  658. }
  659. break;
  660. }
  661. return (int)(regs->ior & align_mask);
  662. }