perf.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Parisc performance counters
  4. * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
  5. *
  6. * This code is derived, with permission, from HP/UX sources.
  7. */
  8. /*
  9. * Edited comment from original sources:
  10. *
  11. * This driver programs the PCX-U/PCX-W performance counters
  12. * on the PA-RISC 2.0 chips. The driver keeps all images now
  13. * internally to the kernel to hopefully eliminate the possibility
  14. * of a bad image halting the CPU. Also, there are different
  15. * images for the PCX-W and later chips vs the PCX-U chips.
  16. *
  17. * Only 1 process is allowed to access the driver at any time,
  18. * so the only protection that is needed is at open and close.
  19. * A variable "perf_enabled" is used to hold the state of the
  20. * driver. The spinlock "perf_lock" is used to protect the
  21. * modification of the state during open/close operations so
  22. * multiple processes don't get into the driver simultaneously.
  23. *
  24. * This driver accesses the processor directly vs going through
  25. * the PDC INTRIGUE calls. This is done to eliminate bugs introduced
  26. * in various PDC revisions. The code is much more maintainable
  27. * and reliable this way vs having to debug on every version of PDC
  28. * on every box.
  29. */
  30. #include <linux/capability.h>
  31. #include <linux/init.h>
  32. #include <linux/proc_fs.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/uaccess.h>
  36. #include <asm/perf.h>
  37. #include <asm/parisc-device.h>
  38. #include <asm/processor.h>
  39. #include <asm/runway.h>
  40. #include <asm/io.h> /* for __raw_read() */
  41. #include "perf_images.h"
  42. #define MAX_RDR_WORDS 24
  43. #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */
  44. /* definition of RDR regs */
  45. struct rdr_tbl_ent {
  46. uint16_t width;
  47. uint8_t num_words;
  48. uint8_t write_control;
  49. };
  50. static int perf_processor_interface __read_mostly = UNKNOWN_INTF;
  51. static int perf_enabled __read_mostly;
  52. static DEFINE_SPINLOCK(perf_lock);
  53. struct parisc_device *cpu_device __read_mostly;
  54. /* RDRs to write for PCX-W */
  55. static const int perf_rdrs_W[] =
  56. { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
  57. /* RDRs to write for PCX-U */
  58. static const int perf_rdrs_U[] =
  59. { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
  60. /* RDR register descriptions for PCX-W */
  61. static const struct rdr_tbl_ent perf_rdr_tbl_W[] = {
  62. { 19, 1, 8 }, /* RDR 0 */
  63. { 16, 1, 16 }, /* RDR 1 */
  64. { 72, 2, 0 }, /* RDR 2 */
  65. { 81, 2, 0 }, /* RDR 3 */
  66. { 328, 6, 0 }, /* RDR 4 */
  67. { 160, 3, 0 }, /* RDR 5 */
  68. { 336, 6, 0 }, /* RDR 6 */
  69. { 164, 3, 0 }, /* RDR 7 */
  70. { 0, 0, 0 }, /* RDR 8 */
  71. { 35, 1, 0 }, /* RDR 9 */
  72. { 6, 1, 0 }, /* RDR 10 */
  73. { 18, 1, 0 }, /* RDR 11 */
  74. { 13, 1, 0 }, /* RDR 12 */
  75. { 8, 1, 0 }, /* RDR 13 */
  76. { 8, 1, 0 }, /* RDR 14 */
  77. { 8, 1, 0 }, /* RDR 15 */
  78. { 1530, 24, 0 }, /* RDR 16 */
  79. { 16, 1, 0 }, /* RDR 17 */
  80. { 4, 1, 0 }, /* RDR 18 */
  81. { 0, 0, 0 }, /* RDR 19 */
  82. { 152, 3, 24 }, /* RDR 20 */
  83. { 152, 3, 24 }, /* RDR 21 */
  84. { 233, 4, 48 }, /* RDR 22 */
  85. { 233, 4, 48 }, /* RDR 23 */
  86. { 71, 2, 0 }, /* RDR 24 */
  87. { 71, 2, 0 }, /* RDR 25 */
  88. { 11, 1, 0 }, /* RDR 26 */
  89. { 18, 1, 0 }, /* RDR 27 */
  90. { 128, 2, 0 }, /* RDR 28 */
  91. { 0, 0, 0 }, /* RDR 29 */
  92. { 16, 1, 0 }, /* RDR 30 */
  93. { 16, 1, 0 }, /* RDR 31 */
  94. };
  95. /* RDR register descriptions for PCX-U */
  96. static const struct rdr_tbl_ent perf_rdr_tbl_U[] = {
  97. { 19, 1, 8 }, /* RDR 0 */
  98. { 32, 1, 16 }, /* RDR 1 */
  99. { 20, 1, 0 }, /* RDR 2 */
  100. { 0, 0, 0 }, /* RDR 3 */
  101. { 344, 6, 0 }, /* RDR 4 */
  102. { 176, 3, 0 }, /* RDR 5 */
  103. { 336, 6, 0 }, /* RDR 6 */
  104. { 0, 0, 0 }, /* RDR 7 */
  105. { 0, 0, 0 }, /* RDR 8 */
  106. { 0, 0, 0 }, /* RDR 9 */
  107. { 28, 1, 0 }, /* RDR 10 */
  108. { 33, 1, 0 }, /* RDR 11 */
  109. { 0, 0, 0 }, /* RDR 12 */
  110. { 230, 4, 0 }, /* RDR 13 */
  111. { 32, 1, 0 }, /* RDR 14 */
  112. { 128, 2, 0 }, /* RDR 15 */
  113. { 1494, 24, 0 }, /* RDR 16 */
  114. { 18, 1, 0 }, /* RDR 17 */
  115. { 4, 1, 0 }, /* RDR 18 */
  116. { 0, 0, 0 }, /* RDR 19 */
  117. { 158, 3, 24 }, /* RDR 20 */
  118. { 158, 3, 24 }, /* RDR 21 */
  119. { 194, 4, 48 }, /* RDR 22 */
  120. { 194, 4, 48 }, /* RDR 23 */
  121. { 71, 2, 0 }, /* RDR 24 */
  122. { 71, 2, 0 }, /* RDR 25 */
  123. { 28, 1, 0 }, /* RDR 26 */
  124. { 33, 1, 0 }, /* RDR 27 */
  125. { 88, 2, 0 }, /* RDR 28 */
  126. { 32, 1, 0 }, /* RDR 29 */
  127. { 24, 1, 0 }, /* RDR 30 */
  128. { 16, 1, 0 }, /* RDR 31 */
  129. };
  130. /*
  131. * A non-zero write_control in the above tables is a byte offset into
  132. * this array.
  133. */
  134. static const uint64_t perf_bitmasks[] = {
  135. 0x0000000000000000ul, /* first dbl word must be zero */
  136. 0xfdffe00000000000ul, /* RDR0 bitmask */
  137. 0x003f000000000000ul, /* RDR1 bitmask */
  138. 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
  139. 0xfffffffffffffffful,
  140. 0xfffffffc00000000ul,
  141. 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
  142. 0xfffffffffffffffful,
  143. 0xfffffffffffffffcul,
  144. 0xff00000000000000ul
  145. };
  146. /*
  147. * Write control bitmasks for Pa-8700 processor given
  148. * some things have changed slightly.
  149. */
  150. static const uint64_t perf_bitmasks_piranha[] = {
  151. 0x0000000000000000ul, /* first dbl word must be zero */
  152. 0xfdffe00000000000ul, /* RDR0 bitmask */
  153. 0x003f000000000000ul, /* RDR1 bitmask */
  154. 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
  155. 0xfffffffffffffffful,
  156. 0xfffffffc00000000ul,
  157. 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
  158. 0xfffffffffffffffful,
  159. 0xfffffffffffffffful,
  160. 0xfffc000000000000ul
  161. };
  162. static const uint64_t *bitmask_array; /* array of bitmasks to use */
  163. /******************************************************************************
  164. * Function Prototypes
  165. *****************************************************************************/
  166. static int perf_config(uint32_t *image_ptr);
  167. static int perf_release(struct inode *inode, struct file *file);
  168. static int perf_open(struct inode *inode, struct file *file);
  169. static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos);
  170. static ssize_t perf_write(struct file *file, const char __user *buf,
  171. size_t count, loff_t *ppos);
  172. static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
  173. static void perf_start_counters(void);
  174. static int perf_stop_counters(uint32_t *raddr);
  175. static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
  176. static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
  177. static int perf_rdr_clear(uint32_t rdr_num);
  178. static int perf_write_image(uint64_t *memaddr);
  179. static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
  180. /* External Assembly Routines */
  181. extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
  182. extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
  183. extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
  184. extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);
  185. extern void perf_intrigue_enable_perf_counters (void);
  186. extern void perf_intrigue_disable_perf_counters (void);
  187. /******************************************************************************
  188. * Function Definitions
  189. *****************************************************************************/
  190. /*
  191. * configure:
  192. *
  193. * Configure the cpu with a given data image. First turn off the counters,
  194. * then download the image, then turn the counters back on.
  195. */
  196. static int perf_config(uint32_t *image_ptr)
  197. {
  198. long error;
  199. uint32_t raddr[4];
  200. /* Stop the counters*/
  201. error = perf_stop_counters(raddr);
  202. if (error != 0) {
  203. printk("perf_config: perf_stop_counters = %ld\n", error);
  204. return -EINVAL;
  205. }
  206. printk("Preparing to write image\n");
  207. /* Write the image to the chip */
  208. error = perf_write_image((uint64_t *)image_ptr);
  209. if (error != 0) {
  210. printk("perf_config: DOWNLOAD = %ld\n", error);
  211. return -EINVAL;
  212. }
  213. printk("Preparing to start counters\n");
  214. /* Start the counters */
  215. perf_start_counters();
  216. return sizeof(uint32_t);
  217. }
  218. /*
  219. * Open the device and initialize all of its memory. The device is only
  220. * opened once, but can be "queried" by multiple processes that know its
  221. * file descriptor.
  222. */
  223. static int perf_open(struct inode *inode, struct file *file)
  224. {
  225. spin_lock(&perf_lock);
  226. if (perf_enabled) {
  227. spin_unlock(&perf_lock);
  228. return -EBUSY;
  229. }
  230. perf_enabled = 1;
  231. spin_unlock(&perf_lock);
  232. return 0;
  233. }
  234. /*
  235. * Close the device.
  236. */
  237. static int perf_release(struct inode *inode, struct file *file)
  238. {
  239. spin_lock(&perf_lock);
  240. perf_enabled = 0;
  241. spin_unlock(&perf_lock);
  242. return 0;
  243. }
  244. /*
  245. * Read does nothing for this driver
  246. */
  247. static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos)
  248. {
  249. return 0;
  250. }
  251. /*
  252. * write:
  253. *
  254. * This routine downloads the image to the chip. It must be
  255. * called on the processor that the download should happen
  256. * on.
  257. */
  258. static ssize_t perf_write(struct file *file, const char __user *buf,
  259. size_t count, loff_t *ppos)
  260. {
  261. size_t image_size;
  262. uint32_t image_type;
  263. uint32_t interface_type;
  264. uint32_t test;
  265. if (perf_processor_interface == ONYX_INTF)
  266. image_size = PCXU_IMAGE_SIZE;
  267. else if (perf_processor_interface == CUDA_INTF)
  268. image_size = PCXW_IMAGE_SIZE;
  269. else
  270. return -EFAULT;
  271. if (!perfmon_capable())
  272. return -EACCES;
  273. if (count != sizeof(uint32_t))
  274. return -EIO;
  275. if (copy_from_user(&image_type, buf, sizeof(uint32_t)))
  276. return -EFAULT;
  277. /* Get the interface type and test type */
  278. interface_type = (image_type >> 16) & 0xffff;
  279. test = (image_type & 0xffff);
  280. /* Make sure everything makes sense */
  281. /* First check the machine type is correct for
  282. the requested image */
  283. if (((perf_processor_interface == CUDA_INTF) &&
  284. (interface_type != CUDA_INTF)) ||
  285. ((perf_processor_interface == ONYX_INTF) &&
  286. (interface_type != ONYX_INTF)))
  287. return -EINVAL;
  288. /* Next check to make sure the requested image
  289. is valid */
  290. if (((interface_type == CUDA_INTF) &&
  291. (test >= MAX_CUDA_IMAGES)) ||
  292. ((interface_type == ONYX_INTF) &&
  293. (test >= MAX_ONYX_IMAGES)))
  294. return -EINVAL;
  295. /* Copy the image into the processor */
  296. if (interface_type == CUDA_INTF)
  297. return perf_config(cuda_images[test]);
  298. else
  299. return perf_config(onyx_images[test]);
  300. return count;
  301. }
  302. /*
  303. * Patch the images that need to know the IVA addresses.
  304. */
  305. static void perf_patch_images(void)
  306. {
  307. #if 0 /* FIXME!! */
  308. /*
  309. * NOTE: this routine is VERY specific to the current TLB image.
  310. * If the image is changed, this routine might also need to be changed.
  311. */
  312. extern void $i_itlb_miss_2_0();
  313. extern void $i_dtlb_miss_2_0();
  314. extern void PA2_0_iva();
  315. /*
  316. * We can only use the lower 32-bits, the upper 32-bits should be 0
  317. * anyway given this is in the kernel
  318. */
  319. uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0);
  320. uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0);
  321. uint32_t IVAaddress = (uint32_t)&PA2_0_iva;
  322. if (perf_processor_interface == ONYX_INTF) {
  323. /* clear last 2 bytes */
  324. onyx_images[TLBMISS][15] &= 0xffffff00;
  325. /* set 2 bytes */
  326. onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
  327. onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
  328. onyx_images[TLBMISS][17] = itlb_addr;
  329. /* clear last 2 bytes */
  330. onyx_images[TLBHANDMISS][15] &= 0xffffff00;
  331. /* set 2 bytes */
  332. onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
  333. onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
  334. onyx_images[TLBHANDMISS][17] = itlb_addr;
  335. /* clear last 2 bytes */
  336. onyx_images[BIG_CPI][15] &= 0xffffff00;
  337. /* set 2 bytes */
  338. onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24));
  339. onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
  340. onyx_images[BIG_CPI][17] = itlb_addr;
  341. onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */
  342. onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */
  343. onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;
  344. } else if (perf_processor_interface == CUDA_INTF) {
  345. /* Cuda interface */
  346. cuda_images[TLBMISS][16] =
  347. (cuda_images[TLBMISS][16]&0xffff0000) |
  348. ((dtlb_addr >> 8)&0x0000ffff);
  349. cuda_images[TLBMISS][17] =
  350. ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
  351. cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
  352. cuda_images[TLBHANDMISS][16] =
  353. (cuda_images[TLBHANDMISS][16]&0xffff0000) |
  354. ((dtlb_addr >> 8)&0x0000ffff);
  355. cuda_images[TLBHANDMISS][17] =
  356. ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
  357. cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
  358. cuda_images[BIG_CPI][16] =
  359. (cuda_images[BIG_CPI][16]&0xffff0000) |
  360. ((dtlb_addr >> 8)&0x0000ffff);
  361. cuda_images[BIG_CPI][17] =
  362. ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
  363. cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
  364. } else {
  365. /* Unknown type */
  366. }
  367. #endif
  368. }
  369. /*
  370. * ioctl routine
  371. * All routines effect the processor that they are executed on. Thus you
  372. * must be running on the processor that you wish to change.
  373. */
  374. static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  375. {
  376. long error_start;
  377. uint32_t raddr[4];
  378. int error = 0;
  379. switch (cmd) {
  380. case PA_PERF_ON:
  381. /* Start the counters */
  382. perf_start_counters();
  383. break;
  384. case PA_PERF_OFF:
  385. error_start = perf_stop_counters(raddr);
  386. if (error_start != 0) {
  387. printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);
  388. error = -EFAULT;
  389. break;
  390. }
  391. /* copy out the Counters */
  392. if (copy_to_user((void __user *)arg, raddr,
  393. sizeof (raddr)) != 0) {
  394. error = -EFAULT;
  395. break;
  396. }
  397. break;
  398. case PA_PERF_VERSION:
  399. /* Return the version # */
  400. error = put_user(PERF_VERSION, (int *)arg);
  401. break;
  402. default:
  403. error = -ENOTTY;
  404. }
  405. return error;
  406. }
  407. static const struct file_operations perf_fops = {
  408. .llseek = no_llseek,
  409. .read = perf_read,
  410. .write = perf_write,
  411. .unlocked_ioctl = perf_ioctl,
  412. .compat_ioctl = perf_ioctl,
  413. .open = perf_open,
  414. .release = perf_release
  415. };
  416. static struct miscdevice perf_dev = {
  417. MISC_DYNAMIC_MINOR,
  418. PA_PERF_DEV,
  419. &perf_fops
  420. };
  421. /*
  422. * Initialize the module
  423. */
  424. static int __init perf_init(void)
  425. {
  426. int ret;
  427. /* Determine correct processor interface to use */
  428. bitmask_array = perf_bitmasks;
  429. if (boot_cpu_data.cpu_type == pcxu ||
  430. boot_cpu_data.cpu_type == pcxu_) {
  431. perf_processor_interface = ONYX_INTF;
  432. } else if (boot_cpu_data.cpu_type == pcxw ||
  433. boot_cpu_data.cpu_type == pcxw_ ||
  434. boot_cpu_data.cpu_type == pcxw2 ||
  435. boot_cpu_data.cpu_type == mako ||
  436. boot_cpu_data.cpu_type == mako2) {
  437. perf_processor_interface = CUDA_INTF;
  438. if (boot_cpu_data.cpu_type == pcxw2 ||
  439. boot_cpu_data.cpu_type == mako ||
  440. boot_cpu_data.cpu_type == mako2)
  441. bitmask_array = perf_bitmasks_piranha;
  442. } else {
  443. perf_processor_interface = UNKNOWN_INTF;
  444. printk("Performance monitoring counters not supported on this processor\n");
  445. return -ENODEV;
  446. }
  447. ret = misc_register(&perf_dev);
  448. if (ret) {
  449. printk(KERN_ERR "Performance monitoring counters: "
  450. "cannot register misc device.\n");
  451. return ret;
  452. }
  453. /* Patch the images to match the system */
  454. perf_patch_images();
  455. /* TODO: this only lets us access the first cpu.. what to do for SMP? */
  456. cpu_device = per_cpu(cpu_data, 0).dev;
  457. printk("Performance monitoring counters enabled for %s\n",
  458. per_cpu(cpu_data, 0).dev->name);
  459. return 0;
  460. }
  461. device_initcall(perf_init);
  462. /*
  463. * perf_start_counters(void)
  464. *
  465. * Start the counters.
  466. */
  467. static void perf_start_counters(void)
  468. {
  469. /* Enable performance monitor counters */
  470. perf_intrigue_enable_perf_counters();
  471. }
  472. /*
  473. * perf_stop_counters
  474. *
  475. * Stop the performance counters and save counts
  476. * in a per_processor array.
  477. */
  478. static int perf_stop_counters(uint32_t *raddr)
  479. {
  480. uint64_t userbuf[MAX_RDR_WORDS];
  481. /* Disable performance counters */
  482. perf_intrigue_disable_perf_counters();
  483. if (perf_processor_interface == ONYX_INTF) {
  484. uint64_t tmp64;
  485. /*
  486. * Read the counters
  487. */
  488. if (!perf_rdr_read_ubuf(16, userbuf))
  489. return -13;
  490. /* Counter0 is bits 1398 to 1429 */
  491. tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
  492. tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
  493. /* OR sticky0 (bit 1430) to counter0 bit 32 */
  494. tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
  495. raddr[0] = (uint32_t)tmp64;
  496. /* Counter1 is bits 1431 to 1462 */
  497. tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
  498. /* OR sticky1 (bit 1463) to counter1 bit 32 */
  499. tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
  500. raddr[1] = (uint32_t)tmp64;
  501. /* Counter2 is bits 1464 to 1495 */
  502. tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
  503. tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
  504. /* OR sticky2 (bit 1496) to counter2 bit 32 */
  505. tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
  506. raddr[2] = (uint32_t)tmp64;
  507. /* Counter3 is bits 1497 to 1528 */
  508. tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
  509. /* OR sticky3 (bit 1529) to counter3 bit 32 */
  510. tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
  511. raddr[3] = (uint32_t)tmp64;
  512. /*
  513. * Zero out the counters
  514. */
  515. /*
  516. * The counters and sticky-bits comprise the last 132 bits
  517. * (1398 - 1529) of RDR16 on a U chip. We'll zero these
  518. * out the easy way: zero out last 10 bits of dword 21,
  519. * all of dword 22 and 58 bits (plus 6 don't care bits) of
  520. * dword 23.
  521. */
  522. userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */
  523. userbuf[22] = 0;
  524. userbuf[23] = 0;
  525. /*
  526. * Write back the zeroed bytes + the image given
  527. * the read was destructive.
  528. */
  529. perf_rdr_write(16, userbuf);
  530. } else {
  531. /*
  532. * Read RDR-15 which contains the counters and sticky bits
  533. */
  534. if (!perf_rdr_read_ubuf(15, userbuf)) {
  535. return -13;
  536. }
  537. /*
  538. * Clear out the counters
  539. */
  540. perf_rdr_clear(15);
  541. /*
  542. * Copy the counters
  543. */
  544. raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);
  545. raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);
  546. raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
  547. raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
  548. }
  549. return 0;
  550. }
  551. /*
  552. * perf_rdr_get_entry
  553. *
  554. * Retrieve a pointer to the description of what this
  555. * RDR contains.
  556. */
  557. static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
  558. {
  559. if (perf_processor_interface == ONYX_INTF) {
  560. return &perf_rdr_tbl_U[rdr_num];
  561. } else {
  562. return &perf_rdr_tbl_W[rdr_num];
  563. }
  564. }
  565. /*
  566. * perf_rdr_read_ubuf
  567. *
  568. * Read the RDR value into the buffer specified.
  569. */
  570. static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
  571. {
  572. uint64_t data, data_mask = 0;
  573. uint32_t width, xbits, i;
  574. const struct rdr_tbl_ent *tentry;
  575. tentry = perf_rdr_get_entry(rdr_num);
  576. if ((width = tentry->width) == 0)
  577. return 0;
  578. /* Clear out buffer */
  579. i = tentry->num_words;
  580. while (i--) {
  581. buffer[i] = 0;
  582. }
  583. /* Check for bits an even number of 64 */
  584. if ((xbits = width & 0x03f) != 0) {
  585. data_mask = 1;
  586. data_mask <<= (64 - xbits);
  587. data_mask--;
  588. }
  589. /* Grab all of the data */
  590. i = tentry->num_words;
  591. while (i--) {
  592. if (perf_processor_interface == ONYX_INTF) {
  593. data = perf_rdr_shift_in_U(rdr_num, width);
  594. } else {
  595. data = perf_rdr_shift_in_W(rdr_num, width);
  596. }
  597. if (xbits) {
  598. buffer[i] |= (data << (64 - xbits));
  599. if (i) {
  600. buffer[i-1] |= ((data >> xbits) & data_mask);
  601. }
  602. } else {
  603. buffer[i] = data;
  604. }
  605. }
  606. return 1;
  607. }
  608. /*
  609. * perf_rdr_clear
  610. *
  611. * Zero out the given RDR register
  612. */
  613. static int perf_rdr_clear(uint32_t rdr_num)
  614. {
  615. const struct rdr_tbl_ent *tentry;
  616. int32_t i;
  617. tentry = perf_rdr_get_entry(rdr_num);
  618. if (tentry->width == 0) {
  619. return -1;
  620. }
  621. i = tentry->num_words;
  622. while (i--) {
  623. if (perf_processor_interface == ONYX_INTF) {
  624. perf_rdr_shift_out_U(rdr_num, 0UL);
  625. } else {
  626. perf_rdr_shift_out_W(rdr_num, 0UL);
  627. }
  628. }
  629. return 0;
  630. }
  631. /*
  632. * perf_write_image
  633. *
  634. * Write the given image out to the processor
  635. */
  636. static int perf_write_image(uint64_t *memaddr)
  637. {
  638. uint64_t buffer[MAX_RDR_WORDS];
  639. uint64_t *bptr;
  640. uint32_t dwords;
  641. const uint32_t *intrigue_rdr;
  642. const uint64_t *intrigue_bitmask;
  643. uint64_t tmp64;
  644. void __iomem *runway;
  645. const struct rdr_tbl_ent *tentry;
  646. int i;
  647. /* Clear out counters */
  648. if (perf_processor_interface == ONYX_INTF) {
  649. perf_rdr_clear(16);
  650. /* Toggle performance monitor */
  651. perf_intrigue_enable_perf_counters();
  652. perf_intrigue_disable_perf_counters();
  653. intrigue_rdr = perf_rdrs_U;
  654. } else {
  655. perf_rdr_clear(15);
  656. intrigue_rdr = perf_rdrs_W;
  657. }
  658. /* Write all RDRs */
  659. while (*intrigue_rdr != -1) {
  660. tentry = perf_rdr_get_entry(*intrigue_rdr);
  661. perf_rdr_read_ubuf(*intrigue_rdr, buffer);
  662. bptr = &buffer[0];
  663. dwords = tentry->num_words;
  664. if (tentry->write_control) {
  665. intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];
  666. while (dwords--) {
  667. tmp64 = *intrigue_bitmask & *memaddr++;
  668. tmp64 |= (~(*intrigue_bitmask++)) & *bptr;
  669. *bptr++ = tmp64;
  670. }
  671. } else {
  672. while (dwords--) {
  673. *bptr++ = *memaddr++;
  674. }
  675. }
  676. perf_rdr_write(*intrigue_rdr, buffer);
  677. intrigue_rdr++;
  678. }
  679. /*
  680. * Now copy out the Runway stuff which is not in RDRs
  681. */
  682. if (cpu_device == NULL)
  683. {
  684. printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");
  685. return -1;
  686. }
  687. runway = ioremap(cpu_device->hpa.start, 4096);
  688. if (!runway) {
  689. pr_err("perf_write_image: ioremap failed!\n");
  690. return -ENOMEM;
  691. }
  692. /* Merge intrigue bits into Runway STATUS 0 */
  693. tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;
  694. __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul),
  695. runway + RUNWAY_STATUS);
  696. /* Write RUNWAY DEBUG registers */
  697. for (i = 0; i < 8; i++) {
  698. __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG);
  699. }
  700. return 0;
  701. }
  702. /*
  703. * perf_rdr_write
  704. *
  705. * Write the given RDR register with the contents
  706. * of the given buffer.
  707. */
  708. static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
  709. {
  710. const struct rdr_tbl_ent *tentry;
  711. int32_t i;
  712. printk("perf_rdr_write\n");
  713. tentry = perf_rdr_get_entry(rdr_num);
  714. if (tentry->width == 0) { return; }
  715. i = tentry->num_words;
  716. while (i--) {
  717. if (perf_processor_interface == ONYX_INTF) {
  718. perf_rdr_shift_out_U(rdr_num, buffer[i]);
  719. } else {
  720. perf_rdr_shift_out_W(rdr_num, buffer[i]);
  721. }
  722. }
  723. printk("perf_rdr_write done\n");
  724. }