cache.c 18 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
  7. * Copyright (C) 1999 SuSE GmbH Nuernberg
  8. * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  9. *
  10. * Cache and TLB management
  11. *
  12. */
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mm.h>
  16. #include <linux/module.h>
  17. #include <linux/seq_file.h>
  18. #include <linux/pagemap.h>
  19. #include <linux/sched.h>
  20. #include <linux/sched/mm.h>
  21. #include <asm/pdc.h>
  22. #include <asm/cache.h>
  23. #include <asm/cacheflush.h>
  24. #include <asm/tlbflush.h>
  25. #include <asm/page.h>
  26. #include <asm/processor.h>
  27. #include <asm/sections.h>
  28. #include <asm/shmparam.h>
  29. int split_tlb __ro_after_init;
  30. int dcache_stride __ro_after_init;
  31. int icache_stride __ro_after_init;
  32. EXPORT_SYMBOL(dcache_stride);
  33. void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  34. EXPORT_SYMBOL(flush_dcache_page_asm);
  35. void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  36. void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  37. /* On some machines (i.e., ones with the Merced bus), there can be
  38. * only a single PxTLB broadcast at a time; this must be guaranteed
  39. * by software. We need a spinlock around all TLB flushes to ensure
  40. * this.
  41. */
  42. DEFINE_SPINLOCK(pa_tlb_flush_lock);
  43. /* Swapper page setup lock. */
  44. DEFINE_SPINLOCK(pa_swapper_pg_lock);
  45. #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
  46. int pa_serialize_tlb_flushes __ro_after_init;
  47. #endif
  48. struct pdc_cache_info cache_info __ro_after_init;
  49. #ifndef CONFIG_PA20
  50. static struct pdc_btlb_info btlb_info __ro_after_init;
  51. #endif
  52. #ifdef CONFIG_SMP
  53. void
  54. flush_data_cache(void)
  55. {
  56. on_each_cpu(flush_data_cache_local, NULL, 1);
  57. }
  58. void
  59. flush_instruction_cache(void)
  60. {
  61. on_each_cpu(flush_instruction_cache_local, NULL, 1);
  62. }
  63. #endif
  64. void
  65. flush_cache_all_local(void)
  66. {
  67. flush_instruction_cache_local(NULL);
  68. flush_data_cache_local(NULL);
  69. }
  70. EXPORT_SYMBOL(flush_cache_all_local);
  71. /* Virtual address of pfn. */
  72. #define pfn_va(pfn) __va(PFN_PHYS(pfn))
  73. void
  74. update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  75. {
  76. unsigned long pfn = pte_pfn(*ptep);
  77. struct page *page;
  78. /* We don't have pte special. As a result, we can be called with
  79. an invalid pfn and we don't need to flush the kernel dcache page.
  80. This occurs with FireGL card in C8000. */
  81. if (!pfn_valid(pfn))
  82. return;
  83. page = pfn_to_page(pfn);
  84. if (page_mapping_file(page) &&
  85. test_bit(PG_dcache_dirty, &page->flags)) {
  86. flush_kernel_dcache_page_addr(pfn_va(pfn));
  87. clear_bit(PG_dcache_dirty, &page->flags);
  88. } else if (parisc_requires_coherency())
  89. flush_kernel_dcache_page_addr(pfn_va(pfn));
  90. }
  91. void
  92. show_cache_info(struct seq_file *m)
  93. {
  94. char buf[32];
  95. seq_printf(m, "I-cache\t\t: %ld KB\n",
  96. cache_info.ic_size/1024 );
  97. if (cache_info.dc_loop != 1)
  98. snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
  99. seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
  100. cache_info.dc_size/1024,
  101. (cache_info.dc_conf.cc_wt ? "WT":"WB"),
  102. (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
  103. ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
  104. seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
  105. cache_info.it_size,
  106. cache_info.dt_size,
  107. cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
  108. );
  109. #ifndef CONFIG_PA20
  110. /* BTLB - Block TLB */
  111. if (btlb_info.max_size==0) {
  112. seq_printf(m, "BTLB\t\t: not supported\n" );
  113. } else {
  114. seq_printf(m,
  115. "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
  116. "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
  117. "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
  118. btlb_info.max_size, (int)4096,
  119. btlb_info.max_size>>8,
  120. btlb_info.fixed_range_info.num_i,
  121. btlb_info.fixed_range_info.num_d,
  122. btlb_info.fixed_range_info.num_comb,
  123. btlb_info.variable_range_info.num_i,
  124. btlb_info.variable_range_info.num_d,
  125. btlb_info.variable_range_info.num_comb
  126. );
  127. }
  128. #endif
  129. }
  130. void __init
  131. parisc_cache_init(void)
  132. {
  133. if (pdc_cache_info(&cache_info) < 0)
  134. panic("parisc_cache_init: pdc_cache_info failed");
  135. #if 0
  136. printk("ic_size %lx dc_size %lx it_size %lx\n",
  137. cache_info.ic_size,
  138. cache_info.dc_size,
  139. cache_info.it_size);
  140. printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
  141. cache_info.dc_base,
  142. cache_info.dc_stride,
  143. cache_info.dc_count,
  144. cache_info.dc_loop);
  145. printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
  146. *(unsigned long *) (&cache_info.dc_conf),
  147. cache_info.dc_conf.cc_alias,
  148. cache_info.dc_conf.cc_block,
  149. cache_info.dc_conf.cc_line,
  150. cache_info.dc_conf.cc_shift);
  151. printk(" wt %d sh %d cst %d hv %d\n",
  152. cache_info.dc_conf.cc_wt,
  153. cache_info.dc_conf.cc_sh,
  154. cache_info.dc_conf.cc_cst,
  155. cache_info.dc_conf.cc_hv);
  156. printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
  157. cache_info.ic_base,
  158. cache_info.ic_stride,
  159. cache_info.ic_count,
  160. cache_info.ic_loop);
  161. printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
  162. cache_info.it_sp_base,
  163. cache_info.it_sp_stride,
  164. cache_info.it_sp_count,
  165. cache_info.it_loop,
  166. cache_info.it_off_base,
  167. cache_info.it_off_stride,
  168. cache_info.it_off_count);
  169. printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
  170. cache_info.dt_sp_base,
  171. cache_info.dt_sp_stride,
  172. cache_info.dt_sp_count,
  173. cache_info.dt_loop,
  174. cache_info.dt_off_base,
  175. cache_info.dt_off_stride,
  176. cache_info.dt_off_count);
  177. printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
  178. *(unsigned long *) (&cache_info.ic_conf),
  179. cache_info.ic_conf.cc_alias,
  180. cache_info.ic_conf.cc_block,
  181. cache_info.ic_conf.cc_line,
  182. cache_info.ic_conf.cc_shift);
  183. printk(" wt %d sh %d cst %d hv %d\n",
  184. cache_info.ic_conf.cc_wt,
  185. cache_info.ic_conf.cc_sh,
  186. cache_info.ic_conf.cc_cst,
  187. cache_info.ic_conf.cc_hv);
  188. printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
  189. cache_info.dt_conf.tc_sh,
  190. cache_info.dt_conf.tc_page,
  191. cache_info.dt_conf.tc_cst,
  192. cache_info.dt_conf.tc_aid,
  193. cache_info.dt_conf.tc_sr);
  194. printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
  195. cache_info.it_conf.tc_sh,
  196. cache_info.it_conf.tc_page,
  197. cache_info.it_conf.tc_cst,
  198. cache_info.it_conf.tc_aid,
  199. cache_info.it_conf.tc_sr);
  200. #endif
  201. split_tlb = 0;
  202. if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
  203. if (cache_info.dt_conf.tc_sh == 2)
  204. printk(KERN_WARNING "Unexpected TLB configuration. "
  205. "Will flush I/D separately (could be optimized).\n");
  206. split_tlb = 1;
  207. }
  208. /* "New and Improved" version from Jim Hull
  209. * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
  210. * The following CAFL_STRIDE is an optimized version, see
  211. * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
  212. * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
  213. */
  214. #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
  215. dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
  216. icache_stride = CAFL_STRIDE(cache_info.ic_conf);
  217. #undef CAFL_STRIDE
  218. #ifndef CONFIG_PA20
  219. if (pdc_btlb_info(&btlb_info) < 0) {
  220. memset(&btlb_info, 0, sizeof btlb_info);
  221. }
  222. #endif
  223. if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
  224. PDC_MODEL_NVA_UNSUPPORTED) {
  225. printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
  226. #if 0
  227. panic("SMP kernel required to avoid non-equivalent aliasing");
  228. #endif
  229. }
  230. }
  231. void __init disable_sr_hashing(void)
  232. {
  233. int srhash_type, retval;
  234. unsigned long space_bits;
  235. switch (boot_cpu_data.cpu_type) {
  236. case pcx: /* We shouldn't get this far. setup.c should prevent it. */
  237. BUG();
  238. return;
  239. case pcxs:
  240. case pcxt:
  241. case pcxt_:
  242. srhash_type = SRHASH_PCXST;
  243. break;
  244. case pcxl:
  245. srhash_type = SRHASH_PCXL;
  246. break;
  247. case pcxl2: /* pcxl2 doesn't support space register hashing */
  248. return;
  249. default: /* Currently all PA2.0 machines use the same ins. sequence */
  250. srhash_type = SRHASH_PA20;
  251. break;
  252. }
  253. disable_sr_hashing_asm(srhash_type);
  254. retval = pdc_spaceid_bits(&space_bits);
  255. /* If this procedure isn't implemented, don't panic. */
  256. if (retval < 0 && retval != PDC_BAD_OPTION)
  257. panic("pdc_spaceid_bits call failed.\n");
  258. if (space_bits != 0)
  259. panic("SpaceID hashing is still on!\n");
  260. }
  261. static inline void
  262. __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
  263. unsigned long physaddr)
  264. {
  265. preempt_disable();
  266. flush_dcache_page_asm(physaddr, vmaddr);
  267. if (vma->vm_flags & VM_EXEC)
  268. flush_icache_page_asm(physaddr, vmaddr);
  269. preempt_enable();
  270. }
  271. static inline void
  272. __purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
  273. unsigned long physaddr)
  274. {
  275. preempt_disable();
  276. purge_dcache_page_asm(physaddr, vmaddr);
  277. if (vma->vm_flags & VM_EXEC)
  278. flush_icache_page_asm(physaddr, vmaddr);
  279. preempt_enable();
  280. }
  281. void flush_dcache_page(struct page *page)
  282. {
  283. struct address_space *mapping = page_mapping_file(page);
  284. struct vm_area_struct *mpnt;
  285. unsigned long offset;
  286. unsigned long addr, old_addr = 0;
  287. pgoff_t pgoff;
  288. if (mapping && !mapping_mapped(mapping)) {
  289. set_bit(PG_dcache_dirty, &page->flags);
  290. return;
  291. }
  292. flush_kernel_dcache_page(page);
  293. if (!mapping)
  294. return;
  295. pgoff = page->index;
  296. /* We have carefully arranged in arch_get_unmapped_area() that
  297. * *any* mappings of a file are always congruently mapped (whether
  298. * declared as MAP_PRIVATE or MAP_SHARED), so we only need
  299. * to flush one address here for them all to become coherent */
  300. flush_dcache_mmap_lock(mapping);
  301. vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
  302. offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
  303. addr = mpnt->vm_start + offset;
  304. /* The TLB is the engine of coherence on parisc: The
  305. * CPU is entitled to speculate any page with a TLB
  306. * mapping, so here we kill the mapping then flush the
  307. * page along a special flush only alias mapping.
  308. * This guarantees that the page is no-longer in the
  309. * cache for any process and nor may it be
  310. * speculatively read in (until the user or kernel
  311. * specifically accesses it, of course) */
  312. flush_tlb_page(mpnt, addr);
  313. if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
  314. != (addr & (SHM_COLOUR - 1))) {
  315. __flush_cache_page(mpnt, addr, page_to_phys(page));
  316. if (parisc_requires_coherency() && old_addr)
  317. printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
  318. old_addr = addr;
  319. }
  320. }
  321. flush_dcache_mmap_unlock(mapping);
  322. }
  323. EXPORT_SYMBOL(flush_dcache_page);
  324. /* Defined in arch/parisc/kernel/pacache.S */
  325. EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
  326. EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
  327. EXPORT_SYMBOL(flush_data_cache_local);
  328. EXPORT_SYMBOL(flush_kernel_icache_range_asm);
  329. #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
  330. static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
  331. #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
  332. static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
  333. void __init parisc_setup_cache_timing(void)
  334. {
  335. unsigned long rangetime, alltime;
  336. unsigned long size;
  337. unsigned long threshold;
  338. alltime = mfctl(16);
  339. flush_data_cache();
  340. alltime = mfctl(16) - alltime;
  341. size = (unsigned long)(_end - _text);
  342. rangetime = mfctl(16);
  343. flush_kernel_dcache_range((unsigned long)_text, size);
  344. rangetime = mfctl(16) - rangetime;
  345. printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
  346. alltime, size, rangetime);
  347. threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
  348. if (threshold > cache_info.dc_size)
  349. threshold = cache_info.dc_size;
  350. if (threshold)
  351. parisc_cache_flush_threshold = threshold;
  352. printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
  353. parisc_cache_flush_threshold/1024);
  354. /* calculate TLB flush threshold */
  355. /* On SMP machines, skip the TLB measure of kernel text which
  356. * has been mapped as huge pages. */
  357. if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
  358. threshold = max(cache_info.it_size, cache_info.dt_size);
  359. threshold *= PAGE_SIZE;
  360. threshold /= num_online_cpus();
  361. goto set_tlb_threshold;
  362. }
  363. size = (unsigned long)_end - (unsigned long)_text;
  364. rangetime = mfctl(16);
  365. flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
  366. rangetime = mfctl(16) - rangetime;
  367. alltime = mfctl(16);
  368. flush_tlb_all();
  369. alltime = mfctl(16) - alltime;
  370. printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
  371. alltime, size, rangetime);
  372. threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
  373. printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
  374. threshold/1024);
  375. set_tlb_threshold:
  376. if (threshold > FLUSH_TLB_THRESHOLD)
  377. parisc_tlb_flush_threshold = threshold;
  378. else
  379. parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
  380. printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
  381. parisc_tlb_flush_threshold/1024);
  382. }
  383. extern void purge_kernel_dcache_page_asm(unsigned long);
  384. extern void clear_user_page_asm(void *, unsigned long);
  385. extern void copy_user_page_asm(void *, void *, unsigned long);
  386. void flush_kernel_dcache_page_addr(void *addr)
  387. {
  388. unsigned long flags;
  389. flush_kernel_dcache_page_asm(addr);
  390. purge_tlb_start(flags);
  391. pdtlb_kernel(addr);
  392. purge_tlb_end(flags);
  393. }
  394. EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
  395. void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
  396. struct page *pg)
  397. {
  398. /* Copy using kernel mapping. No coherency is needed (all in
  399. kunmap) for the `to' page. However, the `from' page needs to
  400. be flushed through a mapping equivalent to the user mapping
  401. before it can be accessed through the kernel mapping. */
  402. preempt_disable();
  403. flush_dcache_page_asm(__pa(vfrom), vaddr);
  404. copy_page_asm(vto, vfrom);
  405. preempt_enable();
  406. }
  407. EXPORT_SYMBOL(copy_user_page);
  408. /* __flush_tlb_range()
  409. *
  410. * returns 1 if all TLBs were flushed.
  411. */
  412. int __flush_tlb_range(unsigned long sid, unsigned long start,
  413. unsigned long end)
  414. {
  415. unsigned long flags;
  416. if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
  417. end - start >= parisc_tlb_flush_threshold) {
  418. flush_tlb_all();
  419. return 1;
  420. }
  421. /* Purge TLB entries for small ranges using the pdtlb and
  422. pitlb instructions. These instructions execute locally
  423. but cause a purge request to be broadcast to other TLBs. */
  424. while (start < end) {
  425. purge_tlb_start(flags);
  426. mtsp(sid, 1);
  427. pdtlb(start);
  428. pitlb(start);
  429. purge_tlb_end(flags);
  430. start += PAGE_SIZE;
  431. }
  432. return 0;
  433. }
  434. static void cacheflush_h_tmp_function(void *dummy)
  435. {
  436. flush_cache_all_local();
  437. }
  438. void flush_cache_all(void)
  439. {
  440. on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
  441. }
  442. static inline unsigned long mm_total_size(struct mm_struct *mm)
  443. {
  444. struct vm_area_struct *vma;
  445. unsigned long usize = 0;
  446. for (vma = mm->mmap; vma; vma = vma->vm_next)
  447. usize += vma->vm_end - vma->vm_start;
  448. return usize;
  449. }
  450. static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
  451. {
  452. pte_t *ptep = NULL;
  453. if (!pgd_none(*pgd)) {
  454. p4d_t *p4d = p4d_offset(pgd, addr);
  455. if (!p4d_none(*p4d)) {
  456. pud_t *pud = pud_offset(p4d, addr);
  457. if (!pud_none(*pud)) {
  458. pmd_t *pmd = pmd_offset(pud, addr);
  459. if (!pmd_none(*pmd))
  460. ptep = pte_offset_map(pmd, addr);
  461. }
  462. }
  463. }
  464. return ptep;
  465. }
  466. void flush_cache_mm(struct mm_struct *mm)
  467. {
  468. struct vm_area_struct *vma;
  469. pgd_t *pgd;
  470. /* Flushing the whole cache on each cpu takes forever on
  471. rp3440, etc. So, avoid it if the mm isn't too big. */
  472. if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
  473. mm_total_size(mm) >= parisc_cache_flush_threshold) {
  474. if (mm->context)
  475. flush_tlb_all();
  476. flush_cache_all();
  477. return;
  478. }
  479. if (mm->context == mfsp(3)) {
  480. for (vma = mm->mmap; vma; vma = vma->vm_next) {
  481. flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
  482. if (vma->vm_flags & VM_EXEC)
  483. flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
  484. flush_tlb_range(vma, vma->vm_start, vma->vm_end);
  485. }
  486. return;
  487. }
  488. pgd = mm->pgd;
  489. for (vma = mm->mmap; vma; vma = vma->vm_next) {
  490. unsigned long addr;
  491. for (addr = vma->vm_start; addr < vma->vm_end;
  492. addr += PAGE_SIZE) {
  493. unsigned long pfn;
  494. pte_t *ptep = get_ptep(pgd, addr);
  495. if (!ptep)
  496. continue;
  497. pfn = pte_pfn(*ptep);
  498. if (!pfn_valid(pfn))
  499. continue;
  500. if (unlikely(mm->context)) {
  501. flush_tlb_page(vma, addr);
  502. __flush_cache_page(vma, addr, PFN_PHYS(pfn));
  503. } else {
  504. __purge_cache_page(vma, addr, PFN_PHYS(pfn));
  505. }
  506. }
  507. }
  508. }
  509. void flush_cache_range(struct vm_area_struct *vma,
  510. unsigned long start, unsigned long end)
  511. {
  512. pgd_t *pgd;
  513. unsigned long addr;
  514. if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
  515. end - start >= parisc_cache_flush_threshold) {
  516. if (vma->vm_mm->context)
  517. flush_tlb_range(vma, start, end);
  518. flush_cache_all();
  519. return;
  520. }
  521. if (vma->vm_mm->context == mfsp(3)) {
  522. flush_user_dcache_range_asm(start, end);
  523. if (vma->vm_flags & VM_EXEC)
  524. flush_user_icache_range_asm(start, end);
  525. flush_tlb_range(vma, start, end);
  526. return;
  527. }
  528. pgd = vma->vm_mm->pgd;
  529. for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
  530. unsigned long pfn;
  531. pte_t *ptep = get_ptep(pgd, addr);
  532. if (!ptep)
  533. continue;
  534. pfn = pte_pfn(*ptep);
  535. if (pfn_valid(pfn)) {
  536. if (unlikely(vma->vm_mm->context)) {
  537. flush_tlb_page(vma, addr);
  538. __flush_cache_page(vma, addr, PFN_PHYS(pfn));
  539. } else {
  540. __purge_cache_page(vma, addr, PFN_PHYS(pfn));
  541. }
  542. }
  543. }
  544. }
  545. void
  546. flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
  547. {
  548. if (pfn_valid(pfn)) {
  549. if (likely(vma->vm_mm->context)) {
  550. flush_tlb_page(vma, vmaddr);
  551. __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
  552. } else {
  553. __purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
  554. }
  555. }
  556. }
  557. void flush_kernel_vmap_range(void *vaddr, int size)
  558. {
  559. unsigned long start = (unsigned long)vaddr;
  560. unsigned long end = start + size;
  561. if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
  562. (unsigned long)size >= parisc_cache_flush_threshold) {
  563. flush_tlb_kernel_range(start, end);
  564. flush_data_cache();
  565. return;
  566. }
  567. flush_kernel_dcache_range_asm(start, end);
  568. flush_tlb_kernel_range(start, end);
  569. }
  570. EXPORT_SYMBOL(flush_kernel_vmap_range);
  571. void invalidate_kernel_vmap_range(void *vaddr, int size)
  572. {
  573. unsigned long start = (unsigned long)vaddr;
  574. unsigned long end = start + size;
  575. if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
  576. (unsigned long)size >= parisc_cache_flush_threshold) {
  577. flush_tlb_kernel_range(start, end);
  578. flush_data_cache();
  579. return;
  580. }
  581. purge_kernel_dcache_range_asm(start, end);
  582. flush_tlb_kernel_range(start, end);
  583. }
  584. EXPORT_SYMBOL(invalidate_kernel_vmap_range);