tlb.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * OpenRISC tlb.c
  4. *
  5. * Linux architectural port borrowing liberally from similar works of
  6. * others. All original copyrights apply as per the original source
  7. * declaration.
  8. *
  9. * Modifications for the OpenRISC architecture:
  10. * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  11. * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
  12. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  13. */
  14. #include <linux/sched.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/string.h>
  18. #include <linux/types.h>
  19. #include <linux/ptrace.h>
  20. #include <linux/mman.h>
  21. #include <linux/mm.h>
  22. #include <linux/init.h>
  23. #include <asm/tlbflush.h>
  24. #include <asm/mmu_context.h>
  25. #include <asm/spr_defs.h>
  26. #define NO_CONTEXT -1
  27. #define NUM_DTLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \
  28. SPR_DMMUCFGR_NTS_OFF))
  29. #define NUM_ITLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \
  30. SPR_IMMUCFGR_NTS_OFF))
  31. #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
  32. #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
  33. /*
  34. * Invalidate all TLB entries.
  35. *
  36. * This comes down to setting the 'valid' bit for all xTLBMR registers to 0.
  37. * Easiest way to accomplish this is to just zero out the xTLBMR register
  38. * completely.
  39. *
  40. */
  41. void local_flush_tlb_all(void)
  42. {
  43. int i;
  44. unsigned long num_tlb_sets;
  45. /* Determine number of sets for IMMU. */
  46. /* FIXME: Assumption is I & D nsets equal. */
  47. num_tlb_sets = NUM_ITLB_SETS;
  48. for (i = 0; i < num_tlb_sets; i++) {
  49. mtspr_off(SPR_DTLBMR_BASE(0), i, 0);
  50. mtspr_off(SPR_ITLBMR_BASE(0), i, 0);
  51. }
  52. }
  53. #define have_dtlbeir (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_TEIRI)
  54. #define have_itlbeir (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_TEIRI)
  55. /*
  56. * Invalidate a single page. This is what the xTLBEIR register is for.
  57. *
  58. * There's no point in checking the vma for PAGE_EXEC to determine whether it's
  59. * the data or instruction TLB that should be flushed... that would take more
  60. * than the few instructions that the following compiles down to!
  61. *
  62. * The case where we don't have the xTLBEIR register really only works for
  63. * MMU's with a single way and is hard-coded that way.
  64. */
  65. #define flush_dtlb_page_eir(addr) mtspr(SPR_DTLBEIR, addr)
  66. #define flush_dtlb_page_no_eir(addr) \
  67. mtspr_off(SPR_DTLBMR_BASE(0), DTLB_OFFSET(addr), 0);
  68. #define flush_itlb_page_eir(addr) mtspr(SPR_ITLBEIR, addr)
  69. #define flush_itlb_page_no_eir(addr) \
  70. mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0);
  71. void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
  72. {
  73. if (have_dtlbeir)
  74. flush_dtlb_page_eir(addr);
  75. else
  76. flush_dtlb_page_no_eir(addr);
  77. if (have_itlbeir)
  78. flush_itlb_page_eir(addr);
  79. else
  80. flush_itlb_page_no_eir(addr);
  81. }
  82. void local_flush_tlb_range(struct vm_area_struct *vma,
  83. unsigned long start, unsigned long end)
  84. {
  85. int addr;
  86. bool dtlbeir;
  87. bool itlbeir;
  88. dtlbeir = have_dtlbeir;
  89. itlbeir = have_itlbeir;
  90. for (addr = start; addr < end; addr += PAGE_SIZE) {
  91. if (dtlbeir)
  92. flush_dtlb_page_eir(addr);
  93. else
  94. flush_dtlb_page_no_eir(addr);
  95. if (itlbeir)
  96. flush_itlb_page_eir(addr);
  97. else
  98. flush_itlb_page_no_eir(addr);
  99. }
  100. }
  101. /*
  102. * Invalidate the selected mm context only.
  103. *
  104. * FIXME: Due to some bug here, we're flushing everything for now.
  105. * This should be changed to loop over over mm and call flush_tlb_range.
  106. */
  107. void local_flush_tlb_mm(struct mm_struct *mm)
  108. {
  109. /* Was seeing bugs with the mm struct passed to us. Scrapped most of
  110. this function. */
  111. /* Several architctures do this */
  112. local_flush_tlb_all();
  113. }
  114. /* called in schedule() just before actually doing the switch_to */
  115. void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  116. struct task_struct *next_tsk)
  117. {
  118. unsigned int cpu;
  119. if (unlikely(prev == next))
  120. return;
  121. cpu = smp_processor_id();
  122. cpumask_clear_cpu(cpu, mm_cpumask(prev));
  123. cpumask_set_cpu(cpu, mm_cpumask(next));
  124. /* remember the pgd for the fault handlers
  125. * this is similar to the pgd register in some other CPU's.
  126. * we need our own copy of it because current and active_mm
  127. * might be invalid at points where we still need to derefer
  128. * the pgd.
  129. */
  130. current_pgd[cpu] = next->pgd;
  131. /* We don't have context support implemented, so flush all
  132. * entries belonging to previous map
  133. */
  134. local_flush_tlb_mm(prev);
  135. }
  136. /*
  137. * Initialize the context related info for a new mm_struct
  138. * instance.
  139. */
  140. int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
  141. {
  142. mm->context = NO_CONTEXT;
  143. return 0;
  144. }
  145. /* called by __exit_mm to destroy the used MMU context if any before
  146. * destroying the mm itself. this is only called when the last user of the mm
  147. * drops it.
  148. */
  149. void destroy_context(struct mm_struct *mm)
  150. {
  151. flush_tlb_mm(mm);
  152. }
  153. /* called once during VM initialization, from init.c */
  154. void __init tlb_init(void)
  155. {
  156. /* Do nothing... */
  157. /* invalidate the entire TLB */
  158. /* flush_tlb_all(); */
  159. }