time.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * OpenRISC time.c
  4. *
  5. * Linux architectural port borrowing liberally from similar works of
  6. * others. All original copyrights apply as per the original source
  7. * declaration.
  8. *
  9. * Modifications for the OpenRISC architecture:
  10. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/time.h>
  14. #include <linux/timex.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/ftrace.h>
  17. #include <linux/clocksource.h>
  18. #include <linux/clockchips.h>
  19. #include <linux/irq.h>
  20. #include <linux/io.h>
  21. #include <asm/cpuinfo.h>
  22. /* Test the timer ticks to count, used in sync routine */
  23. inline void openrisc_timer_set(unsigned long count)
  24. {
  25. mtspr(SPR_TTCR, count);
  26. }
  27. /* Set the timer to trigger in delta cycles */
  28. inline void openrisc_timer_set_next(unsigned long delta)
  29. {
  30. u32 c;
  31. /* Read 32-bit counter value, add delta, mask off the low 28 bits.
  32. * We're guaranteed delta won't be bigger than 28 bits because the
  33. * generic timekeeping code ensures that for us.
  34. */
  35. c = mfspr(SPR_TTCR);
  36. c += delta;
  37. c &= SPR_TTMR_TP;
  38. /* Set counter and enable interrupt.
  39. * Keep timer in continuous mode always.
  40. */
  41. mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
  42. }
  43. static int openrisc_timer_set_next_event(unsigned long delta,
  44. struct clock_event_device *dev)
  45. {
  46. openrisc_timer_set_next(delta);
  47. return 0;
  48. }
  49. /* This is the clock event device based on the OR1K tick timer.
  50. * As the timer is being used as a continuous clock-source (required for HR
  51. * timers) we cannot enable the PERIODIC feature. The tick timer can run using
  52. * one-shot events, so no problem.
  53. */
  54. DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
  55. void openrisc_clockevent_init(void)
  56. {
  57. unsigned int cpu = smp_processor_id();
  58. struct clock_event_device *evt =
  59. &per_cpu(clockevent_openrisc_timer, cpu);
  60. struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
  61. mtspr(SPR_TTMR, SPR_TTMR_CR);
  62. #ifdef CONFIG_SMP
  63. evt->broadcast = tick_broadcast;
  64. #endif
  65. evt->name = "openrisc_timer_clockevent",
  66. evt->features = CLOCK_EVT_FEAT_ONESHOT,
  67. evt->rating = 300,
  68. evt->set_next_event = openrisc_timer_set_next_event,
  69. evt->cpumask = cpumask_of(cpu);
  70. /* We only have 28 bits */
  71. clockevents_config_and_register(evt, cpuinfo->clock_frequency,
  72. 100, 0x0fffffff);
  73. }
  74. static inline void timer_ack(void)
  75. {
  76. /* Clear the IP bit and disable further interrupts */
  77. /* This can be done very simply... we just need to keep the timer
  78. running, so just maintain the CR bits while clearing the rest
  79. of the register
  80. */
  81. mtspr(SPR_TTMR, SPR_TTMR_CR);
  82. }
  83. /*
  84. * The timer interrupt is mostly handled in generic code nowadays... this
  85. * function just acknowledges the interrupt and fires the event handler that
  86. * has been set on the clockevent device by the generic time management code.
  87. *
  88. * This function needs to be called by the timer exception handler and that's
  89. * all the exception handler needs to do.
  90. */
  91. irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
  92. {
  93. struct pt_regs *old_regs = set_irq_regs(regs);
  94. unsigned int cpu = smp_processor_id();
  95. struct clock_event_device *evt =
  96. &per_cpu(clockevent_openrisc_timer, cpu);
  97. timer_ack();
  98. /*
  99. * update_process_times() expects us to have called irq_enter().
  100. */
  101. irq_enter();
  102. evt->event_handler(evt);
  103. irq_exit();
  104. set_irq_regs(old_regs);
  105. return IRQ_HANDLED;
  106. }
  107. /**
  108. * Clocksource: Based on OpenRISC timer/counter
  109. *
  110. * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
  111. * is 32 bits wide and runs at the CPU clock frequency.
  112. */
  113. static u64 openrisc_timer_read(struct clocksource *cs)
  114. {
  115. return (u64) mfspr(SPR_TTCR);
  116. }
  117. static struct clocksource openrisc_timer = {
  118. .name = "openrisc_timer",
  119. .rating = 200,
  120. .read = openrisc_timer_read,
  121. .mask = CLOCKSOURCE_MASK(32),
  122. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  123. };
  124. static int __init openrisc_timer_init(void)
  125. {
  126. struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
  127. if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
  128. panic("failed to register clocksource");
  129. /* Enable the incrementer: 'continuous' mode with interrupt disabled */
  130. mtspr(SPR_TTMR, SPR_TTMR_CR);
  131. return 0;
  132. }
  133. void __init time_init(void)
  134. {
  135. u32 upr;
  136. upr = mfspr(SPR_UPR);
  137. if (!(upr & SPR_UPR_TTP))
  138. panic("Linux not supported on devices without tick timer");
  139. openrisc_timer_init();
  140. openrisc_clockevent_init();
  141. }