sync-timer.c 2.9 KB

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  1. /*
  2. * OR1K timer synchronisation
  3. *
  4. * Based on work from MIPS implementation.
  5. *
  6. * All CPUs will have their count registers synchronised to the CPU0 next time
  7. * value. This can cause a small timewarp for CPU0. All other CPU's should
  8. * not have done anything significant (but they may have had interrupts
  9. * enabled briefly - prom_smp_finish() should not be responsible for enabling
  10. * interrupts...)
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/irqflags.h>
  14. #include <linux/cpumask.h>
  15. #include <asm/time.h>
  16. #include <asm/timex.h>
  17. #include <linux/atomic.h>
  18. #include <asm/barrier.h>
  19. #include <asm/spr.h>
  20. static unsigned int initcount;
  21. static atomic_t count_count_start = ATOMIC_INIT(0);
  22. static atomic_t count_count_stop = ATOMIC_INIT(0);
  23. #define COUNTON 100
  24. #define NR_LOOPS 3
  25. void synchronise_count_master(int cpu)
  26. {
  27. int i;
  28. unsigned long flags;
  29. pr_info("Synchronize counters for CPU %u: ", cpu);
  30. local_irq_save(flags);
  31. /*
  32. * We loop a few times to get a primed instruction cache,
  33. * then the last pass is more or less synchronised and
  34. * the master and slaves each set their cycle counters to a known
  35. * value all at once. This reduces the chance of having random offsets
  36. * between the processors, and guarantees that the maximum
  37. * delay between the cycle counters is never bigger than
  38. * the latency of information-passing (cachelines) between
  39. * two CPUs.
  40. */
  41. for (i = 0; i < NR_LOOPS; i++) {
  42. /* slaves loop on '!= 2' */
  43. while (atomic_read(&count_count_start) != 1)
  44. mb();
  45. atomic_set(&count_count_stop, 0);
  46. smp_wmb();
  47. /* Let the slave writes its count register */
  48. atomic_inc(&count_count_start);
  49. /* Count will be initialised to current timer */
  50. if (i == 1)
  51. initcount = get_cycles();
  52. /*
  53. * Everyone initialises count in the last loop:
  54. */
  55. if (i == NR_LOOPS-1)
  56. openrisc_timer_set(initcount);
  57. /*
  58. * Wait for slave to leave the synchronization point:
  59. */
  60. while (atomic_read(&count_count_stop) != 1)
  61. mb();
  62. atomic_set(&count_count_start, 0);
  63. smp_wmb();
  64. atomic_inc(&count_count_stop);
  65. }
  66. /* Arrange for an interrupt in a short while */
  67. openrisc_timer_set_next(COUNTON);
  68. local_irq_restore(flags);
  69. /*
  70. * i386 code reported the skew here, but the
  71. * count registers were almost certainly out of sync
  72. * so no point in alarming people
  73. */
  74. pr_cont("done.\n");
  75. }
  76. void synchronise_count_slave(int cpu)
  77. {
  78. int i;
  79. /*
  80. * Not every cpu is online at the time this gets called,
  81. * so we first wait for the master to say everyone is ready
  82. */
  83. for (i = 0; i < NR_LOOPS; i++) {
  84. atomic_inc(&count_count_start);
  85. while (atomic_read(&count_count_start) != 2)
  86. mb();
  87. /*
  88. * Everyone initialises count in the last loop:
  89. */
  90. if (i == NR_LOOPS-1)
  91. openrisc_timer_set(initcount);
  92. atomic_inc(&count_count_stop);
  93. while (atomic_read(&count_count_stop) != 2)
  94. mb();
  95. }
  96. /* Arrange for an interrupt in a short while */
  97. openrisc_timer_set_next(COUNTON);
  98. }
  99. #undef NR_LOOPS