setup.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * OpenRISC setup.c
  4. *
  5. * Linux architectural port borrowing liberally from similar works of
  6. * others. All original copyrights apply as per the original source
  7. * declaration.
  8. *
  9. * Modifications for the OpenRISC architecture:
  10. * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  11. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  12. *
  13. * This file handles the architecture-dependent parts of initialization
  14. */
  15. #include <linux/errno.h>
  16. #include <linux/sched.h>
  17. #include <linux/kernel.h>
  18. #include <linux/mm.h>
  19. #include <linux/stddef.h>
  20. #include <linux/unistd.h>
  21. #include <linux/ptrace.h>
  22. #include <linux/slab.h>
  23. #include <linux/tty.h>
  24. #include <linux/ioport.h>
  25. #include <linux/delay.h>
  26. #include <linux/console.h>
  27. #include <linux/init.h>
  28. #include <linux/memblock.h>
  29. #include <linux/seq_file.h>
  30. #include <linux/serial.h>
  31. #include <linux/initrd.h>
  32. #include <linux/of_fdt.h>
  33. #include <linux/of.h>
  34. #include <linux/device.h>
  35. #include <asm/sections.h>
  36. #include <asm/types.h>
  37. #include <asm/setup.h>
  38. #include <asm/io.h>
  39. #include <asm/cpuinfo.h>
  40. #include <asm/delay.h>
  41. #include "vmlinux.h"
  42. static void __init setup_memory(void)
  43. {
  44. unsigned long ram_start_pfn;
  45. unsigned long ram_end_pfn;
  46. phys_addr_t memory_start, memory_end;
  47. memory_end = memory_start = 0;
  48. /* Find main memory where is the kernel, we assume its the only one */
  49. memory_start = memblock_start_of_DRAM();
  50. memory_end = memblock_end_of_DRAM();
  51. if (!memory_end) {
  52. panic("No memory!");
  53. }
  54. ram_start_pfn = PFN_UP(memory_start);
  55. ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
  56. /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
  57. min_low_pfn = ram_start_pfn;
  58. max_low_pfn = ram_end_pfn;
  59. max_pfn = ram_end_pfn;
  60. /*
  61. * initialize the boot-time allocator (with low memory only).
  62. *
  63. * This makes the memory from the end of the kernel to the end of
  64. * RAM usable.
  65. */
  66. memblock_reserve(__pa(_stext), _end - _stext);
  67. #ifdef CONFIG_BLK_DEV_INITRD
  68. /* Then reserve the initrd, if any */
  69. if (initrd_start && (initrd_end > initrd_start)) {
  70. unsigned long aligned_start = ALIGN_DOWN(initrd_start, PAGE_SIZE);
  71. unsigned long aligned_end = ALIGN(initrd_end, PAGE_SIZE);
  72. memblock_reserve(__pa(aligned_start), aligned_end - aligned_start);
  73. }
  74. #endif /* CONFIG_BLK_DEV_INITRD */
  75. early_init_fdt_reserve_self();
  76. early_init_fdt_scan_reserved_mem();
  77. memblock_dump_all();
  78. }
  79. struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
  80. static void print_cpuinfo(void)
  81. {
  82. unsigned long upr = mfspr(SPR_UPR);
  83. unsigned long vr = mfspr(SPR_VR);
  84. unsigned int version;
  85. unsigned int revision;
  86. struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
  87. version = (vr & SPR_VR_VER) >> 24;
  88. revision = (vr & SPR_VR_REV);
  89. printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
  90. version, revision, cpuinfo->clock_frequency / 1000000);
  91. if (!(upr & SPR_UPR_UP)) {
  92. printk(KERN_INFO
  93. "-- no UPR register... unable to detect configuration\n");
  94. return;
  95. }
  96. if (upr & SPR_UPR_DCP)
  97. printk(KERN_INFO
  98. "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
  99. cpuinfo->dcache_size, cpuinfo->dcache_block_size,
  100. cpuinfo->dcache_ways);
  101. else
  102. printk(KERN_INFO "-- dcache disabled\n");
  103. if (upr & SPR_UPR_ICP)
  104. printk(KERN_INFO
  105. "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
  106. cpuinfo->icache_size, cpuinfo->icache_block_size,
  107. cpuinfo->icache_ways);
  108. else
  109. printk(KERN_INFO "-- icache disabled\n");
  110. if (upr & SPR_UPR_DMP)
  111. printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
  112. 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
  113. 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
  114. if (upr & SPR_UPR_IMP)
  115. printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
  116. 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
  117. 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
  118. printk(KERN_INFO "-- additional features:\n");
  119. if (upr & SPR_UPR_DUP)
  120. printk(KERN_INFO "-- debug unit\n");
  121. if (upr & SPR_UPR_PCUP)
  122. printk(KERN_INFO "-- performance counters\n");
  123. if (upr & SPR_UPR_PMP)
  124. printk(KERN_INFO "-- power management\n");
  125. if (upr & SPR_UPR_PICP)
  126. printk(KERN_INFO "-- PIC\n");
  127. if (upr & SPR_UPR_TTP)
  128. printk(KERN_INFO "-- timer\n");
  129. if (upr & SPR_UPR_CUP)
  130. printk(KERN_INFO "-- custom unit(s)\n");
  131. }
  132. static struct device_node *setup_find_cpu_node(int cpu)
  133. {
  134. u32 hwid;
  135. struct device_node *cpun;
  136. for_each_of_cpu_node(cpun) {
  137. if (of_property_read_u32(cpun, "reg", &hwid))
  138. continue;
  139. if (hwid == cpu)
  140. return cpun;
  141. }
  142. return NULL;
  143. }
  144. void __init setup_cpuinfo(void)
  145. {
  146. struct device_node *cpu;
  147. unsigned long iccfgr, dccfgr;
  148. unsigned long cache_set_size;
  149. int cpu_id = smp_processor_id();
  150. struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
  151. cpu = setup_find_cpu_node(cpu_id);
  152. if (!cpu)
  153. panic("Couldn't find CPU%d in device tree...\n", cpu_id);
  154. iccfgr = mfspr(SPR_ICCFGR);
  155. cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
  156. cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
  157. cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
  158. cpuinfo->icache_size =
  159. cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
  160. dccfgr = mfspr(SPR_DCCFGR);
  161. cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
  162. cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
  163. cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
  164. cpuinfo->dcache_size =
  165. cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
  166. if (of_property_read_u32(cpu, "clock-frequency",
  167. &cpuinfo->clock_frequency)) {
  168. printk(KERN_WARNING
  169. "Device tree missing CPU 'clock-frequency' parameter."
  170. "Assuming frequency 25MHZ"
  171. "This is probably not what you want.");
  172. }
  173. cpuinfo->coreid = mfspr(SPR_COREID);
  174. of_node_put(cpu);
  175. print_cpuinfo();
  176. }
  177. /**
  178. * or32_early_setup
  179. *
  180. * Handles the pointer to the device tree that this kernel is to use
  181. * for establishing the available platform devices.
  182. *
  183. * Falls back on built-in device tree in case null pointer is passed.
  184. */
  185. void __init or32_early_setup(void *fdt)
  186. {
  187. if (fdt)
  188. pr_info("FDT at %p\n", fdt);
  189. else {
  190. fdt = __dtb_start;
  191. pr_info("Compiled-in FDT at %p\n", fdt);
  192. }
  193. early_init_devtree(fdt);
  194. }
  195. static inline unsigned long extract_value_bits(unsigned long reg,
  196. short bit_nr, short width)
  197. {
  198. return (reg >> bit_nr) & (0 << width);
  199. }
  200. static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
  201. {
  202. while (!(mask & 0x1)) {
  203. reg = reg >> 1;
  204. mask = mask >> 1;
  205. }
  206. return mask & reg;
  207. }
  208. void __init detect_unit_config(unsigned long upr, unsigned long mask,
  209. char *text, void (*func) (void))
  210. {
  211. if (text != NULL)
  212. printk("%s", text);
  213. if (upr & mask) {
  214. if (func != NULL)
  215. func();
  216. else
  217. printk("present\n");
  218. } else
  219. printk("not present\n");
  220. }
  221. /*
  222. * calibrate_delay
  223. *
  224. * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
  225. * from the clock frequency passed in via the device tree
  226. *
  227. */
  228. void calibrate_delay(void)
  229. {
  230. const int *val;
  231. struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
  232. val = of_get_property(cpu, "clock-frequency", NULL);
  233. if (!val)
  234. panic("no cpu 'clock-frequency' parameter in device tree");
  235. loops_per_jiffy = *val / HZ;
  236. pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
  237. loops_per_jiffy / (500000 / HZ),
  238. (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
  239. of_node_put(cpu);
  240. }
  241. void __init setup_arch(char **cmdline_p)
  242. {
  243. unflatten_and_copy_device_tree();
  244. setup_cpuinfo();
  245. #ifdef CONFIG_SMP
  246. smp_init_cpus();
  247. #endif
  248. /* process 1's initial memory region is the kernel code/data */
  249. init_mm.start_code = (unsigned long)_stext;
  250. init_mm.end_code = (unsigned long)_etext;
  251. init_mm.end_data = (unsigned long)_edata;
  252. init_mm.brk = (unsigned long)_end;
  253. #ifdef CONFIG_BLK_DEV_INITRD
  254. if (initrd_start == initrd_end) {
  255. printk(KERN_INFO "Initial ramdisk not found\n");
  256. initrd_start = 0;
  257. initrd_end = 0;
  258. } else {
  259. printk(KERN_INFO "Initial ramdisk at: 0x%p (%lu bytes)\n",
  260. (void *)(initrd_start), initrd_end - initrd_start);
  261. initrd_below_start_ok = 1;
  262. }
  263. #endif
  264. /* setup memblock allocator */
  265. setup_memory();
  266. /* paging_init() sets up the MMU and marks all pages as reserved */
  267. paging_init();
  268. *cmdline_p = boot_command_line;
  269. printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
  270. }
  271. static int show_cpuinfo(struct seq_file *m, void *v)
  272. {
  273. unsigned int vr, cpucfgr;
  274. unsigned int avr;
  275. unsigned int version;
  276. struct cpuinfo_or1k *cpuinfo = v;
  277. vr = mfspr(SPR_VR);
  278. cpucfgr = mfspr(SPR_CPUCFGR);
  279. #ifdef CONFIG_SMP
  280. seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
  281. #endif
  282. if (vr & SPR_VR_UVRP) {
  283. vr = mfspr(SPR_VR2);
  284. version = vr & SPR_VR2_VER;
  285. avr = mfspr(SPR_AVR);
  286. seq_printf(m, "cpu architecture\t: "
  287. "OpenRISC 1000 (%d.%d-rev%d)\n",
  288. (avr >> 24) & 0xff,
  289. (avr >> 16) & 0xff,
  290. (avr >> 8) & 0xff);
  291. seq_printf(m, "cpu implementation id\t: 0x%x\n",
  292. (vr & SPR_VR2_CPUID) >> 24);
  293. seq_printf(m, "cpu version\t\t: 0x%x\n", version);
  294. } else {
  295. version = (vr & SPR_VR_VER) >> 24;
  296. seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
  297. seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
  298. }
  299. seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
  300. seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
  301. seq_printf(m, "dcache block size\t: %d bytes\n",
  302. cpuinfo->dcache_block_size);
  303. seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
  304. seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
  305. seq_printf(m, "icache block size\t: %d bytes\n",
  306. cpuinfo->icache_block_size);
  307. seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
  308. seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
  309. 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
  310. 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
  311. seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
  312. 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
  313. 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
  314. seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
  315. (loops_per_jiffy * HZ) / 500000,
  316. ((loops_per_jiffy * HZ) / 5000) % 100);
  317. seq_puts(m, "features\t\t: ");
  318. seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
  319. seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
  320. seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
  321. seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
  322. seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
  323. seq_puts(m, "\n");
  324. seq_puts(m, "\n");
  325. return 0;
  326. }
  327. static void *c_start(struct seq_file *m, loff_t *pos)
  328. {
  329. *pos = cpumask_next(*pos - 1, cpu_online_mask);
  330. if ((*pos) < nr_cpu_ids)
  331. return &cpuinfo_or1k[*pos];
  332. return NULL;
  333. }
  334. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  335. {
  336. (*pos)++;
  337. return c_start(m, pos);
  338. }
  339. static void c_stop(struct seq_file *m, void *v)
  340. {
  341. }
  342. const struct seq_operations cpuinfo_op = {
  343. .start = c_start,
  344. .next = c_next,
  345. .stop = c_stop,
  346. .show = show_cpuinfo,
  347. };