entry.S 33 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * OpenRISC entry.S
  4. *
  5. * Linux architectural port borrowing liberally from similar works of
  6. * others. All original copyrights apply as per the original source
  7. * declaration.
  8. *
  9. * Modifications for the OpenRISC architecture:
  10. * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  11. * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
  12. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/processor.h>
  17. #include <asm/unistd.h>
  18. #include <asm/thread_info.h>
  19. #include <asm/errno.h>
  20. #include <asm/spr_defs.h>
  21. #include <asm/page.h>
  22. #include <asm/mmu.h>
  23. #include <asm/asm-offsets.h>
  24. #define DISABLE_INTERRUPTS(t1,t2) \
  25. l.mfspr t2,r0,SPR_SR ;\
  26. l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
  27. l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
  28. l.and t2,t2,t1 ;\
  29. l.mtspr r0,t2,SPR_SR
  30. #define ENABLE_INTERRUPTS(t1) \
  31. l.mfspr t1,r0,SPR_SR ;\
  32. l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
  33. l.mtspr r0,t1,SPR_SR
  34. /* =========================================================[ macros ]=== */
  35. #ifdef CONFIG_TRACE_IRQFLAGS
  36. /*
  37. * Trace irq on/off creating a stack frame.
  38. */
  39. #define TRACE_IRQS_OP(trace_op) \
  40. l.sw -8(r1),r2 /* store frame pointer */ ;\
  41. l.sw -4(r1),r9 /* store return address */ ;\
  42. l.addi r2,r1,0 /* move sp to fp */ ;\
  43. l.jal trace_op ;\
  44. l.addi r1,r1,-8 ;\
  45. l.ori r1,r2,0 /* restore sp */ ;\
  46. l.lwz r9,-4(r1) /* restore return address */ ;\
  47. l.lwz r2,-8(r1) /* restore fp */ ;\
  48. /*
  49. * Trace irq on/off and save registers we need that would otherwise be
  50. * clobbered.
  51. */
  52. #define TRACE_IRQS_SAVE(t1,trace_op) \
  53. l.sw -12(r1),t1 /* save extra reg */ ;\
  54. l.sw -8(r1),r2 /* store frame pointer */ ;\
  55. l.sw -4(r1),r9 /* store return address */ ;\
  56. l.addi r2,r1,0 /* move sp to fp */ ;\
  57. l.jal trace_op ;\
  58. l.addi r1,r1,-12 ;\
  59. l.ori r1,r2,0 /* restore sp */ ;\
  60. l.lwz r9,-4(r1) /* restore return address */ ;\
  61. l.lwz r2,-8(r1) /* restore fp */ ;\
  62. l.lwz t1,-12(r1) /* restore extra reg */
  63. #define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
  64. #define TRACE_IRQS_ON TRACE_IRQS_OP(trace_hardirqs_on)
  65. #define TRACE_IRQS_ON_SYSCALL \
  66. TRACE_IRQS_SAVE(r10,trace_hardirqs_on) ;\
  67. l.lwz r3,PT_GPR3(r1) ;\
  68. l.lwz r4,PT_GPR4(r1) ;\
  69. l.lwz r5,PT_GPR5(r1) ;\
  70. l.lwz r6,PT_GPR6(r1) ;\
  71. l.lwz r7,PT_GPR7(r1) ;\
  72. l.lwz r8,PT_GPR8(r1) ;\
  73. l.lwz r11,PT_GPR11(r1)
  74. #define TRACE_IRQS_OFF_ENTRY \
  75. l.lwz r5,PT_SR(r1) ;\
  76. l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
  77. l.sfeq r5,r0 /* skip trace if irqs were already off */;\
  78. l.bf 1f ;\
  79. l.nop ;\
  80. TRACE_IRQS_SAVE(r4,trace_hardirqs_off) ;\
  81. 1:
  82. #else
  83. #define TRACE_IRQS_OFF
  84. #define TRACE_IRQS_ON
  85. #define TRACE_IRQS_OFF_ENTRY
  86. #define TRACE_IRQS_ON_SYSCALL
  87. #endif
  88. /*
  89. * We need to disable interrupts at beginning of RESTORE_ALL
  90. * since interrupt might come in after we've loaded EPC return address
  91. * and overwrite EPC with address somewhere in RESTORE_ALL
  92. * which is of course wrong!
  93. */
  94. #define RESTORE_ALL \
  95. DISABLE_INTERRUPTS(r3,r4) ;\
  96. l.lwz r3,PT_PC(r1) ;\
  97. l.mtspr r0,r3,SPR_EPCR_BASE ;\
  98. l.lwz r3,PT_SR(r1) ;\
  99. l.mtspr r0,r3,SPR_ESR_BASE ;\
  100. l.lwz r2,PT_GPR2(r1) ;\
  101. l.lwz r3,PT_GPR3(r1) ;\
  102. l.lwz r4,PT_GPR4(r1) ;\
  103. l.lwz r5,PT_GPR5(r1) ;\
  104. l.lwz r6,PT_GPR6(r1) ;\
  105. l.lwz r7,PT_GPR7(r1) ;\
  106. l.lwz r8,PT_GPR8(r1) ;\
  107. l.lwz r9,PT_GPR9(r1) ;\
  108. l.lwz r10,PT_GPR10(r1) ;\
  109. l.lwz r11,PT_GPR11(r1) ;\
  110. l.lwz r12,PT_GPR12(r1) ;\
  111. l.lwz r13,PT_GPR13(r1) ;\
  112. l.lwz r14,PT_GPR14(r1) ;\
  113. l.lwz r15,PT_GPR15(r1) ;\
  114. l.lwz r16,PT_GPR16(r1) ;\
  115. l.lwz r17,PT_GPR17(r1) ;\
  116. l.lwz r18,PT_GPR18(r1) ;\
  117. l.lwz r19,PT_GPR19(r1) ;\
  118. l.lwz r20,PT_GPR20(r1) ;\
  119. l.lwz r21,PT_GPR21(r1) ;\
  120. l.lwz r22,PT_GPR22(r1) ;\
  121. l.lwz r23,PT_GPR23(r1) ;\
  122. l.lwz r24,PT_GPR24(r1) ;\
  123. l.lwz r25,PT_GPR25(r1) ;\
  124. l.lwz r26,PT_GPR26(r1) ;\
  125. l.lwz r27,PT_GPR27(r1) ;\
  126. l.lwz r28,PT_GPR28(r1) ;\
  127. l.lwz r29,PT_GPR29(r1) ;\
  128. l.lwz r30,PT_GPR30(r1) ;\
  129. l.lwz r31,PT_GPR31(r1) ;\
  130. l.lwz r1,PT_SP(r1) ;\
  131. l.rfe
  132. #define EXCEPTION_ENTRY(handler) \
  133. .global handler ;\
  134. handler: ;\
  135. /* r1, EPCR, ESR a already saved */ ;\
  136. l.sw PT_GPR2(r1),r2 ;\
  137. l.sw PT_GPR3(r1),r3 ;\
  138. /* r4 already save */ ;\
  139. l.sw PT_GPR5(r1),r5 ;\
  140. l.sw PT_GPR6(r1),r6 ;\
  141. l.sw PT_GPR7(r1),r7 ;\
  142. l.sw PT_GPR8(r1),r8 ;\
  143. l.sw PT_GPR9(r1),r9 ;\
  144. /* r10 already saved */ ;\
  145. l.sw PT_GPR11(r1),r11 ;\
  146. /* r12 already saved */ ;\
  147. l.sw PT_GPR13(r1),r13 ;\
  148. l.sw PT_GPR14(r1),r14 ;\
  149. l.sw PT_GPR15(r1),r15 ;\
  150. l.sw PT_GPR16(r1),r16 ;\
  151. l.sw PT_GPR17(r1),r17 ;\
  152. l.sw PT_GPR18(r1),r18 ;\
  153. l.sw PT_GPR19(r1),r19 ;\
  154. l.sw PT_GPR20(r1),r20 ;\
  155. l.sw PT_GPR21(r1),r21 ;\
  156. l.sw PT_GPR22(r1),r22 ;\
  157. l.sw PT_GPR23(r1),r23 ;\
  158. l.sw PT_GPR24(r1),r24 ;\
  159. l.sw PT_GPR25(r1),r25 ;\
  160. l.sw PT_GPR26(r1),r26 ;\
  161. l.sw PT_GPR27(r1),r27 ;\
  162. l.sw PT_GPR28(r1),r28 ;\
  163. l.sw PT_GPR29(r1),r29 ;\
  164. /* r30 already save */ ;\
  165. /* l.sw PT_GPR30(r1),r30*/ ;\
  166. l.sw PT_GPR31(r1),r31 ;\
  167. TRACE_IRQS_OFF_ENTRY ;\
  168. /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
  169. l.addi r30,r0,-1 ;\
  170. l.sw PT_ORIG_GPR11(r1),r30
  171. #define UNHANDLED_EXCEPTION(handler,vector) \
  172. .global handler ;\
  173. handler: ;\
  174. /* r1, EPCR, ESR already saved */ ;\
  175. l.sw PT_GPR2(r1),r2 ;\
  176. l.sw PT_GPR3(r1),r3 ;\
  177. l.sw PT_GPR5(r1),r5 ;\
  178. l.sw PT_GPR6(r1),r6 ;\
  179. l.sw PT_GPR7(r1),r7 ;\
  180. l.sw PT_GPR8(r1),r8 ;\
  181. l.sw PT_GPR9(r1),r9 ;\
  182. /* r10 already saved */ ;\
  183. l.sw PT_GPR11(r1),r11 ;\
  184. /* r12 already saved */ ;\
  185. l.sw PT_GPR13(r1),r13 ;\
  186. l.sw PT_GPR14(r1),r14 ;\
  187. l.sw PT_GPR15(r1),r15 ;\
  188. l.sw PT_GPR16(r1),r16 ;\
  189. l.sw PT_GPR17(r1),r17 ;\
  190. l.sw PT_GPR18(r1),r18 ;\
  191. l.sw PT_GPR19(r1),r19 ;\
  192. l.sw PT_GPR20(r1),r20 ;\
  193. l.sw PT_GPR21(r1),r21 ;\
  194. l.sw PT_GPR22(r1),r22 ;\
  195. l.sw PT_GPR23(r1),r23 ;\
  196. l.sw PT_GPR24(r1),r24 ;\
  197. l.sw PT_GPR25(r1),r25 ;\
  198. l.sw PT_GPR26(r1),r26 ;\
  199. l.sw PT_GPR27(r1),r27 ;\
  200. l.sw PT_GPR28(r1),r28 ;\
  201. l.sw PT_GPR29(r1),r29 ;\
  202. /* r31 already saved */ ;\
  203. l.sw PT_GPR30(r1),r30 ;\
  204. /* l.sw PT_GPR31(r1),r31 */ ;\
  205. /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
  206. l.addi r30,r0,-1 ;\
  207. l.sw PT_ORIG_GPR11(r1),r30 ;\
  208. l.addi r3,r1,0 ;\
  209. /* r4 is exception EA */ ;\
  210. l.addi r5,r0,vector ;\
  211. l.jal unhandled_exception ;\
  212. l.nop ;\
  213. l.j _ret_from_exception ;\
  214. l.nop
  215. /* clobbers 'reg' */
  216. #define CLEAR_LWA_FLAG(reg) \
  217. l.movhi reg,hi(lwa_flag) ;\
  218. l.ori reg,reg,lo(lwa_flag) ;\
  219. l.sw 0(reg),r0
  220. /*
  221. * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
  222. * contain the same values as when exception we're handling
  223. * occured. in fact they never do. if you need them use
  224. * values saved on stack (for SPR_EPC, SPR_ESR) or content
  225. * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
  226. * in 'arch/openrisc/kernel/head.S'
  227. */
  228. /* =====================================================[ exceptions] === */
  229. /* ---[ 0x100: RESET exception ]----------------------------------------- */
  230. EXCEPTION_ENTRY(_tng_kernel_start)
  231. l.jal _start
  232. l.andi r0,r0,0
  233. /* ---[ 0x200: BUS exception ]------------------------------------------- */
  234. EXCEPTION_ENTRY(_bus_fault_handler)
  235. CLEAR_LWA_FLAG(r3)
  236. /* r4: EA of fault (set by EXCEPTION_HANDLE) */
  237. l.jal do_bus_fault
  238. l.addi r3,r1,0 /* pt_regs */
  239. l.j _ret_from_exception
  240. l.nop
  241. /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
  242. EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
  243. CLEAR_LWA_FLAG(r3)
  244. l.and r5,r5,r0
  245. l.j 1f
  246. l.nop
  247. EXCEPTION_ENTRY(_data_page_fault_handler)
  248. CLEAR_LWA_FLAG(r3)
  249. /* set up parameters for do_page_fault */
  250. l.ori r5,r0,0x300 // exception vector
  251. 1:
  252. l.addi r3,r1,0 // pt_regs
  253. /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
  254. #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
  255. l.lwz r6,PT_PC(r3) // address of an offending insn
  256. l.lwz r6,0(r6) // instruction that caused pf
  257. l.srli r6,r6,26 // check opcode for jump insn
  258. l.sfeqi r6,0 // l.j
  259. l.bf 8f
  260. l.sfeqi r6,1 // l.jal
  261. l.bf 8f
  262. l.sfeqi r6,3 // l.bnf
  263. l.bf 8f
  264. l.sfeqi r6,4 // l.bf
  265. l.bf 8f
  266. l.sfeqi r6,0x11 // l.jr
  267. l.bf 8f
  268. l.sfeqi r6,0x12 // l.jalr
  269. l.bf 8f
  270. l.nop
  271. l.j 9f
  272. l.nop
  273. 8: // offending insn is in delay slot
  274. l.lwz r6,PT_PC(r3) // address of an offending insn
  275. l.addi r6,r6,4
  276. l.lwz r6,0(r6) // instruction that caused pf
  277. l.srli r6,r6,26 // get opcode
  278. 9: // offending instruction opcode loaded in r6
  279. #else
  280. l.mfspr r6,r0,SPR_SR // SR
  281. l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
  282. l.sfne r6,r0 // exception happened in delay slot
  283. l.bnf 7f
  284. l.lwz r6,PT_PC(r3) // address of an offending insn
  285. l.addi r6,r6,4 // offending insn is in delay slot
  286. 7:
  287. l.lwz r6,0(r6) // instruction that caused pf
  288. l.srli r6,r6,26 // check opcode for write access
  289. #endif
  290. l.sfgeui r6,0x33 // check opcode for write access
  291. l.bnf 1f
  292. l.sfleui r6,0x37
  293. l.bnf 1f
  294. l.ori r6,r0,0x1 // write access
  295. l.j 2f
  296. l.nop
  297. 1: l.ori r6,r0,0x0 // !write access
  298. 2:
  299. /* call fault.c handler in or32/mm/fault.c */
  300. l.jal do_page_fault
  301. l.nop
  302. l.j _ret_from_exception
  303. l.nop
  304. /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
  305. EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
  306. CLEAR_LWA_FLAG(r3)
  307. l.and r5,r5,r0
  308. l.j 1f
  309. l.nop
  310. EXCEPTION_ENTRY(_insn_page_fault_handler)
  311. CLEAR_LWA_FLAG(r3)
  312. /* set up parameters for do_page_fault */
  313. l.ori r5,r0,0x400 // exception vector
  314. 1:
  315. l.addi r3,r1,0 // pt_regs
  316. /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
  317. l.ori r6,r0,0x0 // !write access
  318. /* call fault.c handler in or32/mm/fault.c */
  319. l.jal do_page_fault
  320. l.nop
  321. l.j _ret_from_exception
  322. l.nop
  323. /* ---[ 0x500: Timer exception ]----------------------------------------- */
  324. EXCEPTION_ENTRY(_timer_handler)
  325. CLEAR_LWA_FLAG(r3)
  326. l.jal timer_interrupt
  327. l.addi r3,r1,0 /* pt_regs */
  328. l.j _ret_from_intr
  329. l.nop
  330. /* ---[ 0x600: Alignment exception ]-------------------------------------- */
  331. EXCEPTION_ENTRY(_alignment_handler)
  332. CLEAR_LWA_FLAG(r3)
  333. /* r4: EA of fault (set by EXCEPTION_HANDLE) */
  334. l.jal do_unaligned_access
  335. l.addi r3,r1,0 /* pt_regs */
  336. l.j _ret_from_exception
  337. l.nop
  338. #if 0
  339. EXCEPTION_ENTRY(_alignment_handler)
  340. // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
  341. l.addi r2,r4,0
  342. // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
  343. l.lwz r5,PT_PC(r1)
  344. l.lwz r3,0(r5) /* Load insn */
  345. l.srli r4,r3,26 /* Shift left to get the insn opcode */
  346. l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
  347. l.bf jmp
  348. l.sfeqi r4,0x01
  349. l.bf jmp
  350. l.sfeqi r4,0x03
  351. l.bf jmp
  352. l.sfeqi r4,0x04
  353. l.bf jmp
  354. l.sfeqi r4,0x11
  355. l.bf jr
  356. l.sfeqi r4,0x12
  357. l.bf jr
  358. l.nop
  359. l.j 1f
  360. l.addi r5,r5,4 /* Increment PC to get return insn address */
  361. jmp:
  362. l.slli r4,r3,6 /* Get the signed extended jump length */
  363. l.srai r4,r4,4
  364. l.lwz r3,4(r5) /* Load the real load/store insn */
  365. l.add r5,r5,r4 /* Calculate jump target address */
  366. l.j 1f
  367. l.srli r4,r3,26 /* Shift left to get the insn opcode */
  368. jr:
  369. l.slli r4,r3,9 /* Shift to get the reg nb */
  370. l.andi r4,r4,0x7c
  371. l.lwz r3,4(r5) /* Load the real load/store insn */
  372. l.add r4,r4,r1 /* Load the jump register value from the stack */
  373. l.lwz r5,0(r4)
  374. l.srli r4,r3,26 /* Shift left to get the insn opcode */
  375. 1:
  376. // l.mtspr r0,r5,SPR_EPCR_BASE
  377. l.sw PT_PC(r1),r5
  378. l.sfeqi r4,0x26
  379. l.bf lhs
  380. l.sfeqi r4,0x25
  381. l.bf lhz
  382. l.sfeqi r4,0x22
  383. l.bf lws
  384. l.sfeqi r4,0x21
  385. l.bf lwz
  386. l.sfeqi r4,0x37
  387. l.bf sh
  388. l.sfeqi r4,0x35
  389. l.bf sw
  390. l.nop
  391. 1: l.j 1b /* I don't know what to do */
  392. l.nop
  393. lhs: l.lbs r5,0(r2)
  394. l.slli r5,r5,8
  395. l.lbz r6,1(r2)
  396. l.or r5,r5,r6
  397. l.srli r4,r3,19
  398. l.andi r4,r4,0x7c
  399. l.add r4,r4,r1
  400. l.j align_end
  401. l.sw 0(r4),r5
  402. lhz: l.lbz r5,0(r2)
  403. l.slli r5,r5,8
  404. l.lbz r6,1(r2)
  405. l.or r5,r5,r6
  406. l.srli r4,r3,19
  407. l.andi r4,r4,0x7c
  408. l.add r4,r4,r1
  409. l.j align_end
  410. l.sw 0(r4),r5
  411. lws: l.lbs r5,0(r2)
  412. l.slli r5,r5,24
  413. l.lbz r6,1(r2)
  414. l.slli r6,r6,16
  415. l.or r5,r5,r6
  416. l.lbz r6,2(r2)
  417. l.slli r6,r6,8
  418. l.or r5,r5,r6
  419. l.lbz r6,3(r2)
  420. l.or r5,r5,r6
  421. l.srli r4,r3,19
  422. l.andi r4,r4,0x7c
  423. l.add r4,r4,r1
  424. l.j align_end
  425. l.sw 0(r4),r5
  426. lwz: l.lbz r5,0(r2)
  427. l.slli r5,r5,24
  428. l.lbz r6,1(r2)
  429. l.slli r6,r6,16
  430. l.or r5,r5,r6
  431. l.lbz r6,2(r2)
  432. l.slli r6,r6,8
  433. l.or r5,r5,r6
  434. l.lbz r6,3(r2)
  435. l.or r5,r5,r6
  436. l.srli r4,r3,19
  437. l.andi r4,r4,0x7c
  438. l.add r4,r4,r1
  439. l.j align_end
  440. l.sw 0(r4),r5
  441. sh:
  442. l.srli r4,r3,9
  443. l.andi r4,r4,0x7c
  444. l.add r4,r4,r1
  445. l.lwz r5,0(r4)
  446. l.sb 1(r2),r5
  447. l.srli r5,r5,8
  448. l.j align_end
  449. l.sb 0(r2),r5
  450. sw:
  451. l.srli r4,r3,9
  452. l.andi r4,r4,0x7c
  453. l.add r4,r4,r1
  454. l.lwz r5,0(r4)
  455. l.sb 3(r2),r5
  456. l.srli r5,r5,8
  457. l.sb 2(r2),r5
  458. l.srli r5,r5,8
  459. l.sb 1(r2),r5
  460. l.srli r5,r5,8
  461. l.j align_end
  462. l.sb 0(r2),r5
  463. align_end:
  464. l.j _ret_from_intr
  465. l.nop
  466. #endif
  467. /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
  468. EXCEPTION_ENTRY(_illegal_instruction_handler)
  469. /* r4: EA of fault (set by EXCEPTION_HANDLE) */
  470. l.jal do_illegal_instruction
  471. l.addi r3,r1,0 /* pt_regs */
  472. l.j _ret_from_exception
  473. l.nop
  474. /* ---[ 0x800: External interrupt exception ]---------------------------- */
  475. EXCEPTION_ENTRY(_external_irq_handler)
  476. #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
  477. l.lwz r4,PT_SR(r1) // were interrupts enabled ?
  478. l.andi r4,r4,SPR_SR_IEE
  479. l.sfeqi r4,0
  480. l.bnf 1f // ext irq enabled, all ok.
  481. l.nop
  482. #ifdef CONFIG_PRINTK
  483. l.addi r1,r1,-0x8
  484. l.movhi r3,hi(42f)
  485. l.ori r3,r3,lo(42f)
  486. l.sw 0x0(r1),r3
  487. l.jal printk
  488. l.sw 0x4(r1),r4
  489. l.addi r1,r1,0x8
  490. .section .rodata, "a"
  491. 42:
  492. .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
  493. .align 4
  494. .previous
  495. #endif
  496. l.ori r4,r4,SPR_SR_IEE // fix the bug
  497. // l.sw PT_SR(r1),r4
  498. 1:
  499. #endif
  500. CLEAR_LWA_FLAG(r3)
  501. l.addi r3,r1,0
  502. l.movhi r8,hi(do_IRQ)
  503. l.ori r8,r8,lo(do_IRQ)
  504. l.jalr r8
  505. l.nop
  506. l.j _ret_from_intr
  507. l.nop
  508. /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
  509. /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
  510. /* ---[ 0xb00: Range exception ]----------------------------------------- */
  511. UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
  512. /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
  513. /*
  514. * Syscalls are a special type of exception in that they are
  515. * _explicitly_ invoked by userspace and can therefore be
  516. * held to conform to the same ABI as normal functions with
  517. * respect to whether registers are preserved across the call
  518. * or not.
  519. */
  520. /* Upon syscall entry we just save the callee-saved registers
  521. * and not the call-clobbered ones.
  522. */
  523. _string_syscall_return:
  524. .string "syscall return %ld \n\r\0"
  525. .align 4
  526. ENTRY(_sys_call_handler)
  527. /* r1, EPCR, ESR a already saved */
  528. l.sw PT_GPR2(r1),r2
  529. /* r3-r8 must be saved because syscall restart relies
  530. * on us being able to restart the syscall args... technically
  531. * they should be clobbered, otherwise
  532. */
  533. l.sw PT_GPR3(r1),r3
  534. /*
  535. * r4 already saved
  536. * r4 holds the EEAR address of the fault, use it as screatch reg and
  537. * then load the original r4
  538. */
  539. CLEAR_LWA_FLAG(r4)
  540. l.lwz r4,PT_GPR4(r1)
  541. l.sw PT_GPR5(r1),r5
  542. l.sw PT_GPR6(r1),r6
  543. l.sw PT_GPR7(r1),r7
  544. l.sw PT_GPR8(r1),r8
  545. l.sw PT_GPR9(r1),r9
  546. /* r10 already saved */
  547. l.sw PT_GPR11(r1),r11
  548. /* orig_gpr11 must be set for syscalls */
  549. l.sw PT_ORIG_GPR11(r1),r11
  550. /* r12,r13 already saved */
  551. /* r14-r28 (even) aren't touched by the syscall fast path below
  552. * so we don't need to save them. However, the functions that return
  553. * to userspace via a call to switch() DO need to save these because
  554. * switch() effectively clobbers them... saving these registers for
  555. * such functions is handled in their syscall wrappers (see fork, vfork,
  556. * and clone, below).
  557. /* r30 is the only register we clobber in the fast path */
  558. /* r30 already saved */
  559. /* l.sw PT_GPR30(r1),r30 */
  560. _syscall_check_trace_enter:
  561. /* syscalls run with interrupts enabled */
  562. TRACE_IRQS_ON_SYSCALL
  563. ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
  564. /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
  565. l.lwz r30,TI_FLAGS(r10)
  566. l.andi r30,r30,_TIF_SYSCALL_TRACE
  567. l.sfne r30,r0
  568. l.bf _syscall_trace_enter
  569. l.nop
  570. _syscall_check:
  571. /* Ensure that the syscall number is reasonable */
  572. l.sfgeui r11,__NR_syscalls
  573. l.bf _syscall_badsys
  574. l.nop
  575. _syscall_call:
  576. l.movhi r29,hi(sys_call_table)
  577. l.ori r29,r29,lo(sys_call_table)
  578. l.slli r11,r11,2
  579. l.add r29,r29,r11
  580. l.lwz r29,0(r29)
  581. l.jalr r29
  582. l.nop
  583. _syscall_return:
  584. /* All syscalls return here... just pay attention to ret_from_fork
  585. * which does it in a round-about way.
  586. */
  587. l.sw PT_GPR11(r1),r11 // save return value
  588. #if 0
  589. _syscall_debug:
  590. l.movhi r3,hi(_string_syscall_return)
  591. l.ori r3,r3,lo(_string_syscall_return)
  592. l.ori r27,r0,1
  593. l.sw -4(r1),r27
  594. l.sw -8(r1),r11
  595. l.addi r1,r1,-8
  596. l.movhi r27,hi(printk)
  597. l.ori r27,r27,lo(printk)
  598. l.jalr r27
  599. l.nop
  600. l.addi r1,r1,8
  601. #endif
  602. _syscall_check_trace_leave:
  603. /* r30 is a callee-saved register so this should still hold the
  604. * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
  605. * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
  606. */
  607. l.sfne r30,r0
  608. l.bf _syscall_trace_leave
  609. l.nop
  610. /* This is where the exception-return code begins... interrupts need to be
  611. * disabled the rest of the way here because we can't afford to miss any
  612. * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
  613. _syscall_check_work:
  614. /* Here we need to disable interrupts */
  615. DISABLE_INTERRUPTS(r27,r29)
  616. TRACE_IRQS_OFF
  617. l.lwz r30,TI_FLAGS(r10)
  618. l.andi r30,r30,_TIF_WORK_MASK
  619. l.sfne r30,r0
  620. l.bnf _syscall_resume_userspace
  621. l.nop
  622. /* Work pending follows a different return path, so we need to
  623. * make sure that all the call-saved registers get into pt_regs
  624. * before branching...
  625. */
  626. l.sw PT_GPR14(r1),r14
  627. l.sw PT_GPR16(r1),r16
  628. l.sw PT_GPR18(r1),r18
  629. l.sw PT_GPR20(r1),r20
  630. l.sw PT_GPR22(r1),r22
  631. l.sw PT_GPR24(r1),r24
  632. l.sw PT_GPR26(r1),r26
  633. l.sw PT_GPR28(r1),r28
  634. /* _work_pending needs to be called with interrupts disabled */
  635. l.j _work_pending
  636. l.nop
  637. _syscall_resume_userspace:
  638. // ENABLE_INTERRUPTS(r29)
  639. /* This is the hot path for returning to userspace from a syscall. If there's
  640. * work to be done and the branch to _work_pending was taken above, then the
  641. * return to userspace will be done via the normal exception return path...
  642. * that path restores _all_ registers and will overwrite the "clobbered"
  643. * registers with whatever garbage is in pt_regs -- that's OK because those
  644. * registers are clobbered anyway and because the extra work is insignificant
  645. * in the context of the extra work that _work_pending is doing.
  646. /* Once again, syscalls are special and only guarantee to preserve the
  647. * same registers as a normal function call */
  648. /* The assumption here is that the registers r14-r28 (even) are untouched and
  649. * don't need to be restored... be sure that that's really the case!
  650. */
  651. /* This is still too much... we should only be restoring what we actually
  652. * clobbered... we should even be using 'scratch' (odd) regs above so that
  653. * we don't need to restore anything, hardly...
  654. */
  655. l.lwz r2,PT_GPR2(r1)
  656. /* Restore args */
  657. /* r3-r8 are technically clobbered, but syscall restart needs these
  658. * to be restored...
  659. */
  660. l.lwz r3,PT_GPR3(r1)
  661. l.lwz r4,PT_GPR4(r1)
  662. l.lwz r5,PT_GPR5(r1)
  663. l.lwz r6,PT_GPR6(r1)
  664. l.lwz r7,PT_GPR7(r1)
  665. l.lwz r8,PT_GPR8(r1)
  666. l.lwz r9,PT_GPR9(r1)
  667. l.lwz r10,PT_GPR10(r1)
  668. l.lwz r11,PT_GPR11(r1)
  669. /* r30 is the only register we clobber in the fast path */
  670. l.lwz r30,PT_GPR30(r1)
  671. /* Here we use r13-r19 (odd) as scratch regs */
  672. l.lwz r13,PT_PC(r1)
  673. l.lwz r15,PT_SR(r1)
  674. l.lwz r1,PT_SP(r1)
  675. /* Interrupts need to be disabled for setting EPCR and ESR
  676. * so that another interrupt doesn't come in here and clobber
  677. * them before we can use them for our l.rfe */
  678. DISABLE_INTERRUPTS(r17,r19)
  679. l.mtspr r0,r13,SPR_EPCR_BASE
  680. l.mtspr r0,r15,SPR_ESR_BASE
  681. l.rfe
  682. /* End of hot path!
  683. * Keep the below tracing and error handling out of the hot path...
  684. */
  685. _syscall_trace_enter:
  686. /* Here we pass pt_regs to do_syscall_trace_enter. Make sure
  687. * that function is really getting all the info it needs as
  688. * pt_regs isn't a complete set of userspace regs, just the
  689. * ones relevant to the syscall...
  690. *
  691. * Note use of delay slot for setting argument.
  692. */
  693. l.jal do_syscall_trace_enter
  694. l.addi r3,r1,0
  695. /* Restore arguments (not preserved across do_syscall_trace_enter)
  696. * so that we can do the syscall for real and return to the syscall
  697. * hot path.
  698. */
  699. l.lwz r11,PT_GPR11(r1)
  700. l.lwz r3,PT_GPR3(r1)
  701. l.lwz r4,PT_GPR4(r1)
  702. l.lwz r5,PT_GPR5(r1)
  703. l.lwz r6,PT_GPR6(r1)
  704. l.lwz r7,PT_GPR7(r1)
  705. l.j _syscall_check
  706. l.lwz r8,PT_GPR8(r1)
  707. _syscall_trace_leave:
  708. l.jal do_syscall_trace_leave
  709. l.addi r3,r1,0
  710. l.j _syscall_check_work
  711. l.nop
  712. _syscall_badsys:
  713. /* Here we effectively pretend to have executed an imaginary
  714. * syscall that returns -ENOSYS and then return to the regular
  715. * syscall hot path.
  716. * Note that "return value" is set in the delay slot...
  717. */
  718. l.j _syscall_return
  719. l.addi r11,r0,-ENOSYS
  720. /******* END SYSCALL HANDLING *******/
  721. /* ---[ 0xd00: Trap exception ]------------------------------------------ */
  722. UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
  723. /* ---[ 0xe00: Trap exception ]------------------------------------------ */
  724. EXCEPTION_ENTRY(_trap_handler)
  725. CLEAR_LWA_FLAG(r3)
  726. /* r4: EA of fault (set by EXCEPTION_HANDLE) */
  727. l.jal do_trap
  728. l.addi r3,r1,0 /* pt_regs */
  729. l.j _ret_from_exception
  730. l.nop
  731. /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
  732. UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
  733. /* ---[ 0x1000: Reserved exception ]------------------------------------- */
  734. UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
  735. /* ---[ 0x1100: Reserved exception ]------------------------------------- */
  736. UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
  737. /* ---[ 0x1200: Reserved exception ]------------------------------------- */
  738. UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
  739. /* ---[ 0x1300: Reserved exception ]------------------------------------- */
  740. UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
  741. /* ---[ 0x1400: Reserved exception ]------------------------------------- */
  742. UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
  743. /* ---[ 0x1500: Reserved exception ]------------------------------------- */
  744. UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
  745. /* ---[ 0x1600: Reserved exception ]------------------------------------- */
  746. UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
  747. /* ---[ 0x1700: Reserved exception ]------------------------------------- */
  748. UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
  749. /* ---[ 0x1800: Reserved exception ]------------------------------------- */
  750. UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
  751. /* ---[ 0x1900: Reserved exception ]------------------------------------- */
  752. UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
  753. /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
  754. UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
  755. /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
  756. UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
  757. /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
  758. UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
  759. /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
  760. UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
  761. /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
  762. UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
  763. /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
  764. UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
  765. /* ========================================================[ return ] === */
  766. _resume_userspace:
  767. DISABLE_INTERRUPTS(r3,r4)
  768. TRACE_IRQS_OFF
  769. l.lwz r4,TI_FLAGS(r10)
  770. l.andi r13,r4,_TIF_WORK_MASK
  771. l.sfeqi r13,0
  772. l.bf _restore_all
  773. l.nop
  774. _work_pending:
  775. l.lwz r5,PT_ORIG_GPR11(r1)
  776. l.sfltsi r5,0
  777. l.bnf 1f
  778. l.nop
  779. l.andi r5,r5,0
  780. 1:
  781. l.jal do_work_pending
  782. l.ori r3,r1,0 /* pt_regs */
  783. l.sfeqi r11,0
  784. l.bf _restore_all
  785. l.nop
  786. l.sfltsi r11,0
  787. l.bnf 1f
  788. l.nop
  789. l.and r11,r11,r0
  790. l.ori r11,r11,__NR_restart_syscall
  791. l.j _syscall_check_trace_enter
  792. l.nop
  793. 1:
  794. l.lwz r11,PT_ORIG_GPR11(r1)
  795. /* Restore arg registers */
  796. l.lwz r3,PT_GPR3(r1)
  797. l.lwz r4,PT_GPR4(r1)
  798. l.lwz r5,PT_GPR5(r1)
  799. l.lwz r6,PT_GPR6(r1)
  800. l.lwz r7,PT_GPR7(r1)
  801. l.j _syscall_check_trace_enter
  802. l.lwz r8,PT_GPR8(r1)
  803. _restore_all:
  804. #ifdef CONFIG_TRACE_IRQFLAGS
  805. l.lwz r4,PT_SR(r1)
  806. l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
  807. l.sfeq r3,r0 /* skip trace if irqs were off */
  808. l.bf skip_hardirqs_on
  809. l.nop
  810. TRACE_IRQS_ON
  811. skip_hardirqs_on:
  812. #endif
  813. RESTORE_ALL
  814. /* This returns to userspace code */
  815. ENTRY(_ret_from_intr)
  816. ENTRY(_ret_from_exception)
  817. l.lwz r4,PT_SR(r1)
  818. l.andi r3,r4,SPR_SR_SM
  819. l.sfeqi r3,0
  820. l.bnf _restore_all
  821. l.nop
  822. l.j _resume_userspace
  823. l.nop
  824. ENTRY(ret_from_fork)
  825. l.jal schedule_tail
  826. l.nop
  827. /* Check if we are a kernel thread */
  828. l.sfeqi r20,0
  829. l.bf 1f
  830. l.nop
  831. /* ...we are a kernel thread so invoke the requested callback */
  832. l.jalr r20
  833. l.or r3,r22,r0
  834. 1:
  835. /* _syscall_returns expect r11 to contain return value */
  836. l.lwz r11,PT_GPR11(r1)
  837. /* The syscall fast path return expects call-saved registers
  838. * r12-r28 to be untouched, so we restore them here as they
  839. * will have been effectively clobbered when arriving here
  840. * via the call to switch()
  841. */
  842. l.lwz r12,PT_GPR12(r1)
  843. l.lwz r14,PT_GPR14(r1)
  844. l.lwz r16,PT_GPR16(r1)
  845. l.lwz r18,PT_GPR18(r1)
  846. l.lwz r20,PT_GPR20(r1)
  847. l.lwz r22,PT_GPR22(r1)
  848. l.lwz r24,PT_GPR24(r1)
  849. l.lwz r26,PT_GPR26(r1)
  850. l.lwz r28,PT_GPR28(r1)
  851. l.j _syscall_return
  852. l.nop
  853. /* ========================================================[ switch ] === */
  854. /*
  855. * This routine switches between two different tasks. The process
  856. * state of one is saved on its kernel stack. Then the state
  857. * of the other is restored from its kernel stack. The memory
  858. * management hardware is updated to the second process's state.
  859. * Finally, we can return to the second process, via the 'return'.
  860. *
  861. * Note: there are two ways to get to the "going out" portion
  862. * of this code; either by coming in via the entry (_switch)
  863. * or via "fork" which must set up an environment equivalent
  864. * to the "_switch" path. If you change this (or in particular, the
  865. * SAVE_REGS macro), you'll have to change the fork code also.
  866. */
  867. /* _switch MUST never lay on page boundry, cause it runs from
  868. * effective addresses and beeing interrupted by iTLB miss would kill it.
  869. * dTLB miss seams to never accour in the bad place since data accesses
  870. * are from task structures which are always page aligned.
  871. *
  872. * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
  873. * register, then load the previous register values and only at the end call
  874. * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
  875. * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
  876. * holds for ESR)
  877. *
  878. * To avoid this problems it is sufficient to align _switch to
  879. * some nice round number smaller than it's size...
  880. */
  881. /* ABI rules apply here... we either enter _switch via schedule() or via
  882. * an imaginary call to which we shall return at return_from_fork. Either
  883. * way, we are a function call and only need to preserve the callee-saved
  884. * registers when we return. As such, we don't need to save the registers
  885. * on the stack that we won't be returning as they were...
  886. */
  887. .align 0x400
  888. ENTRY(_switch)
  889. /* We don't store SR as _switch only gets called in a context where
  890. * the SR will be the same going in and coming out... */
  891. /* Set up new pt_regs struct for saving task state */
  892. l.addi r1,r1,-(INT_FRAME_SIZE)
  893. /* No need to store r1/PT_SP as it goes into KSP below */
  894. l.sw PT_GPR2(r1),r2
  895. l.sw PT_GPR9(r1),r9
  896. /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
  897. * and expects r12 to be callee-saved... */
  898. l.sw PT_GPR12(r1),r12
  899. l.sw PT_GPR14(r1),r14
  900. l.sw PT_GPR16(r1),r16
  901. l.sw PT_GPR18(r1),r18
  902. l.sw PT_GPR20(r1),r20
  903. l.sw PT_GPR22(r1),r22
  904. l.sw PT_GPR24(r1),r24
  905. l.sw PT_GPR26(r1),r26
  906. l.sw PT_GPR28(r1),r28
  907. l.sw PT_GPR30(r1),r30
  908. l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
  909. /* We use thread_info->ksp for storing the address of the above
  910. * structure so that we can get back to it later... we don't want
  911. * to lose the value of thread_info->ksp, though, so store it as
  912. * pt_regs->sp so that we can easily restore it when we are made
  913. * live again...
  914. */
  915. /* Save the old value of thread_info->ksp as pt_regs->sp */
  916. l.lwz r29,TI_KSP(r10)
  917. l.sw PT_SP(r1),r29
  918. /* Swap kernel stack pointers */
  919. l.sw TI_KSP(r10),r1 /* Save old stack pointer */
  920. l.or r10,r4,r0 /* Set up new current_thread_info */
  921. l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
  922. /* Restore the old value of thread_info->ksp */
  923. l.lwz r29,PT_SP(r1)
  924. l.sw TI_KSP(r10),r29
  925. /* ...and restore the registers, except r11 because the return value
  926. * has already been set above.
  927. */
  928. l.lwz r2,PT_GPR2(r1)
  929. l.lwz r9,PT_GPR9(r1)
  930. /* No need to restore r10 */
  931. /* ...and do not restore r11 */
  932. /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
  933. * and expects r12 to be callee-saved... */
  934. l.lwz r12,PT_GPR12(r1)
  935. l.lwz r14,PT_GPR14(r1)
  936. l.lwz r16,PT_GPR16(r1)
  937. l.lwz r18,PT_GPR18(r1)
  938. l.lwz r20,PT_GPR20(r1)
  939. l.lwz r22,PT_GPR22(r1)
  940. l.lwz r24,PT_GPR24(r1)
  941. l.lwz r26,PT_GPR26(r1)
  942. l.lwz r28,PT_GPR28(r1)
  943. l.lwz r30,PT_GPR30(r1)
  944. /* Unwind stack to pre-switch state */
  945. l.addi r1,r1,(INT_FRAME_SIZE)
  946. /* Return via the link-register back to where we 'came from', where
  947. * that may be either schedule(), ret_from_fork(), or
  948. * ret_from_kernel_thread(). If we are returning to a new thread,
  949. * we are expected to have set up the arg to schedule_tail already,
  950. * hence we do so here unconditionally:
  951. */
  952. l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
  953. l.jr r9
  954. l.nop
  955. /* ==================================================================== */
  956. /* These all use the delay slot for setting the argument register, so the
  957. * jump is always happening after the l.addi instruction.
  958. *
  959. * These are all just wrappers that don't touch the link-register r9, so the
  960. * return from the "real" syscall function will return back to the syscall
  961. * code that did the l.jal that brought us here.
  962. */
  963. /* fork requires that we save all the callee-saved registers because they
  964. * are all effectively clobbered by the call to _switch. Here we store
  965. * all the registers that aren't touched by the syscall fast path and thus
  966. * weren't saved there.
  967. */
  968. _fork_save_extra_regs_and_call:
  969. l.sw PT_GPR14(r1),r14
  970. l.sw PT_GPR16(r1),r16
  971. l.sw PT_GPR18(r1),r18
  972. l.sw PT_GPR20(r1),r20
  973. l.sw PT_GPR22(r1),r22
  974. l.sw PT_GPR24(r1),r24
  975. l.sw PT_GPR26(r1),r26
  976. l.jr r29
  977. l.sw PT_GPR28(r1),r28
  978. ENTRY(__sys_clone)
  979. l.movhi r29,hi(sys_clone)
  980. l.ori r29,r29,lo(sys_clone)
  981. l.j _fork_save_extra_regs_and_call
  982. l.nop
  983. ENTRY(__sys_clone3)
  984. l.movhi r29,hi(sys_clone3)
  985. l.j _fork_save_extra_regs_and_call
  986. l.ori r29,r29,lo(sys_clone3)
  987. ENTRY(__sys_fork)
  988. l.movhi r29,hi(sys_fork)
  989. l.ori r29,r29,lo(sys_fork)
  990. l.j _fork_save_extra_regs_and_call
  991. l.nop
  992. ENTRY(sys_rt_sigreturn)
  993. l.jal _sys_rt_sigreturn
  994. l.addi r3,r1,0
  995. l.sfne r30,r0
  996. l.bnf _no_syscall_trace
  997. l.nop
  998. l.jal do_syscall_trace_leave
  999. l.addi r3,r1,0
  1000. _no_syscall_trace:
  1001. l.j _resume_userspace
  1002. l.nop
  1003. /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
  1004. * The functions takes a variable number of parameters depending on which
  1005. * particular flavour of atomic you want... parameter 1 is a flag identifying
  1006. * the atomic in question. Currently, this function implements the
  1007. * following variants:
  1008. *
  1009. * XCHG:
  1010. * @flag: 1
  1011. * @ptr1:
  1012. * @ptr2:
  1013. * Atomically exchange the values in pointers 1 and 2.
  1014. *
  1015. */
  1016. ENTRY(sys_or1k_atomic)
  1017. /* FIXME: This ignores r3 and always does an XCHG */
  1018. DISABLE_INTERRUPTS(r17,r19)
  1019. l.lwz r29,0(r4)
  1020. l.lwz r27,0(r5)
  1021. l.sw 0(r4),r27
  1022. l.sw 0(r5),r29
  1023. ENABLE_INTERRUPTS(r17)
  1024. l.jr r9
  1025. l.or r11,r0,r0
  1026. /* ============================================================[ EOF ]=== */