Kconfig 4.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. #
  3. # For a description of the syntax of this configuration file,
  4. # see Documentation/kbuild/kconfig-language.rst.
  5. #
  6. config OPENRISC
  7. def_bool y
  8. select ARCH_32BIT_OFF_T
  9. select ARCH_HAS_DMA_SET_UNCACHED
  10. select ARCH_HAS_DMA_CLEAR_UNCACHED
  11. select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  12. select OF
  13. select OF_EARLY_FLATTREE
  14. select IRQ_DOMAIN
  15. select HANDLE_DOMAIN_IRQ
  16. select GPIOLIB
  17. select HAVE_ARCH_TRACEHOOK
  18. select SPARSE_IRQ
  19. select GENERIC_IRQ_CHIP
  20. select GENERIC_IRQ_PROBE
  21. select GENERIC_IRQ_SHOW
  22. select GENERIC_IOMAP
  23. select GENERIC_CPU_DEVICES
  24. select HAVE_UID16
  25. select GENERIC_ATOMIC64
  26. select GENERIC_CLOCKEVENTS
  27. select GENERIC_CLOCKEVENTS_BROADCAST
  28. select GENERIC_STRNCPY_FROM_USER
  29. select GENERIC_STRNLEN_USER
  30. select GENERIC_SMP_IDLE_THREAD
  31. select MODULES_USE_ELF_RELA
  32. select HAVE_DEBUG_STACKOVERFLOW
  33. select OR1K_PIC
  34. select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
  35. select ARCH_USE_QUEUED_SPINLOCKS
  36. select ARCH_USE_QUEUED_RWLOCKS
  37. select OMPIC if SMP
  38. select ARCH_WANT_FRAME_POINTERS
  39. select GENERIC_IRQ_MULTI_HANDLER
  40. select MMU_GATHER_NO_RANGE if MMU
  41. select SET_FS
  42. config CPU_BIG_ENDIAN
  43. def_bool y
  44. config MMU
  45. def_bool y
  46. config GENERIC_HWEIGHT
  47. def_bool y
  48. config NO_IOPORT_MAP
  49. def_bool y
  50. config TRACE_IRQFLAGS_SUPPORT
  51. def_bool y
  52. # For now, use generic checksum functions
  53. #These can be reimplemented in assembly later if so inclined
  54. config GENERIC_CSUM
  55. def_bool y
  56. config STACKTRACE_SUPPORT
  57. def_bool y
  58. config LOCKDEP_SUPPORT
  59. def_bool y
  60. menu "Processor type and features"
  61. choice
  62. prompt "Subarchitecture"
  63. default OR1K_1200
  64. config OR1K_1200
  65. bool "OR1200"
  66. help
  67. Generic OpenRISC 1200 architecture
  68. endchoice
  69. config DCACHE_WRITETHROUGH
  70. bool "Have write through data caches"
  71. default n
  72. help
  73. Select this if your implementation features write through data caches.
  74. Selecting 'N' here will allow the kernel to force flushing of data
  75. caches at relevant times. Most OpenRISC implementations support write-
  76. through data caches.
  77. If unsure say N here
  78. config OPENRISC_BUILTIN_DTB
  79. string "Builtin DTB"
  80. default ""
  81. menu "Class II Instructions"
  82. config OPENRISC_HAVE_INST_FF1
  83. bool "Have instruction l.ff1"
  84. default y
  85. help
  86. Select this if your implementation has the Class II instruction l.ff1
  87. config OPENRISC_HAVE_INST_FL1
  88. bool "Have instruction l.fl1"
  89. default y
  90. help
  91. Select this if your implementation has the Class II instruction l.fl1
  92. config OPENRISC_HAVE_INST_MUL
  93. bool "Have instruction l.mul for hardware multiply"
  94. default y
  95. help
  96. Select this if your implementation has a hardware multiply instruction
  97. config OPENRISC_HAVE_INST_DIV
  98. bool "Have instruction l.div for hardware divide"
  99. default y
  100. help
  101. Select this if your implementation has a hardware divide instruction
  102. endmenu
  103. config NR_CPUS
  104. int "Maximum number of CPUs (2-32)"
  105. range 2 32
  106. depends on SMP
  107. default "2"
  108. config SMP
  109. bool "Symmetric Multi-Processing support"
  110. help
  111. This enables support for systems with more than one CPU. If you have
  112. a system with only one CPU, say N. If you have a system with more
  113. than one CPU, say Y.
  114. If you don't know what to do here, say N.
  115. source "kernel/Kconfig.hz"
  116. config OPENRISC_NO_SPR_SR_DSX
  117. bool "use SPR_SR_DSX software emulation" if OR1K_1200
  118. default y
  119. help
  120. SPR_SR_DSX bit is status register bit indicating whether
  121. the last exception has happened in delay slot.
  122. OpenRISC architecture makes it optional to have it implemented
  123. in hardware and the OR1200 does not have it.
  124. Say N here if you know that your OpenRISC processor has
  125. SPR_SR_DSX bit implemented. Say Y if you are unsure.
  126. config OPENRISC_HAVE_SHADOW_GPRS
  127. bool "Support for shadow gpr files" if !SMP
  128. default y if SMP
  129. help
  130. Say Y here if your OpenRISC processor features shadowed
  131. register files. They will in such case be used as a
  132. scratch reg storage on exception entry.
  133. On SMP systems, this feature is mandatory.
  134. On a unicore system it's safe to say N here if you are unsure.
  135. config CMDLINE
  136. string "Default kernel command string"
  137. default ""
  138. help
  139. On some architectures there is currently no way for the boot loader
  140. to pass arguments to the kernel. For these architectures, you should
  141. supply some command-line options at build time by entering them
  142. here.
  143. menu "Debugging options"
  144. config JUMP_UPON_UNHANDLED_EXCEPTION
  145. bool "Try to die gracefully"
  146. default y
  147. help
  148. Now this puts kernel into infinite loop after first oops. Till
  149. your kernel crashes this doesn't have any influence.
  150. Say Y if you are unsure.
  151. config OPENRISC_ESR_EXCEPTION_BUG_CHECK
  152. bool "Check for possible ESR exception bug"
  153. default n
  154. help
  155. This option enables some checks that might expose some problems
  156. in kernel.
  157. Say N if you are unsure.
  158. endmenu
  159. endmenu