devices.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * RouterBoard 500 Platform devices
  4. *
  5. * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  6. * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/export.h>
  10. #include <linux/init.h>
  11. #include <linux/ctype.h>
  12. #include <linux/string.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/mtd/platnand.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/gpio.h>
  17. #include <linux/gpio/machine.h>
  18. #include <linux/gpio_keys.h>
  19. #include <linux/input.h>
  20. #include <linux/serial_8250.h>
  21. #include <asm/bootinfo.h>
  22. #include <asm/mach-rc32434/rc32434.h>
  23. #include <asm/mach-rc32434/dma.h>
  24. #include <asm/mach-rc32434/dma_v.h>
  25. #include <asm/mach-rc32434/eth.h>
  26. #include <asm/mach-rc32434/rb.h>
  27. #include <asm/mach-rc32434/integ.h>
  28. #include <asm/mach-rc32434/gpio.h>
  29. #include <asm/mach-rc32434/irq.h>
  30. #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  31. #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  32. extern unsigned int idt_cpu_freq;
  33. static struct mpmc_device dev3;
  34. void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
  35. {
  36. unsigned long flags;
  37. spin_lock_irqsave(&dev3.lock, flags);
  38. dev3.state = (dev3.state | or_mask) & ~nand_mask;
  39. writeb(dev3.state, dev3.base);
  40. spin_unlock_irqrestore(&dev3.lock, flags);
  41. }
  42. EXPORT_SYMBOL(set_latch_u5);
  43. unsigned char get_latch_u5(void)
  44. {
  45. return dev3.state;
  46. }
  47. EXPORT_SYMBOL(get_latch_u5);
  48. static struct resource korina_dev0_res[] = {
  49. {
  50. .name = "korina_regs",
  51. .start = ETH0_BASE_ADDR,
  52. .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
  53. .flags = IORESOURCE_MEM,
  54. }, {
  55. .name = "korina_rx",
  56. .start = ETH0_DMA_RX_IRQ,
  57. .end = ETH0_DMA_RX_IRQ,
  58. .flags = IORESOURCE_IRQ
  59. }, {
  60. .name = "korina_tx",
  61. .start = ETH0_DMA_TX_IRQ,
  62. .end = ETH0_DMA_TX_IRQ,
  63. .flags = IORESOURCE_IRQ
  64. }, {
  65. .name = "korina_ovr",
  66. .start = ETH0_RX_OVR_IRQ,
  67. .end = ETH0_RX_OVR_IRQ,
  68. .flags = IORESOURCE_IRQ
  69. }, {
  70. .name = "korina_und",
  71. .start = ETH0_TX_UND_IRQ,
  72. .end = ETH0_TX_UND_IRQ,
  73. .flags = IORESOURCE_IRQ
  74. }, {
  75. .name = "korina_dma_rx",
  76. .start = ETH0_RX_DMA_ADDR,
  77. .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  78. .flags = IORESOURCE_MEM,
  79. }, {
  80. .name = "korina_dma_tx",
  81. .start = ETH0_TX_DMA_ADDR,
  82. .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  83. .flags = IORESOURCE_MEM,
  84. }
  85. };
  86. static struct korina_device korina_dev0_data = {
  87. .name = "korina0",
  88. .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  89. };
  90. static struct platform_device korina_dev0 = {
  91. .id = -1,
  92. .name = "korina",
  93. .resource = korina_dev0_res,
  94. .num_resources = ARRAY_SIZE(korina_dev0_res),
  95. };
  96. static struct resource cf_slot0_res[] = {
  97. {
  98. .name = "cf_membase",
  99. .flags = IORESOURCE_MEM
  100. }, {
  101. .name = "cf_irq",
  102. .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
  103. .end = (8 + 4 * 32 + CF_GPIO_NUM),
  104. .flags = IORESOURCE_IRQ
  105. }
  106. };
  107. static struct gpiod_lookup_table cf_slot0_gpio_table = {
  108. .dev_id = "pata-rb532-cf",
  109. .table = {
  110. GPIO_LOOKUP("gpio0", CF_GPIO_NUM,
  111. NULL, GPIO_ACTIVE_HIGH),
  112. { },
  113. },
  114. };
  115. static struct platform_device cf_slot0 = {
  116. .id = -1,
  117. .name = "pata-rb532-cf",
  118. .resource = cf_slot0_res,
  119. .num_resources = ARRAY_SIZE(cf_slot0_res),
  120. };
  121. /* Resources and device for NAND */
  122. static int rb532_dev_ready(struct nand_chip *chip)
  123. {
  124. return gpio_get_value(GPIO_RDY);
  125. }
  126. static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
  127. {
  128. unsigned char orbits, nandbits;
  129. if (ctrl & NAND_CTRL_CHANGE) {
  130. orbits = (ctrl & NAND_CLE) << 1;
  131. orbits |= (ctrl & NAND_ALE) >> 1;
  132. nandbits = (~ctrl & NAND_CLE) << 1;
  133. nandbits |= (~ctrl & NAND_ALE) >> 1;
  134. set_latch_u5(orbits, nandbits);
  135. }
  136. if (cmd != NAND_CMD_NONE)
  137. writeb(cmd, chip->legacy.IO_ADDR_W);
  138. }
  139. static struct resource nand_slot0_res[] = {
  140. [0] = {
  141. .name = "nand_membase",
  142. .flags = IORESOURCE_MEM
  143. }
  144. };
  145. static struct platform_nand_data rb532_nand_data = {
  146. .ctrl.dev_ready = rb532_dev_ready,
  147. .ctrl.cmd_ctrl = rb532_cmd_ctrl,
  148. };
  149. static struct platform_device nand_slot0 = {
  150. .name = "gen_nand",
  151. .id = -1,
  152. .resource = nand_slot0_res,
  153. .num_resources = ARRAY_SIZE(nand_slot0_res),
  154. .dev.platform_data = &rb532_nand_data,
  155. };
  156. static struct mtd_partition rb532_partition_info[] = {
  157. {
  158. .name = "Routerboard NAND boot",
  159. .offset = 0,
  160. .size = 4 * 1024 * 1024,
  161. }, {
  162. .name = "rootfs",
  163. .offset = MTDPART_OFS_NXTBLK,
  164. .size = MTDPART_SIZ_FULL,
  165. }
  166. };
  167. static struct platform_device rb532_led = {
  168. .name = "rb532-led",
  169. .id = -1,
  170. };
  171. static struct platform_device rb532_button = {
  172. .name = "rb532-button",
  173. .id = -1,
  174. };
  175. static struct resource rb532_wdt_res[] = {
  176. {
  177. .name = "rb532_wdt_res",
  178. .start = INTEG0_BASE_ADDR,
  179. .end = INTEG0_BASE_ADDR + sizeof(struct integ),
  180. .flags = IORESOURCE_MEM,
  181. }
  182. };
  183. static struct platform_device rb532_wdt = {
  184. .name = "rc32434_wdt",
  185. .id = -1,
  186. .resource = rb532_wdt_res,
  187. .num_resources = ARRAY_SIZE(rb532_wdt_res),
  188. };
  189. static struct plat_serial8250_port rb532_uart_res[] = {
  190. {
  191. .type = PORT_16550A,
  192. .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
  193. .irq = UART0_IRQ,
  194. .regshift = 2,
  195. .iotype = UPIO_MEM,
  196. .flags = UPF_BOOT_AUTOCONF,
  197. },
  198. {
  199. .flags = 0,
  200. }
  201. };
  202. static struct platform_device rb532_uart = {
  203. .name = "serial8250",
  204. .id = PLAT8250_DEV_PLATFORM,
  205. .dev.platform_data = &rb532_uart_res,
  206. };
  207. static struct platform_device *rb532_devs[] = {
  208. &korina_dev0,
  209. &nand_slot0,
  210. &cf_slot0,
  211. &rb532_led,
  212. &rb532_button,
  213. &rb532_uart,
  214. &rb532_wdt
  215. };
  216. /* NAND definitions */
  217. #define NAND_CHIP_DELAY 25
  218. static void __init rb532_nand_setup(void)
  219. {
  220. switch (mips_machtype) {
  221. case MACH_MIKROTIK_RB532A:
  222. set_latch_u5(LO_FOFF | LO_CEX,
  223. LO_ULED | LO_ALE | LO_CLE | LO_WPX);
  224. break;
  225. default:
  226. set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
  227. LO_ULED | LO_ALE | LO_CLE);
  228. break;
  229. }
  230. /* Setup NAND specific settings */
  231. rb532_nand_data.chip.nr_chips = 1;
  232. rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
  233. rb532_nand_data.chip.partitions = rb532_partition_info;
  234. rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
  235. }
  236. static int __init plat_setup_devices(void)
  237. {
  238. /* Look for the CF card reader */
  239. if (!readl(IDT434_REG_BASE + DEV1MASK))
  240. rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
  241. else {
  242. cf_slot0_res[0].start =
  243. readl(IDT434_REG_BASE + DEV1BASE);
  244. cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
  245. }
  246. /* Read the NAND resources from the device controller */
  247. nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
  248. nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
  249. /* Read and map device controller 3 */
  250. dev3.base = ioremap(readl(IDT434_REG_BASE + DEV3BASE), 1);
  251. if (!dev3.base) {
  252. printk(KERN_ERR "rb532: cannot remap device controller 3\n");
  253. return -ENXIO;
  254. }
  255. /* Initialise the NAND device */
  256. rb532_nand_setup();
  257. /* set the uart clock to the current cpu frequency */
  258. rb532_uart_res[0].uartclk = idt_cpu_freq;
  259. dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
  260. gpiod_add_lookup_table(&cf_slot0_gpio_table);
  261. return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
  262. }
  263. #ifdef CONFIG_NET
  264. static int __init setup_kmac(char *s)
  265. {
  266. printk(KERN_INFO "korina mac = %s\n", s);
  267. if (!mac_pton(s, korina_dev0_data.mac))
  268. printk(KERN_ERR "Invalid mac\n");
  269. return 1;
  270. }
  271. __setup("kmac=", setup_kmac);
  272. #endif /* CONFIG_NET */
  273. arch_initcall(plat_setup_devices);