irq.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2013 John Crispin <john@phrozen.org>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/bitops.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/interrupt.h>
  14. #include <asm/irq_cpu.h>
  15. #include <asm/mipsregs.h>
  16. #include "common.h"
  17. #define INTC_INT_GLOBAL BIT(31)
  18. #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
  19. #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
  20. #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
  21. #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
  22. #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
  23. /* we have a cascade of 8 irqs */
  24. #define RALINK_INTC_IRQ_BASE 8
  25. /* we have 32 SoC irqs */
  26. #define RALINK_INTC_IRQ_COUNT 32
  27. #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
  28. enum rt_intc_regs_enum {
  29. INTC_REG_STATUS0 = 0,
  30. INTC_REG_STATUS1,
  31. INTC_REG_TYPE,
  32. INTC_REG_RAW_STATUS,
  33. INTC_REG_ENABLE,
  34. INTC_REG_DISABLE,
  35. };
  36. static u32 rt_intc_regs[] = {
  37. [INTC_REG_STATUS0] = 0x00,
  38. [INTC_REG_STATUS1] = 0x04,
  39. [INTC_REG_TYPE] = 0x20,
  40. [INTC_REG_RAW_STATUS] = 0x30,
  41. [INTC_REG_ENABLE] = 0x34,
  42. [INTC_REG_DISABLE] = 0x38,
  43. };
  44. static void __iomem *rt_intc_membase;
  45. static int rt_perfcount_irq;
  46. static inline void rt_intc_w32(u32 val, unsigned reg)
  47. {
  48. __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
  49. }
  50. static inline u32 rt_intc_r32(unsigned reg)
  51. {
  52. return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
  53. }
  54. static void ralink_intc_irq_unmask(struct irq_data *d)
  55. {
  56. rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
  57. }
  58. static void ralink_intc_irq_mask(struct irq_data *d)
  59. {
  60. rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
  61. }
  62. static struct irq_chip ralink_intc_irq_chip = {
  63. .name = "INTC",
  64. .irq_unmask = ralink_intc_irq_unmask,
  65. .irq_mask = ralink_intc_irq_mask,
  66. .irq_mask_ack = ralink_intc_irq_mask,
  67. };
  68. int get_c0_perfcount_int(void)
  69. {
  70. return rt_perfcount_irq;
  71. }
  72. EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
  73. unsigned int get_c0_compare_int(void)
  74. {
  75. return CP0_LEGACY_COMPARE_IRQ;
  76. }
  77. static void ralink_intc_irq_handler(struct irq_desc *desc)
  78. {
  79. u32 pending = rt_intc_r32(INTC_REG_STATUS0);
  80. if (pending) {
  81. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  82. generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
  83. } else {
  84. spurious_interrupt();
  85. }
  86. }
  87. asmlinkage void plat_irq_dispatch(void)
  88. {
  89. unsigned long pending;
  90. pending = read_c0_status() & read_c0_cause() & ST0_IM;
  91. if (pending & STATUSF_IP7)
  92. do_IRQ(RALINK_CPU_IRQ_COUNTER);
  93. else if (pending & STATUSF_IP5)
  94. do_IRQ(RALINK_CPU_IRQ_FE);
  95. else if (pending & STATUSF_IP6)
  96. do_IRQ(RALINK_CPU_IRQ_WIFI);
  97. else if (pending & STATUSF_IP4)
  98. do_IRQ(RALINK_CPU_IRQ_PCI);
  99. else if (pending & STATUSF_IP2)
  100. do_IRQ(RALINK_CPU_IRQ_INTC);
  101. else
  102. spurious_interrupt();
  103. }
  104. static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  105. {
  106. irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
  107. return 0;
  108. }
  109. static const struct irq_domain_ops irq_domain_ops = {
  110. .xlate = irq_domain_xlate_onecell,
  111. .map = intc_map,
  112. };
  113. static int __init intc_of_init(struct device_node *node,
  114. struct device_node *parent)
  115. {
  116. struct resource res;
  117. struct irq_domain *domain;
  118. int irq;
  119. if (!of_property_read_u32_array(node, "ralink,intc-registers",
  120. rt_intc_regs, 6))
  121. pr_info("intc: using register map from devicetree\n");
  122. irq = irq_of_parse_and_map(node, 0);
  123. if (!irq)
  124. panic("Failed to get INTC IRQ");
  125. if (of_address_to_resource(node, 0, &res))
  126. panic("Failed to get intc memory range");
  127. if (!request_mem_region(res.start, resource_size(&res),
  128. res.name))
  129. pr_err("Failed to request intc memory");
  130. rt_intc_membase = ioremap(res.start,
  131. resource_size(&res));
  132. if (!rt_intc_membase)
  133. panic("Failed to remap intc memory");
  134. /* disable all interrupts */
  135. rt_intc_w32(~0, INTC_REG_DISABLE);
  136. /* route all INTC interrupts to MIPS HW0 interrupt */
  137. rt_intc_w32(0, INTC_REG_TYPE);
  138. domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
  139. RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
  140. if (!domain)
  141. panic("Failed to add irqdomain");
  142. rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
  143. irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain);
  144. /* tell the kernel which irq is used for performance monitoring */
  145. rt_perfcount_irq = irq_create_mapping(domain, 9);
  146. return 0;
  147. }
  148. static struct of_device_id __initdata of_irq_ids[] = {
  149. { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
  150. { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
  151. {},
  152. };
  153. void __init arch_init_irq(void)
  154. {
  155. of_irq_init(of_irq_ids);
  156. }