pcie-octeon.c 67 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/pci.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/time.h>
  13. #include <linux/delay.h>
  14. #include <linux/moduleparam.h>
  15. #include <asm/octeon/octeon.h>
  16. #include <asm/octeon/cvmx-npei-defs.h>
  17. #include <asm/octeon/cvmx-pciercx-defs.h>
  18. #include <asm/octeon/cvmx-pescx-defs.h>
  19. #include <asm/octeon/cvmx-pexp-defs.h>
  20. #include <asm/octeon/cvmx-pemx-defs.h>
  21. #include <asm/octeon/cvmx-dpi-defs.h>
  22. #include <asm/octeon/cvmx-sli-defs.h>
  23. #include <asm/octeon/cvmx-sriox-defs.h>
  24. #include <asm/octeon/cvmx-helper-errata.h>
  25. #include <asm/octeon/pci-octeon.h>
  26. #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
  27. #define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
  28. #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
  29. #define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
  30. /* Module parameter to disable PCI probing */
  31. static int pcie_disable;
  32. module_param(pcie_disable, int, S_IRUGO);
  33. static int enable_pcie_14459_war;
  34. static int enable_pcie_bus_num_war[2];
  35. union cvmx_pcie_address {
  36. uint64_t u64;
  37. struct {
  38. uint64_t upper:2; /* Normally 2 for XKPHYS */
  39. uint64_t reserved_49_61:13; /* Must be zero */
  40. uint64_t io:1; /* 1 for IO space access */
  41. uint64_t did:5; /* PCIe DID = 3 */
  42. uint64_t subdid:3; /* PCIe SubDID = 1 */
  43. uint64_t reserved_36_39:4; /* Must be zero */
  44. uint64_t es:2; /* Endian swap = 1 */
  45. uint64_t port:2; /* PCIe port 0,1 */
  46. uint64_t reserved_29_31:3; /* Must be zero */
  47. /*
  48. * Selects the type of the configuration request (0 = type 0,
  49. * 1 = type 1).
  50. */
  51. uint64_t ty:1;
  52. /* Target bus number sent in the ID in the request. */
  53. uint64_t bus:8;
  54. /*
  55. * Target device number sent in the ID in the
  56. * request. Note that Dev must be zero for type 0
  57. * configuration requests.
  58. */
  59. uint64_t dev:5;
  60. /* Target function number sent in the ID in the request. */
  61. uint64_t func:3;
  62. /*
  63. * Selects a register in the configuration space of
  64. * the target.
  65. */
  66. uint64_t reg:12;
  67. } config;
  68. struct {
  69. uint64_t upper:2; /* Normally 2 for XKPHYS */
  70. uint64_t reserved_49_61:13; /* Must be zero */
  71. uint64_t io:1; /* 1 for IO space access */
  72. uint64_t did:5; /* PCIe DID = 3 */
  73. uint64_t subdid:3; /* PCIe SubDID = 2 */
  74. uint64_t reserved_36_39:4; /* Must be zero */
  75. uint64_t es:2; /* Endian swap = 1 */
  76. uint64_t port:2; /* PCIe port 0,1 */
  77. uint64_t address:32; /* PCIe IO address */
  78. } io;
  79. struct {
  80. uint64_t upper:2; /* Normally 2 for XKPHYS */
  81. uint64_t reserved_49_61:13; /* Must be zero */
  82. uint64_t io:1; /* 1 for IO space access */
  83. uint64_t did:5; /* PCIe DID = 3 */
  84. uint64_t subdid:3; /* PCIe SubDID = 3-6 */
  85. uint64_t reserved_36_39:4; /* Must be zero */
  86. uint64_t address:36; /* PCIe Mem address */
  87. } mem;
  88. };
  89. static int cvmx_pcie_rc_initialize(int pcie_port);
  90. /**
  91. * Return the Core virtual base address for PCIe IO access. IOs are
  92. * read/written as an offset from this address.
  93. *
  94. * @pcie_port: PCIe port the IO is for
  95. *
  96. * Returns 64bit Octeon IO base address for read/write
  97. */
  98. static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
  99. {
  100. union cvmx_pcie_address pcie_addr;
  101. pcie_addr.u64 = 0;
  102. pcie_addr.io.upper = 0;
  103. pcie_addr.io.io = 1;
  104. pcie_addr.io.did = 3;
  105. pcie_addr.io.subdid = 2;
  106. pcie_addr.io.es = 1;
  107. pcie_addr.io.port = pcie_port;
  108. return pcie_addr.u64;
  109. }
  110. /**
  111. * Size of the IO address region returned at address
  112. * cvmx_pcie_get_io_base_address()
  113. *
  114. * @pcie_port: PCIe port the IO is for
  115. *
  116. * Returns Size of the IO window
  117. */
  118. static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
  119. {
  120. return 1ull << 32;
  121. }
  122. /**
  123. * Return the Core virtual base address for PCIe MEM access. Memory is
  124. * read/written as an offset from this address.
  125. *
  126. * @pcie_port: PCIe port the IO is for
  127. *
  128. * Returns 64bit Octeon IO base address for read/write
  129. */
  130. static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
  131. {
  132. union cvmx_pcie_address pcie_addr;
  133. pcie_addr.u64 = 0;
  134. pcie_addr.mem.upper = 0;
  135. pcie_addr.mem.io = 1;
  136. pcie_addr.mem.did = 3;
  137. pcie_addr.mem.subdid = 3 + pcie_port;
  138. return pcie_addr.u64;
  139. }
  140. /**
  141. * Size of the Mem address region returned at address
  142. * cvmx_pcie_get_mem_base_address()
  143. *
  144. * @pcie_port: PCIe port the IO is for
  145. *
  146. * Returns Size of the Mem window
  147. */
  148. static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
  149. {
  150. return 1ull << 36;
  151. }
  152. /**
  153. * Read a PCIe config space register indirectly. This is used for
  154. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  155. *
  156. * @pcie_port: PCIe port to read from
  157. * @cfg_offset: Address to read
  158. *
  159. * Returns Value read
  160. */
  161. static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
  162. {
  163. if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
  164. union cvmx_pescx_cfg_rd pescx_cfg_rd;
  165. pescx_cfg_rd.u64 = 0;
  166. pescx_cfg_rd.s.addr = cfg_offset;
  167. cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
  168. pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
  169. return pescx_cfg_rd.s.data;
  170. } else {
  171. union cvmx_pemx_cfg_rd pemx_cfg_rd;
  172. pemx_cfg_rd.u64 = 0;
  173. pemx_cfg_rd.s.addr = cfg_offset;
  174. cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
  175. pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
  176. return pemx_cfg_rd.s.data;
  177. }
  178. }
  179. /**
  180. * Write a PCIe config space register indirectly. This is used for
  181. * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  182. *
  183. * @pcie_port: PCIe port to write to
  184. * @cfg_offset: Address to write
  185. * @val: Value to write
  186. */
  187. static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
  188. uint32_t val)
  189. {
  190. if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
  191. union cvmx_pescx_cfg_wr pescx_cfg_wr;
  192. pescx_cfg_wr.u64 = 0;
  193. pescx_cfg_wr.s.addr = cfg_offset;
  194. pescx_cfg_wr.s.data = val;
  195. cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
  196. } else {
  197. union cvmx_pemx_cfg_wr pemx_cfg_wr;
  198. pemx_cfg_wr.u64 = 0;
  199. pemx_cfg_wr.s.addr = cfg_offset;
  200. pemx_cfg_wr.s.data = val;
  201. cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
  202. }
  203. }
  204. /**
  205. * Build a PCIe config space request address for a device
  206. *
  207. * @pcie_port: PCIe port to access
  208. * @bus: Sub bus
  209. * @dev: Device ID
  210. * @fn: Device sub function
  211. * @reg: Register to access
  212. *
  213. * Returns 64bit Octeon IO address
  214. */
  215. static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
  216. int dev, int fn, int reg)
  217. {
  218. union cvmx_pcie_address pcie_addr;
  219. union cvmx_pciercx_cfg006 pciercx_cfg006;
  220. pciercx_cfg006.u32 =
  221. cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
  222. if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
  223. return 0;
  224. pcie_addr.u64 = 0;
  225. pcie_addr.config.upper = 2;
  226. pcie_addr.config.io = 1;
  227. pcie_addr.config.did = 3;
  228. pcie_addr.config.subdid = 1;
  229. pcie_addr.config.es = 1;
  230. pcie_addr.config.port = pcie_port;
  231. pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
  232. pcie_addr.config.bus = bus;
  233. pcie_addr.config.dev = dev;
  234. pcie_addr.config.func = fn;
  235. pcie_addr.config.reg = reg;
  236. return pcie_addr.u64;
  237. }
  238. /**
  239. * Read 8bits from a Device's config space
  240. *
  241. * @pcie_port: PCIe port the device is on
  242. * @bus: Sub bus
  243. * @dev: Device ID
  244. * @fn: Device sub function
  245. * @reg: Register to access
  246. *
  247. * Returns Result of the read
  248. */
  249. static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
  250. int fn, int reg)
  251. {
  252. uint64_t address =
  253. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  254. if (address)
  255. return cvmx_read64_uint8(address);
  256. else
  257. return 0xff;
  258. }
  259. /**
  260. * Read 16bits from a Device's config space
  261. *
  262. * @pcie_port: PCIe port the device is on
  263. * @bus: Sub bus
  264. * @dev: Device ID
  265. * @fn: Device sub function
  266. * @reg: Register to access
  267. *
  268. * Returns Result of the read
  269. */
  270. static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
  271. int fn, int reg)
  272. {
  273. uint64_t address =
  274. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  275. if (address)
  276. return le16_to_cpu(cvmx_read64_uint16(address));
  277. else
  278. return 0xffff;
  279. }
  280. /**
  281. * Read 32bits from a Device's config space
  282. *
  283. * @pcie_port: PCIe port the device is on
  284. * @bus: Sub bus
  285. * @dev: Device ID
  286. * @fn: Device sub function
  287. * @reg: Register to access
  288. *
  289. * Returns Result of the read
  290. */
  291. static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
  292. int fn, int reg)
  293. {
  294. uint64_t address =
  295. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  296. if (address)
  297. return le32_to_cpu(cvmx_read64_uint32(address));
  298. else
  299. return 0xffffffff;
  300. }
  301. /**
  302. * Write 8bits to a Device's config space
  303. *
  304. * @pcie_port: PCIe port the device is on
  305. * @bus: Sub bus
  306. * @dev: Device ID
  307. * @fn: Device sub function
  308. * @reg: Register to access
  309. * @val: Value to write
  310. */
  311. static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
  312. int reg, uint8_t val)
  313. {
  314. uint64_t address =
  315. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  316. if (address)
  317. cvmx_write64_uint8(address, val);
  318. }
  319. /**
  320. * Write 16bits to a Device's config space
  321. *
  322. * @pcie_port: PCIe port the device is on
  323. * @bus: Sub bus
  324. * @dev: Device ID
  325. * @fn: Device sub function
  326. * @reg: Register to access
  327. * @val: Value to write
  328. */
  329. static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
  330. int reg, uint16_t val)
  331. {
  332. uint64_t address =
  333. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  334. if (address)
  335. cvmx_write64_uint16(address, cpu_to_le16(val));
  336. }
  337. /**
  338. * Write 32bits to a Device's config space
  339. *
  340. * @pcie_port: PCIe port the device is on
  341. * @bus: Sub bus
  342. * @dev: Device ID
  343. * @fn: Device sub function
  344. * @reg: Register to access
  345. * @val: Value to write
  346. */
  347. static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
  348. int reg, uint32_t val)
  349. {
  350. uint64_t address =
  351. __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
  352. if (address)
  353. cvmx_write64_uint32(address, cpu_to_le32(val));
  354. }
  355. /**
  356. * Initialize the RC config space CSRs
  357. *
  358. * @pcie_port: PCIe port to initialize
  359. */
  360. static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
  361. {
  362. union cvmx_pciercx_cfg030 pciercx_cfg030;
  363. union cvmx_pciercx_cfg070 pciercx_cfg070;
  364. union cvmx_pciercx_cfg001 pciercx_cfg001;
  365. union cvmx_pciercx_cfg032 pciercx_cfg032;
  366. union cvmx_pciercx_cfg006 pciercx_cfg006;
  367. union cvmx_pciercx_cfg008 pciercx_cfg008;
  368. union cvmx_pciercx_cfg009 pciercx_cfg009;
  369. union cvmx_pciercx_cfg010 pciercx_cfg010;
  370. union cvmx_pciercx_cfg011 pciercx_cfg011;
  371. union cvmx_pciercx_cfg035 pciercx_cfg035;
  372. union cvmx_pciercx_cfg075 pciercx_cfg075;
  373. union cvmx_pciercx_cfg034 pciercx_cfg034;
  374. /* Max Payload Size (PCIE*_CFG030[MPS]) */
  375. /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
  376. /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
  377. /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
  378. pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
  379. if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
  380. pciercx_cfg030.s.mps = MPS_CN5XXX;
  381. pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
  382. } else {
  383. pciercx_cfg030.s.mps = MPS_CN6XXX;
  384. pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
  385. }
  386. /*
  387. * Enable relaxed order processing. This will allow devices to
  388. * affect read response ordering.
  389. */
  390. pciercx_cfg030.s.ro_en = 1;
  391. /* Enable no snoop processing. Not used by Octeon */
  392. pciercx_cfg030.s.ns_en = 1;
  393. /* Correctable error reporting enable. */
  394. pciercx_cfg030.s.ce_en = 1;
  395. /* Non-fatal error reporting enable. */
  396. pciercx_cfg030.s.nfe_en = 1;
  397. /* Fatal error reporting enable. */
  398. pciercx_cfg030.s.fe_en = 1;
  399. /* Unsupported request reporting enable. */
  400. pciercx_cfg030.s.ur_en = 1;
  401. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
  402. if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
  403. union cvmx_npei_ctl_status2 npei_ctl_status2;
  404. /*
  405. * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
  406. * PCIE*_CFG030[MPS]. Max Read Request Size
  407. * (NPEI_CTL_STATUS2[MRRS]) must not exceed
  408. * PCIE*_CFG030[MRRS]
  409. */
  410. npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
  411. /* Max payload size = 128 bytes for best Octeon DMA performance */
  412. npei_ctl_status2.s.mps = MPS_CN5XXX;
  413. /* Max read request size = 128 bytes for best Octeon DMA performance */
  414. npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
  415. if (pcie_port)
  416. npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
  417. else
  418. npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
  419. cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
  420. } else {
  421. /*
  422. * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
  423. * PCIE*_CFG030[MPS]. Max Read Request Size
  424. * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
  425. * PCIE*_CFG030[MRRS].
  426. */
  427. union cvmx_dpi_sli_prtx_cfg prt_cfg;
  428. union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
  429. prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
  430. prt_cfg.s.mps = MPS_CN6XXX;
  431. prt_cfg.s.mrrs = MRRS_CN6XXX;
  432. /* Max outstanding load request. */
  433. prt_cfg.s.molr = 32;
  434. cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
  435. sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
  436. sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
  437. cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
  438. }
  439. /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
  440. pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
  441. pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
  442. pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
  443. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
  444. /*
  445. * Access Enables (PCIE*_CFG001[MSAE,ME])
  446. * ME and MSAE should always be set.
  447. * Interrupt Disable (PCIE*_CFG001[I_DIS])
  448. * System Error Message Enable (PCIE*_CFG001[SEE])
  449. */
  450. pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
  451. pciercx_cfg001.s.msae = 1; /* Memory space enable. */
  452. pciercx_cfg001.s.me = 1; /* Bus master enable. */
  453. pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
  454. pciercx_cfg001.s.see = 1; /* SERR# enable */
  455. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
  456. /* Advanced Error Recovery Message Enables */
  457. /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
  458. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
  459. /* Use CVMX_PCIERCX_CFG067 hardware default */
  460. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
  461. /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
  462. pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  463. pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
  464. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
  465. /*
  466. * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
  467. * cvmx_pcie_rc_initialize_link()
  468. *
  469. * Primary Bus Number (PCIERCn_CFG006[PBNUM])
  470. *
  471. * We set the primary bus number to 1 so IDT bridges are
  472. * happy. They don't like zero.
  473. */
  474. pciercx_cfg006.u32 = 0;
  475. pciercx_cfg006.s.pbnum = 1;
  476. pciercx_cfg006.s.sbnum = 1;
  477. pciercx_cfg006.s.subbnum = 1;
  478. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
  479. /*
  480. * Memory-mapped I/O BAR (PCIERCn_CFG008)
  481. * Most applications should disable the memory-mapped I/O BAR by
  482. * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
  483. */
  484. pciercx_cfg008.u32 = 0;
  485. pciercx_cfg008.s.mb_addr = 0x100;
  486. pciercx_cfg008.s.ml_addr = 0;
  487. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
  488. /*
  489. * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
  490. * Most applications should disable the prefetchable BAR by setting
  491. * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
  492. * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
  493. */
  494. pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
  495. pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
  496. pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
  497. pciercx_cfg009.s.lmem_base = 0x100;
  498. pciercx_cfg009.s.lmem_limit = 0;
  499. pciercx_cfg010.s.umem_base = 0x100;
  500. pciercx_cfg011.s.umem_limit = 0;
  501. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
  502. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
  503. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
  504. /*
  505. * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
  506. * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
  507. */
  508. pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
  509. pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
  510. pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
  511. pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
  512. pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
  513. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
  514. /*
  515. * Advanced Error Recovery Interrupt Enables
  516. * (PCIERCn_CFG075[CERE,NFERE,FERE])
  517. */
  518. pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
  519. pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
  520. pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
  521. pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
  522. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
  523. /*
  524. * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
  525. * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
  526. */
  527. pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
  528. pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
  529. pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
  530. pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
  531. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
  532. }
  533. /**
  534. * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
  535. * port from reset to a link up state. Software can then begin
  536. * configuring the rest of the link.
  537. *
  538. * @pcie_port: PCIe port to initialize
  539. *
  540. * Returns Zero on success
  541. */
  542. static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
  543. {
  544. uint64_t start_cycle;
  545. union cvmx_pescx_ctl_status pescx_ctl_status;
  546. union cvmx_pciercx_cfg452 pciercx_cfg452;
  547. union cvmx_pciercx_cfg032 pciercx_cfg032;
  548. union cvmx_pciercx_cfg448 pciercx_cfg448;
  549. /* Set the lane width */
  550. pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
  551. pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
  552. if (pescx_ctl_status.s.qlm_cfg == 0)
  553. /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
  554. pciercx_cfg452.s.lme = 0xf;
  555. else
  556. /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
  557. pciercx_cfg452.s.lme = 0x7;
  558. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
  559. /*
  560. * CN52XX pass 1.x has an errata where length mismatches on UR
  561. * responses can cause bus errors on 64bit memory
  562. * reads. Turning off length error checking fixes this.
  563. */
  564. if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
  565. union cvmx_pciercx_cfg455 pciercx_cfg455;
  566. pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
  567. pciercx_cfg455.s.m_cpl_len_err = 1;
  568. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
  569. }
  570. /* Lane swap needs to be manually enabled for CN52XX */
  571. if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
  572. pescx_ctl_status.s.lane_swp = 1;
  573. cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
  574. }
  575. /* Bring up the link */
  576. pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
  577. pescx_ctl_status.s.lnk_enb = 1;
  578. cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
  579. /*
  580. * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
  581. * be disabled.
  582. */
  583. if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
  584. __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
  585. /* Wait for the link to come up */
  586. start_cycle = cvmx_get_cycle();
  587. do {
  588. if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
  589. cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
  590. return -1;
  591. }
  592. __delay(10000);
  593. pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  594. } while (pciercx_cfg032.s.dlla == 0);
  595. /* Clear all pending errors */
  596. cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
  597. /*
  598. * Update the Replay Time Limit. Empirically, some PCIe
  599. * devices take a little longer to respond than expected under
  600. * load. As a workaround for this we configure the Replay Time
  601. * Limit to the value expected for a 512 byte MPS instead of
  602. * our actual 256 byte MPS. The numbers below are directly
  603. * from the PCIe spec table 3-4.
  604. */
  605. pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
  606. switch (pciercx_cfg032.s.nlw) {
  607. case 1: /* 1 lane */
  608. pciercx_cfg448.s.rtl = 1677;
  609. break;
  610. case 2: /* 2 lanes */
  611. pciercx_cfg448.s.rtl = 867;
  612. break;
  613. case 4: /* 4 lanes */
  614. pciercx_cfg448.s.rtl = 462;
  615. break;
  616. case 8: /* 8 lanes */
  617. pciercx_cfg448.s.rtl = 258;
  618. break;
  619. }
  620. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
  621. return 0;
  622. }
  623. static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
  624. {
  625. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  626. pmas->cn68xx.ba++;
  627. else
  628. pmas->s.ba++;
  629. }
  630. /**
  631. * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
  632. * enumerate the bus.
  633. *
  634. * @pcie_port: PCIe port to initialize
  635. *
  636. * Returns Zero on success
  637. */
  638. static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
  639. {
  640. int i;
  641. int base;
  642. u64 addr_swizzle;
  643. union cvmx_ciu_soft_prst ciu_soft_prst;
  644. union cvmx_pescx_bist_status pescx_bist_status;
  645. union cvmx_pescx_bist_status2 pescx_bist_status2;
  646. union cvmx_npei_ctl_status npei_ctl_status;
  647. union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
  648. union cvmx_npei_mem_access_subidx mem_access_subid;
  649. union cvmx_npei_dbg_data npei_dbg_data;
  650. union cvmx_pescx_ctl_status2 pescx_ctl_status2;
  651. union cvmx_pciercx_cfg032 pciercx_cfg032;
  652. union cvmx_npei_bar1_indexx bar1_index;
  653. retry:
  654. /*
  655. * Make sure we aren't trying to setup a target mode interface
  656. * in host mode.
  657. */
  658. npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
  659. if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
  660. cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
  661. return -1;
  662. }
  663. /*
  664. * Make sure a CN52XX isn't trying to bring up port 1 when it
  665. * is disabled.
  666. */
  667. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  668. npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
  669. if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
  670. cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
  671. return -1;
  672. }
  673. }
  674. /*
  675. * PCIe switch arbitration mode. '0' == fixed priority NPEI,
  676. * PCIe0, then PCIe1. '1' == round robin.
  677. */
  678. npei_ctl_status.s.arb = 1;
  679. /* Allow up to 0x20 config retries */
  680. npei_ctl_status.s.cfg_rtry = 0x20;
  681. /*
  682. * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
  683. * don't reset.
  684. */
  685. if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
  686. npei_ctl_status.s.p0_ntags = 0x20;
  687. npei_ctl_status.s.p1_ntags = 0x20;
  688. }
  689. cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
  690. /* Bring the PCIe out of reset */
  691. if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
  692. /*
  693. * The EBH5200 board swapped the PCIe reset lines on
  694. * the board. As a workaround for this bug, we bring
  695. * both PCIe ports out of reset at the same time
  696. * instead of on separate calls. So for port 0, we
  697. * bring both out of reset and do nothing on port 1
  698. */
  699. if (pcie_port == 0) {
  700. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  701. /*
  702. * After a chip reset the PCIe will also be in
  703. * reset. If it isn't, most likely someone is
  704. * trying to init it again without a proper
  705. * PCIe reset.
  706. */
  707. if (ciu_soft_prst.s.soft_prst == 0) {
  708. /* Reset the ports */
  709. ciu_soft_prst.s.soft_prst = 1;
  710. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  711. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  712. ciu_soft_prst.s.soft_prst = 1;
  713. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  714. /* Wait until pcie resets the ports. */
  715. udelay(2000);
  716. }
  717. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  718. ciu_soft_prst.s.soft_prst = 0;
  719. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  720. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  721. ciu_soft_prst.s.soft_prst = 0;
  722. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  723. }
  724. } else {
  725. /*
  726. * The normal case: The PCIe ports are completely
  727. * separate and can be brought out of reset
  728. * independently.
  729. */
  730. if (pcie_port)
  731. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  732. else
  733. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  734. /*
  735. * After a chip reset the PCIe will also be in
  736. * reset. If it isn't, most likely someone is trying
  737. * to init it again without a proper PCIe reset.
  738. */
  739. if (ciu_soft_prst.s.soft_prst == 0) {
  740. /* Reset the port */
  741. ciu_soft_prst.s.soft_prst = 1;
  742. if (pcie_port)
  743. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  744. else
  745. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  746. /* Wait until pcie resets the ports. */
  747. udelay(2000);
  748. }
  749. if (pcie_port) {
  750. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  751. ciu_soft_prst.s.soft_prst = 0;
  752. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  753. } else {
  754. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  755. ciu_soft_prst.s.soft_prst = 0;
  756. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  757. }
  758. }
  759. /*
  760. * Wait for PCIe reset to complete. Due to errata PCIE-700, we
  761. * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
  762. * fixed number of cycles.
  763. */
  764. __delay(400000);
  765. /*
  766. * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
  767. * CN56XX and CN52XX, so we only probe it on newer chips
  768. */
  769. if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
  770. /* Clear PCLK_RUN so we can check if the clock is running */
  771. pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
  772. pescx_ctl_status2.s.pclk_run = 1;
  773. cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
  774. /* Now that we cleared PCLK_RUN, wait for it to be set
  775. * again telling us the clock is running
  776. */
  777. if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
  778. union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
  779. cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
  780. return -1;
  781. }
  782. }
  783. /*
  784. * Check and make sure PCIe came out of reset. If it doesn't
  785. * the board probably hasn't wired the clocks up and the
  786. * interface should be skipped.
  787. */
  788. pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
  789. if (pescx_ctl_status2.s.pcierst) {
  790. cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
  791. return -1;
  792. }
  793. /*
  794. * Check BIST2 status. If any bits are set skip this
  795. * interface. This is an attempt to catch PCIE-813 on pass 1
  796. * parts.
  797. */
  798. pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
  799. if (pescx_bist_status2.u64) {
  800. cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
  801. pcie_port);
  802. return -1;
  803. }
  804. /* Check BIST status */
  805. pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
  806. if (pescx_bist_status.u64)
  807. cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
  808. pcie_port, CAST64(pescx_bist_status.u64));
  809. /* Initialize the config space CSRs */
  810. __cvmx_pcie_rc_initialize_config_space(pcie_port);
  811. /* Bring the link up */
  812. if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
  813. cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
  814. pcie_port);
  815. return -1;
  816. }
  817. /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
  818. npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
  819. npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
  820. npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
  821. cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
  822. /* Setup Mem access SubDIDs */
  823. mem_access_subid.u64 = 0;
  824. mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
  825. mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
  826. mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
  827. mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
  828. mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
  829. mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
  830. mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
  831. mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
  832. mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
  833. /*
  834. * Setup mem access 12-15 for port 0, 16-19 for port 1,
  835. * supplying 36 bits of address space.
  836. */
  837. for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
  838. cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
  839. mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
  840. }
  841. /*
  842. * Disable the peer to peer forwarding register. This must be
  843. * setup by the OS after it enumerates the bus and assigns
  844. * addresses to the PCIe busses.
  845. */
  846. for (i = 0; i < 4; i++) {
  847. cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
  848. cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
  849. }
  850. /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
  851. cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
  852. /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
  853. cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
  854. bar1_index.u32 = 0;
  855. bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
  856. bar1_index.s.ca = 1; /* Not Cached */
  857. bar1_index.s.end_swp = 1; /* Endian Swap mode */
  858. bar1_index.s.addr_v = 1; /* Valid entry */
  859. base = pcie_port ? 16 : 0;
  860. /* Big endian swizzle for 32-bit PEXP_NCB register. */
  861. #ifdef __MIPSEB__
  862. addr_swizzle = 4;
  863. #else
  864. addr_swizzle = 0;
  865. #endif
  866. for (i = 0; i < 16; i++) {
  867. cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
  868. bar1_index.u32);
  869. base++;
  870. /* 256MB / 16 >> 22 == 4 */
  871. bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
  872. }
  873. /*
  874. * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
  875. * precedence where they overlap. It also overlaps with the
  876. * device addresses, so make sure the peer to peer forwarding
  877. * is set right.
  878. */
  879. cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
  880. /*
  881. * Setup BAR2 attributes
  882. *
  883. * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
  884. * - PTLP_RO,CTLP_RO should normally be set (except for debug).
  885. * - WAIT_COM=0 will likely work for all applications.
  886. *
  887. * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
  888. */
  889. if (pcie_port) {
  890. union cvmx_npei_ctl_port1 npei_ctl_port;
  891. npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
  892. npei_ctl_port.s.bar2_enb = 1;
  893. npei_ctl_port.s.bar2_esx = 1;
  894. npei_ctl_port.s.bar2_cax = 0;
  895. npei_ctl_port.s.ptlp_ro = 1;
  896. npei_ctl_port.s.ctlp_ro = 1;
  897. npei_ctl_port.s.wait_com = 0;
  898. npei_ctl_port.s.waitl_com = 0;
  899. cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
  900. } else {
  901. union cvmx_npei_ctl_port0 npei_ctl_port;
  902. npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
  903. npei_ctl_port.s.bar2_enb = 1;
  904. npei_ctl_port.s.bar2_esx = 1;
  905. npei_ctl_port.s.bar2_cax = 0;
  906. npei_ctl_port.s.ptlp_ro = 1;
  907. npei_ctl_port.s.ctlp_ro = 1;
  908. npei_ctl_port.s.wait_com = 0;
  909. npei_ctl_port.s.waitl_com = 0;
  910. cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
  911. }
  912. /*
  913. * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
  914. * that causes TLP ordering to not be preserved after multiple
  915. * PCIe port resets. This code detects this fault and corrects
  916. * it by aligning the TLP counters properly. Another link
  917. * reset is then performed. See PCIE-13340
  918. */
  919. if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
  920. OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
  921. OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
  922. OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
  923. union cvmx_npei_dbg_data dbg_data;
  924. int old_in_fif_p_count;
  925. int in_fif_p_count;
  926. int out_p_count;
  927. int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
  928. int i;
  929. /*
  930. * Choose a write address of 1MB. It should be
  931. * harmless as all bars haven't been setup.
  932. */
  933. uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
  934. /*
  935. * Make sure at least in_p_offset have been executed before we try and
  936. * read in_fif_p_count
  937. */
  938. i = in_p_offset;
  939. while (i--) {
  940. cvmx_write64_uint32(write_address, 0);
  941. __delay(10000);
  942. }
  943. /*
  944. * Read the IN_FIF_P_COUNT from the debug
  945. * select. IN_FIF_P_COUNT can be unstable sometimes so
  946. * read it twice with a write between the reads. This
  947. * way we can tell the value is good as it will
  948. * increment by one due to the write
  949. */
  950. cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
  951. cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
  952. do {
  953. dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
  954. old_in_fif_p_count = dbg_data.s.data & 0xff;
  955. cvmx_write64_uint32(write_address, 0);
  956. __delay(10000);
  957. dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
  958. in_fif_p_count = dbg_data.s.data & 0xff;
  959. } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
  960. /* Update in_fif_p_count for it's offset with respect to out_p_count */
  961. in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
  962. /* Read the OUT_P_COUNT from the debug select */
  963. cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
  964. cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
  965. dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
  966. out_p_count = (dbg_data.s.data>>1) & 0xff;
  967. /* Check that the two counters are aligned */
  968. if (out_p_count != in_fif_p_count) {
  969. cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
  970. while (in_fif_p_count != 0) {
  971. cvmx_write64_uint32(write_address, 0);
  972. __delay(10000);
  973. in_fif_p_count = (in_fif_p_count + 1) & 0xff;
  974. }
  975. /*
  976. * The EBH5200 board swapped the PCIe reset
  977. * lines on the board. This means we must
  978. * bring both links down and up, which will
  979. * cause the PCIe0 to need alignment
  980. * again. Lots of messages will be displayed,
  981. * but everything should work
  982. */
  983. if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
  984. (pcie_port == 1))
  985. cvmx_pcie_rc_initialize(0);
  986. /* Rety bringing this port up */
  987. goto retry;
  988. }
  989. }
  990. /* Display the link status */
  991. pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  992. cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
  993. return 0;
  994. }
  995. /**
  996. * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
  997. * port from reset to a link up state. Software can then begin
  998. * configuring the rest of the link.
  999. *
  1000. * @pcie_port: PCIe port to initialize
  1001. *
  1002. * Return Zero on success.
  1003. */
  1004. static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
  1005. {
  1006. uint64_t start_cycle;
  1007. union cvmx_pemx_ctl_status pem_ctl_status;
  1008. union cvmx_pciercx_cfg032 pciercx_cfg032;
  1009. union cvmx_pciercx_cfg448 pciercx_cfg448;
  1010. /* Bring up the link */
  1011. pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
  1012. pem_ctl_status.s.lnk_enb = 1;
  1013. cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
  1014. /* Wait for the link to come up */
  1015. start_cycle = cvmx_get_cycle();
  1016. do {
  1017. if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
  1018. return -1;
  1019. __delay(10000);
  1020. pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1021. } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
  1022. /*
  1023. * Update the Replay Time Limit. Empirically, some PCIe
  1024. * devices take a little longer to respond than expected under
  1025. * load. As a workaround for this we configure the Replay Time
  1026. * Limit to the value expected for a 512 byte MPS instead of
  1027. * our actual 256 byte MPS. The numbers below are directly
  1028. * from the PCIe spec table 3-4
  1029. */
  1030. pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
  1031. switch (pciercx_cfg032.s.nlw) {
  1032. case 1: /* 1 lane */
  1033. pciercx_cfg448.s.rtl = 1677;
  1034. break;
  1035. case 2: /* 2 lanes */
  1036. pciercx_cfg448.s.rtl = 867;
  1037. break;
  1038. case 4: /* 4 lanes */
  1039. pciercx_cfg448.s.rtl = 462;
  1040. break;
  1041. case 8: /* 8 lanes */
  1042. pciercx_cfg448.s.rtl = 258;
  1043. break;
  1044. }
  1045. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
  1046. return 0;
  1047. }
  1048. /**
  1049. * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
  1050. * the bus.
  1051. *
  1052. * @pcie_port: PCIe port to initialize
  1053. *
  1054. * Returns Zero on success.
  1055. */
  1056. static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
  1057. {
  1058. int i;
  1059. union cvmx_ciu_soft_prst ciu_soft_prst;
  1060. union cvmx_mio_rst_ctlx mio_rst_ctl;
  1061. union cvmx_pemx_bar_ctl pemx_bar_ctl;
  1062. union cvmx_pemx_ctl_status pemx_ctl_status;
  1063. union cvmx_pemx_bist_status pemx_bist_status;
  1064. union cvmx_pemx_bist_status2 pemx_bist_status2;
  1065. union cvmx_pciercx_cfg032 pciercx_cfg032;
  1066. union cvmx_pciercx_cfg515 pciercx_cfg515;
  1067. union cvmx_sli_ctl_portx sli_ctl_portx;
  1068. union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
  1069. union cvmx_sli_mem_access_subidx mem_access_subid;
  1070. union cvmx_sriox_status_reg sriox_status_reg;
  1071. union cvmx_pemx_bar1_indexx bar1_index;
  1072. if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
  1073. /* Make sure this interface isn't SRIO */
  1074. if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
  1075. /*
  1076. * The CN66XX requires reading the
  1077. * MIO_QLMX_CFG register to figure out the
  1078. * port type.
  1079. */
  1080. union cvmx_mio_qlmx_cfg qlmx_cfg;
  1081. qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
  1082. if (qlmx_cfg.s.qlm_spd == 15) {
  1083. pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
  1084. return -1;
  1085. }
  1086. switch (qlmx_cfg.s.qlm_spd) {
  1087. case 0x1: /* SRIO 1x4 short */
  1088. case 0x3: /* SRIO 1x4 long */
  1089. case 0x4: /* SRIO 2x2 short */
  1090. case 0x6: /* SRIO 2x2 long */
  1091. pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
  1092. return -1;
  1093. case 0x9: /* SGMII */
  1094. pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
  1095. return -1;
  1096. case 0xb: /* XAUI */
  1097. pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
  1098. return -1;
  1099. case 0x0: /* PCIE gen2 */
  1100. case 0x8: /* PCIE gen2 (alias) */
  1101. case 0x2: /* PCIE gen1 */
  1102. case 0xa: /* PCIE gen1 (alias) */
  1103. break;
  1104. default:
  1105. pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
  1106. return -1;
  1107. }
  1108. } else {
  1109. sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
  1110. if (sriox_status_reg.s.srio) {
  1111. pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
  1112. return -1;
  1113. }
  1114. }
  1115. }
  1116. #if 0
  1117. /* This code is so that the PCIe analyzer is able to see 63XX traffic */
  1118. pr_notice("PCIE : init for pcie analyzer.\n");
  1119. cvmx_helper_qlm_jtag_init();
  1120. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
  1121. cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
  1122. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
  1123. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
  1124. cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
  1125. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
  1126. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
  1127. cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
  1128. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
  1129. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
  1130. cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
  1131. cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
  1132. cvmx_helper_qlm_jtag_update(pcie_port);
  1133. #endif
  1134. /* Make sure we aren't trying to setup a target mode interface in host mode */
  1135. mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
  1136. if (!mio_rst_ctl.s.host_mode) {
  1137. pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
  1138. return -1;
  1139. }
  1140. /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
  1141. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
  1142. if (pcie_port) {
  1143. union cvmx_ciu_qlm ciu_qlm;
  1144. ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
  1145. ciu_qlm.s.txbypass = 1;
  1146. ciu_qlm.s.txdeemph = 5;
  1147. ciu_qlm.s.txmargin = 0x17;
  1148. cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
  1149. } else {
  1150. union cvmx_ciu_qlm ciu_qlm;
  1151. ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
  1152. ciu_qlm.s.txbypass = 1;
  1153. ciu_qlm.s.txdeemph = 5;
  1154. ciu_qlm.s.txmargin = 0x17;
  1155. cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
  1156. }
  1157. }
  1158. /* Bring the PCIe out of reset */
  1159. if (pcie_port)
  1160. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  1161. else
  1162. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  1163. /*
  1164. * After a chip reset the PCIe will also be in reset. If it
  1165. * isn't, most likely someone is trying to init it again
  1166. * without a proper PCIe reset
  1167. */
  1168. if (ciu_soft_prst.s.soft_prst == 0) {
  1169. /* Reset the port */
  1170. ciu_soft_prst.s.soft_prst = 1;
  1171. if (pcie_port)
  1172. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  1173. else
  1174. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  1175. /* Wait until pcie resets the ports. */
  1176. udelay(2000);
  1177. }
  1178. if (pcie_port) {
  1179. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
  1180. ciu_soft_prst.s.soft_prst = 0;
  1181. cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
  1182. } else {
  1183. ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
  1184. ciu_soft_prst.s.soft_prst = 0;
  1185. cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
  1186. }
  1187. /* Wait for PCIe reset to complete */
  1188. udelay(1000);
  1189. /*
  1190. * Check and make sure PCIe came out of reset. If it doesn't
  1191. * the board probably hasn't wired the clocks up and the
  1192. * interface should be skipped.
  1193. */
  1194. if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
  1195. pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
  1196. return -1;
  1197. }
  1198. /* Check BIST status */
  1199. pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
  1200. if (pemx_bist_status.u64)
  1201. pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
  1202. pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
  1203. /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
  1204. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
  1205. pemx_bist_status2.u64 &= ~0x3full;
  1206. if (pemx_bist_status2.u64)
  1207. pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
  1208. /* Initialize the config space CSRs */
  1209. __cvmx_pcie_rc_initialize_config_space(pcie_port);
  1210. /* Enable gen2 speed selection */
  1211. pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
  1212. pciercx_cfg515.s.dsc = 1;
  1213. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
  1214. /* Bring the link up */
  1215. if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
  1216. /*
  1217. * Some gen1 devices don't handle the gen 2 training
  1218. * correctly. Disable gen2 and try again with only
  1219. * gen1
  1220. */
  1221. union cvmx_pciercx_cfg031 pciercx_cfg031;
  1222. pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
  1223. pciercx_cfg031.s.mls = 1;
  1224. cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
  1225. if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
  1226. pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
  1227. return -1;
  1228. }
  1229. }
  1230. /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
  1231. sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
  1232. sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
  1233. sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
  1234. cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
  1235. /* Setup Mem access SubDIDs */
  1236. mem_access_subid.u64 = 0;
  1237. mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
  1238. mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
  1239. mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
  1240. mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
  1241. mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  1242. mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
  1243. /* PCIe Adddress Bits <63:34>. */
  1244. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  1245. mem_access_subid.cn68xx.ba = 0;
  1246. else
  1247. mem_access_subid.s.ba = 0;
  1248. /*
  1249. * Setup mem access 12-15 for port 0, 16-19 for port 1,
  1250. * supplying 36 bits of address space.
  1251. */
  1252. for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
  1253. cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
  1254. /* Set each SUBID to extend the addressable range */
  1255. __cvmx_increment_ba(&mem_access_subid);
  1256. }
  1257. /*
  1258. * Disable the peer to peer forwarding register. This must be
  1259. * setup by the OS after it enumerates the bus and assigns
  1260. * addresses to the PCIe busses.
  1261. */
  1262. for (i = 0; i < 4; i++) {
  1263. cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
  1264. cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
  1265. }
  1266. /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
  1267. cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
  1268. /*
  1269. * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
  1270. * precedence where they overlap. It also overlaps with the
  1271. * device addresses, so make sure the peer to peer forwarding
  1272. * is set right.
  1273. */
  1274. cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
  1275. /*
  1276. * Setup BAR2 attributes
  1277. * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
  1278. * - PTLP_RO,CTLP_RO should normally be set (except for debug).
  1279. * - WAIT_COM=0 will likely work for all applications.
  1280. * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
  1281. */
  1282. pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
  1283. pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
  1284. pemx_bar_ctl.s.bar2_enb = 1;
  1285. pemx_bar_ctl.s.bar2_esx = 1;
  1286. pemx_bar_ctl.s.bar2_cax = 0;
  1287. cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
  1288. sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
  1289. sli_ctl_portx.s.ptlp_ro = 1;
  1290. sli_ctl_portx.s.ctlp_ro = 1;
  1291. sli_ctl_portx.s.wait_com = 0;
  1292. sli_ctl_portx.s.waitl_com = 0;
  1293. cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
  1294. /* BAR1 follows BAR2 */
  1295. cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
  1296. bar1_index.u64 = 0;
  1297. bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
  1298. bar1_index.s.ca = 1; /* Not Cached */
  1299. bar1_index.s.end_swp = 1; /* Endian Swap mode */
  1300. bar1_index.s.addr_v = 1; /* Valid entry */
  1301. for (i = 0; i < 16; i++) {
  1302. cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
  1303. /* 256MB / 16 >> 22 == 4 */
  1304. bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
  1305. }
  1306. /*
  1307. * Allow config retries for 250ms. Count is based off the 5Ghz
  1308. * SERDES clock.
  1309. */
  1310. pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
  1311. pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
  1312. cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
  1313. /* Display the link status */
  1314. pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
  1315. pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
  1316. return 0;
  1317. }
  1318. /**
  1319. * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
  1320. *
  1321. * @pcie_port: PCIe port to initialize
  1322. *
  1323. * Returns Zero on success
  1324. */
  1325. static int cvmx_pcie_rc_initialize(int pcie_port)
  1326. {
  1327. int result;
  1328. if (octeon_has_feature(OCTEON_FEATURE_NPEI))
  1329. result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
  1330. else
  1331. result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
  1332. return result;
  1333. }
  1334. /* Above was cvmx-pcie.c, below original pcie.c */
  1335. /**
  1336. * Map a PCI device to the appropriate interrupt line
  1337. *
  1338. * @dev: The Linux PCI device structure for the device to map
  1339. * @slot: The slot number for this device on __BUS 0__. Linux
  1340. * enumerates through all the bridges and figures out the
  1341. * slot on Bus 0 where this device eventually hooks to.
  1342. * @pin: The PCI interrupt pin read from the device, then swizzled
  1343. * as it goes through each bridge.
  1344. * Returns Interrupt number for the device
  1345. */
  1346. int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  1347. {
  1348. /*
  1349. * The EBH5600 board with the PCI to PCIe bridge mistakenly
  1350. * wires the first slot for both device id 2 and interrupt
  1351. * A. According to the PCI spec, device id 2 should be C. The
  1352. * following kludge attempts to fix this.
  1353. */
  1354. if (strstr(octeon_board_type_string(), "EBH5600") &&
  1355. dev->bus && dev->bus->parent) {
  1356. /*
  1357. * Iterate all the way up the device chain and find
  1358. * the root bus.
  1359. */
  1360. while (dev->bus && dev->bus->parent)
  1361. dev = to_pci_dev(dev->bus->bridge);
  1362. /*
  1363. * If the root bus is number 0 and the PEX 8114 is the
  1364. * root, assume we are behind the miswired bus. We
  1365. * need to correct the swizzle level by two. Yuck.
  1366. */
  1367. if ((dev->bus->number == 1) &&
  1368. (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
  1369. /*
  1370. * The pin field is one based, not zero. We
  1371. * need to swizzle it by minus two.
  1372. */
  1373. pin = ((pin - 3) & 3) + 1;
  1374. }
  1375. }
  1376. /*
  1377. * The -1 is because pin starts with one, not zero. It might
  1378. * be that this equation needs to include the slot number, but
  1379. * I don't have hardware to check that against.
  1380. */
  1381. return pin - 1 + OCTEON_IRQ_PCI_INT0;
  1382. }
  1383. static void set_cfg_read_retry(u32 retry_cnt)
  1384. {
  1385. union cvmx_pemx_ctl_status pemx_ctl;
  1386. pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
  1387. pemx_ctl.s.cfg_rtry = retry_cnt;
  1388. cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
  1389. }
  1390. static u32 disable_cfg_read_retry(void)
  1391. {
  1392. u32 retry_cnt;
  1393. union cvmx_pemx_ctl_status pemx_ctl;
  1394. pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
  1395. retry_cnt = pemx_ctl.s.cfg_rtry;
  1396. pemx_ctl.s.cfg_rtry = 0;
  1397. cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
  1398. return retry_cnt;
  1399. }
  1400. static int is_cfg_retry(void)
  1401. {
  1402. union cvmx_pemx_int_sum pemx_int_sum;
  1403. pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
  1404. if (pemx_int_sum.s.crs_dr)
  1405. return 1;
  1406. return 0;
  1407. }
  1408. /*
  1409. * Read a value from configuration space
  1410. *
  1411. */
  1412. static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
  1413. unsigned int devfn, int reg, int size,
  1414. u32 *val)
  1415. {
  1416. union octeon_cvmemctl cvmmemctl;
  1417. union octeon_cvmemctl cvmmemctl_save;
  1418. int bus_number = bus->number;
  1419. int cfg_retry = 0;
  1420. int retry_cnt = 0;
  1421. int max_retry_cnt = 10;
  1422. u32 cfg_retry_cnt = 0;
  1423. cvmmemctl_save.u64 = 0;
  1424. BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
  1425. /*
  1426. * For the top level bus make sure our hardware bus number
  1427. * matches the software one
  1428. */
  1429. if (bus->parent == NULL) {
  1430. if (enable_pcie_bus_num_war[pcie_port])
  1431. bus_number = 0;
  1432. else {
  1433. union cvmx_pciercx_cfg006 pciercx_cfg006;
  1434. pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
  1435. CVMX_PCIERCX_CFG006(pcie_port));
  1436. if (pciercx_cfg006.s.pbnum != bus_number) {
  1437. pciercx_cfg006.s.pbnum = bus_number;
  1438. pciercx_cfg006.s.sbnum = bus_number;
  1439. pciercx_cfg006.s.subbnum = bus_number;
  1440. cvmx_pcie_cfgx_write(pcie_port,
  1441. CVMX_PCIERCX_CFG006(pcie_port),
  1442. pciercx_cfg006.u32);
  1443. }
  1444. }
  1445. }
  1446. /*
  1447. * PCIe only has a single device connected to Octeon. It is
  1448. * always device ID 0. Don't bother doing reads for other
  1449. * device IDs on the first segment.
  1450. */
  1451. if ((bus->parent == NULL) && (devfn >> 3 != 0))
  1452. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1453. /*
  1454. * The following is a workaround for the CN57XX, CN56XX,
  1455. * CN55XX, and CN54XX errata with PCIe config reads from non
  1456. * existent devices. These chips will hang the PCIe link if a
  1457. * config read is performed that causes a UR response.
  1458. */
  1459. if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
  1460. OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
  1461. /*
  1462. * For our EBH5600 board, port 0 has a bridge with two
  1463. * PCI-X slots. We need a new special checks to make
  1464. * sure we only probe valid stuff. The PCIe->PCI-X
  1465. * bridge only respondes to device ID 0, function
  1466. * 0-1
  1467. */
  1468. if ((bus->parent == NULL) && (devfn >= 2))
  1469. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1470. /*
  1471. * The PCI-X slots are device ID 2,3. Choose one of
  1472. * the below "if" blocks based on what is plugged into
  1473. * the board.
  1474. */
  1475. #if 1
  1476. /* Use this option if you aren't using either slot */
  1477. if (bus_number == 2)
  1478. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1479. #elif 0
  1480. /*
  1481. * Use this option if you are using the first slot but
  1482. * not the second.
  1483. */
  1484. if ((bus_number == 2) && (devfn >> 3 != 2))
  1485. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1486. #elif 0
  1487. /*
  1488. * Use this option if you are using the second slot
  1489. * but not the first.
  1490. */
  1491. if ((bus_number == 2) && (devfn >> 3 != 3))
  1492. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1493. #elif 0
  1494. /* Use this opion if you are using both slots */
  1495. if ((bus_number == 2) &&
  1496. !((devfn == (2 << 3)) || (devfn == (3 << 3))))
  1497. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1498. #endif
  1499. /* The following #if gives a more complicated example. This is
  1500. the required checks for running a Nitrox CN16XX-NHBX in the
  1501. slot of the EBH5600. This card has a PLX PCIe bridge with
  1502. four Nitrox PLX parts behind it */
  1503. #if 0
  1504. /* PLX bridge with 4 ports */
  1505. if ((bus_number == 4) &&
  1506. !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
  1507. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1508. /* Nitrox behind PLX 1 */
  1509. if ((bus_number == 5) && (devfn >> 3 != 0))
  1510. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1511. /* Nitrox behind PLX 2 */
  1512. if ((bus_number == 6) && (devfn >> 3 != 0))
  1513. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1514. /* Nitrox behind PLX 3 */
  1515. if ((bus_number == 7) && (devfn >> 3 != 0))
  1516. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1517. /* Nitrox behind PLX 4 */
  1518. if ((bus_number == 8) && (devfn >> 3 != 0))
  1519. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1520. #endif
  1521. /*
  1522. * Shorten the DID timeout so bus errors for PCIe
  1523. * config reads from non existent devices happen
  1524. * faster. This allows us to continue booting even if
  1525. * the above "if" checks are wrong. Once one of these
  1526. * errors happens, the PCIe port is dead.
  1527. */
  1528. cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
  1529. cvmmemctl.u64 = cvmmemctl_save.u64;
  1530. cvmmemctl.s.didtto = 2;
  1531. __write_64bit_c0_register($11, 7, cvmmemctl.u64);
  1532. }
  1533. if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
  1534. cfg_retry_cnt = disable_cfg_read_retry();
  1535. pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
  1536. " size=%d ", pcie_port, bus_number, devfn, reg, size);
  1537. do {
  1538. switch (size) {
  1539. case 4:
  1540. *val = cvmx_pcie_config_read32(pcie_port, bus_number,
  1541. devfn >> 3, devfn & 0x7, reg);
  1542. break;
  1543. case 2:
  1544. *val = cvmx_pcie_config_read16(pcie_port, bus_number,
  1545. devfn >> 3, devfn & 0x7, reg);
  1546. break;
  1547. case 1:
  1548. *val = cvmx_pcie_config_read8(pcie_port, bus_number,
  1549. devfn >> 3, devfn & 0x7, reg);
  1550. break;
  1551. default:
  1552. if (OCTEON_IS_MODEL(OCTEON_CN63XX))
  1553. set_cfg_read_retry(cfg_retry_cnt);
  1554. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1555. }
  1556. if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
  1557. (enable_pcie_14459_war)) {
  1558. cfg_retry = is_cfg_retry();
  1559. retry_cnt++;
  1560. if (retry_cnt > max_retry_cnt) {
  1561. pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
  1562. retry_cnt);
  1563. cfg_retry = 0;
  1564. }
  1565. }
  1566. } while (cfg_retry);
  1567. if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
  1568. set_cfg_read_retry(cfg_retry_cnt);
  1569. pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
  1570. if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
  1571. OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
  1572. write_c0_cvmmemctl(cvmmemctl_save.u64);
  1573. return PCIBIOS_SUCCESSFUL;
  1574. }
  1575. static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
  1576. int reg, int size, u32 *val)
  1577. {
  1578. return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
  1579. }
  1580. static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
  1581. int reg, int size, u32 *val)
  1582. {
  1583. return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
  1584. }
  1585. static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
  1586. int reg, int size, u32 *val)
  1587. {
  1588. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1589. }
  1590. /*
  1591. * Write a value to PCI configuration space
  1592. */
  1593. static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
  1594. unsigned int devfn, int reg,
  1595. int size, u32 val)
  1596. {
  1597. int bus_number = bus->number;
  1598. BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
  1599. if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
  1600. bus_number = 0;
  1601. pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
  1602. " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
  1603. reg, size, val);
  1604. switch (size) {
  1605. case 4:
  1606. cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
  1607. devfn & 0x7, reg, val);
  1608. break;
  1609. case 2:
  1610. cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
  1611. devfn & 0x7, reg, val);
  1612. break;
  1613. case 1:
  1614. cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
  1615. devfn & 0x7, reg, val);
  1616. break;
  1617. default:
  1618. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1619. }
  1620. return PCIBIOS_SUCCESSFUL;
  1621. }
  1622. static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
  1623. int reg, int size, u32 val)
  1624. {
  1625. return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
  1626. }
  1627. static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
  1628. int reg, int size, u32 val)
  1629. {
  1630. return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
  1631. }
  1632. static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
  1633. int reg, int size, u32 val)
  1634. {
  1635. return PCIBIOS_FUNC_NOT_SUPPORTED;
  1636. }
  1637. static struct pci_ops octeon_pcie0_ops = {
  1638. .read = octeon_pcie0_read_config,
  1639. .write = octeon_pcie0_write_config,
  1640. };
  1641. static struct resource octeon_pcie0_mem_resource = {
  1642. .name = "Octeon PCIe0 MEM",
  1643. .flags = IORESOURCE_MEM,
  1644. };
  1645. static struct resource octeon_pcie0_io_resource = {
  1646. .name = "Octeon PCIe0 IO",
  1647. .flags = IORESOURCE_IO,
  1648. };
  1649. static struct pci_controller octeon_pcie0_controller = {
  1650. .pci_ops = &octeon_pcie0_ops,
  1651. .mem_resource = &octeon_pcie0_mem_resource,
  1652. .io_resource = &octeon_pcie0_io_resource,
  1653. };
  1654. static struct pci_ops octeon_pcie1_ops = {
  1655. .read = octeon_pcie1_read_config,
  1656. .write = octeon_pcie1_write_config,
  1657. };
  1658. static struct resource octeon_pcie1_mem_resource = {
  1659. .name = "Octeon PCIe1 MEM",
  1660. .flags = IORESOURCE_MEM,
  1661. };
  1662. static struct resource octeon_pcie1_io_resource = {
  1663. .name = "Octeon PCIe1 IO",
  1664. .flags = IORESOURCE_IO,
  1665. };
  1666. static struct pci_controller octeon_pcie1_controller = {
  1667. .pci_ops = &octeon_pcie1_ops,
  1668. .mem_resource = &octeon_pcie1_mem_resource,
  1669. .io_resource = &octeon_pcie1_io_resource,
  1670. };
  1671. static struct pci_ops octeon_dummy_ops = {
  1672. .read = octeon_dummy_read_config,
  1673. .write = octeon_dummy_write_config,
  1674. };
  1675. static struct resource octeon_dummy_mem_resource = {
  1676. .name = "Virtual PCIe MEM",
  1677. .flags = IORESOURCE_MEM,
  1678. };
  1679. static struct resource octeon_dummy_io_resource = {
  1680. .name = "Virtual PCIe IO",
  1681. .flags = IORESOURCE_IO,
  1682. };
  1683. static struct pci_controller octeon_dummy_controller = {
  1684. .pci_ops = &octeon_dummy_ops,
  1685. .mem_resource = &octeon_dummy_mem_resource,
  1686. .io_resource = &octeon_dummy_io_resource,
  1687. };
  1688. static int device_needs_bus_num_war(uint32_t deviceid)
  1689. {
  1690. #define IDT_VENDOR_ID 0x111d
  1691. if ((deviceid & 0xffff) == IDT_VENDOR_ID)
  1692. return 1;
  1693. return 0;
  1694. }
  1695. /**
  1696. * Initialize the Octeon PCIe controllers
  1697. *
  1698. * Returns
  1699. */
  1700. static int __init octeon_pcie_setup(void)
  1701. {
  1702. int result;
  1703. int host_mode;
  1704. int srio_war15205 = 0, port;
  1705. union cvmx_sli_ctl_portx sli_ctl_portx;
  1706. union cvmx_sriox_status_reg sriox_status_reg;
  1707. /* These chips don't have PCIe */
  1708. if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
  1709. return 0;
  1710. /* No PCIe simulation */
  1711. if (octeon_is_simulation())
  1712. return 0;
  1713. /* Disable PCI if instructed on the command line */
  1714. if (pcie_disable)
  1715. return 0;
  1716. /* Point pcibios_map_irq() to the PCIe version of it */
  1717. octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
  1718. /*
  1719. * PCIe I/O range. It is based on port 0 but includes up until
  1720. * port 1's end.
  1721. */
  1722. set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
  1723. ioport_resource.start = 0;
  1724. ioport_resource.end =
  1725. cvmx_pcie_get_io_base_address(1) -
  1726. cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
  1727. /*
  1728. * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
  1729. * don't work if the primary bus number is zero. Here we add a fake
  1730. * PCIe controller that the kernel will give bus 0. This allows
  1731. * us to not change the normal kernel bus enumeration
  1732. */
  1733. octeon_dummy_controller.io_map_base = -1;
  1734. octeon_dummy_controller.mem_resource->start = (1ull<<48);
  1735. octeon_dummy_controller.mem_resource->end = (1ull<<48);
  1736. register_pci_controller(&octeon_dummy_controller);
  1737. if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
  1738. union cvmx_npei_ctl_status npei_ctl_status;
  1739. npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
  1740. host_mode = npei_ctl_status.s.host_mode;
  1741. octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
  1742. } else {
  1743. union cvmx_mio_rst_ctlx mio_rst_ctl;
  1744. mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
  1745. host_mode = mio_rst_ctl.s.host_mode;
  1746. octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
  1747. }
  1748. if (host_mode) {
  1749. pr_notice("PCIe: Initializing port 0\n");
  1750. /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
  1751. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
  1752. OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
  1753. sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
  1754. if (sriox_status_reg.s.srio) {
  1755. srio_war15205 += 1; /* Port is SRIO */
  1756. port = 0;
  1757. }
  1758. }
  1759. result = cvmx_pcie_rc_initialize(0);
  1760. if (result == 0) {
  1761. uint32_t device0;
  1762. /* Memory offsets are physical addresses */
  1763. octeon_pcie0_controller.mem_offset =
  1764. cvmx_pcie_get_mem_base_address(0);
  1765. /* IO offsets are Mips virtual addresses */
  1766. octeon_pcie0_controller.io_map_base =
  1767. CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
  1768. (0));
  1769. octeon_pcie0_controller.io_offset = 0;
  1770. /*
  1771. * To keep things similar to PCI, we start
  1772. * device addresses at the same place as PCI
  1773. * uisng big bar support. This normally
  1774. * translates to 4GB-256MB, which is the same
  1775. * as most x86 PCs.
  1776. */
  1777. octeon_pcie0_controller.mem_resource->start =
  1778. cvmx_pcie_get_mem_base_address(0) +
  1779. (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
  1780. octeon_pcie0_controller.mem_resource->end =
  1781. cvmx_pcie_get_mem_base_address(0) +
  1782. cvmx_pcie_get_mem_size(0) - 1;
  1783. /*
  1784. * Ports must be above 16KB for the ISA bus
  1785. * filtering in the PCI-X to PCI bridge.
  1786. */
  1787. octeon_pcie0_controller.io_resource->start = 4 << 10;
  1788. octeon_pcie0_controller.io_resource->end =
  1789. cvmx_pcie_get_io_size(0) - 1;
  1790. msleep(100); /* Some devices need extra time */
  1791. register_pci_controller(&octeon_pcie0_controller);
  1792. device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
  1793. enable_pcie_bus_num_war[0] =
  1794. device_needs_bus_num_war(device0);
  1795. }
  1796. } else {
  1797. pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
  1798. /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
  1799. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
  1800. OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
  1801. srio_war15205 += 1;
  1802. port = 0;
  1803. }
  1804. }
  1805. if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
  1806. host_mode = 1;
  1807. /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
  1808. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  1809. union cvmx_npei_dbg_data dbg_data;
  1810. dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
  1811. if (dbg_data.cn52xx.qlm0_link_width)
  1812. host_mode = 0;
  1813. }
  1814. } else {
  1815. union cvmx_mio_rst_ctlx mio_rst_ctl;
  1816. mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
  1817. host_mode = mio_rst_ctl.s.host_mode;
  1818. }
  1819. if (host_mode) {
  1820. pr_notice("PCIe: Initializing port 1\n");
  1821. /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
  1822. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
  1823. OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
  1824. sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
  1825. if (sriox_status_reg.s.srio) {
  1826. srio_war15205 += 1; /* Port is SRIO */
  1827. port = 1;
  1828. }
  1829. }
  1830. result = cvmx_pcie_rc_initialize(1);
  1831. if (result == 0) {
  1832. uint32_t device0;
  1833. /* Memory offsets are physical addresses */
  1834. octeon_pcie1_controller.mem_offset =
  1835. cvmx_pcie_get_mem_base_address(1);
  1836. /*
  1837. * To calculate the address for accessing the 2nd PCIe device,
  1838. * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
  1839. * (ioport_map()) value is added to
  1840. * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
  1841. * only once based on first PCIe. Also changing 'io_map_base'
  1842. * based on first slot's value so that both the routines will
  1843. * work properly.
  1844. */
  1845. octeon_pcie1_controller.io_map_base =
  1846. CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
  1847. /* IO offsets are Mips virtual addresses */
  1848. octeon_pcie1_controller.io_offset =
  1849. cvmx_pcie_get_io_base_address(1) -
  1850. cvmx_pcie_get_io_base_address(0);
  1851. /*
  1852. * To keep things similar to PCI, we start device
  1853. * addresses at the same place as PCI uisng big bar
  1854. * support. This normally translates to 4GB-256MB,
  1855. * which is the same as most x86 PCs.
  1856. */
  1857. octeon_pcie1_controller.mem_resource->start =
  1858. cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
  1859. (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
  1860. octeon_pcie1_controller.mem_resource->end =
  1861. cvmx_pcie_get_mem_base_address(1) +
  1862. cvmx_pcie_get_mem_size(1) - 1;
  1863. /*
  1864. * Ports must be above 16KB for the ISA bus filtering
  1865. * in the PCI-X to PCI bridge.
  1866. */
  1867. octeon_pcie1_controller.io_resource->start =
  1868. cvmx_pcie_get_io_base_address(1) -
  1869. cvmx_pcie_get_io_base_address(0);
  1870. octeon_pcie1_controller.io_resource->end =
  1871. octeon_pcie1_controller.io_resource->start +
  1872. cvmx_pcie_get_io_size(1) - 1;
  1873. msleep(100); /* Some devices need extra time */
  1874. register_pci_controller(&octeon_pcie1_controller);
  1875. device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
  1876. enable_pcie_bus_num_war[1] =
  1877. device_needs_bus_num_war(device0);
  1878. }
  1879. } else {
  1880. pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
  1881. /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
  1882. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
  1883. OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
  1884. srio_war15205 += 1;
  1885. port = 1;
  1886. }
  1887. }
  1888. /*
  1889. * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
  1890. * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
  1891. * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
  1892. * from the previous set values
  1893. */
  1894. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
  1895. OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
  1896. if (srio_war15205 == 1) {
  1897. sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
  1898. sli_ctl_portx.s.inta_map = 1;
  1899. sli_ctl_portx.s.intb_map = 1;
  1900. sli_ctl_portx.s.intc_map = 1;
  1901. sli_ctl_portx.s.intd_map = 1;
  1902. cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
  1903. sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
  1904. sli_ctl_portx.s.inta_map = 0;
  1905. sli_ctl_portx.s.intb_map = 0;
  1906. sli_ctl_portx.s.intc_map = 0;
  1907. sli_ctl_portx.s.intd_map = 0;
  1908. cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
  1909. }
  1910. }
  1911. octeon_pci_dma_init();
  1912. return 0;
  1913. }
  1914. arch_initcall(octeon_pcie_setup);