pci-rt3883.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink RT3662/RT3883 SoC PCI support
  4. *
  5. * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * Parts of this file are based on Ralink's 2.6.21 BSP
  8. */
  9. #include <linux/types.h>
  10. #include <linux/pci.h>
  11. #include <linux/io.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/of.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_pci.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/mach-ralink/rt3883.h>
  20. #include <asm/mach-ralink/ralink_regs.h>
  21. #define RT3883_MEMORY_BASE 0x00000000
  22. #define RT3883_MEMORY_SIZE 0x02000000
  23. #define RT3883_PCI_REG_PCICFG 0x00
  24. #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  25. #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  26. #define RT3883_PCICFG_PCIRST BIT(1)
  27. #define RT3883_PCI_REG_PCIRAW 0x04
  28. #define RT3883_PCI_REG_PCIINT 0x08
  29. #define RT3883_PCI_REG_PCIENA 0x0c
  30. #define RT3883_PCI_REG_CFGADDR 0x20
  31. #define RT3883_PCI_REG_CFGDATA 0x24
  32. #define RT3883_PCI_REG_MEMBASE 0x28
  33. #define RT3883_PCI_REG_IOBASE 0x2c
  34. #define RT3883_PCI_REG_ARBCTL 0x80
  35. #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
  36. #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
  37. #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
  38. #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
  39. #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
  40. #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
  41. #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
  42. #define RT3883_PCI_MODE_NONE 0
  43. #define RT3883_PCI_MODE_PCI BIT(0)
  44. #define RT3883_PCI_MODE_PCIE BIT(1)
  45. #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  46. #define RT3883_PCI_IRQ_COUNT 32
  47. #define RT3883_P2P_BR_DEVNUM 1
  48. struct rt3883_pci_controller {
  49. void __iomem *base;
  50. struct device_node *intc_of_node;
  51. struct irq_domain *irq_domain;
  52. struct pci_controller pci_controller;
  53. struct resource io_res;
  54. struct resource mem_res;
  55. bool pcie_ready;
  56. };
  57. static inline struct rt3883_pci_controller *
  58. pci_bus_to_rt3883_controller(struct pci_bus *bus)
  59. {
  60. struct pci_controller *hose;
  61. hose = (struct pci_controller *) bus->sysdata;
  62. return container_of(hose, struct rt3883_pci_controller, pci_controller);
  63. }
  64. static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
  65. unsigned reg)
  66. {
  67. return ioread32(rpc->base + reg);
  68. }
  69. static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
  70. u32 val, unsigned reg)
  71. {
  72. iowrite32(val, rpc->base + reg);
  73. }
  74. static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  75. unsigned int func, unsigned int where)
  76. {
  77. return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  78. 0x80000000;
  79. }
  80. static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
  81. unsigned bus, unsigned slot,
  82. unsigned func, unsigned reg)
  83. {
  84. unsigned long flags;
  85. u32 address;
  86. u32 ret;
  87. address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
  88. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  89. ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  90. return ret;
  91. }
  92. static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
  93. unsigned bus, unsigned slot,
  94. unsigned func, unsigned reg, u32 val)
  95. {
  96. unsigned long flags;
  97. u32 address;
  98. address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
  99. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  100. rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
  101. }
  102. static void rt3883_pci_irq_handler(struct irq_desc *desc)
  103. {
  104. struct rt3883_pci_controller *rpc;
  105. u32 pending;
  106. rpc = irq_desc_get_handler_data(desc);
  107. pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
  108. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  109. if (!pending) {
  110. spurious_interrupt();
  111. return;
  112. }
  113. while (pending) {
  114. unsigned irq, bit = __ffs(pending);
  115. irq = irq_find_mapping(rpc->irq_domain, bit);
  116. generic_handle_irq(irq);
  117. pending &= ~BIT(bit);
  118. }
  119. }
  120. static void rt3883_pci_irq_unmask(struct irq_data *d)
  121. {
  122. struct rt3883_pci_controller *rpc;
  123. u32 t;
  124. rpc = irq_data_get_irq_chip_data(d);
  125. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  126. rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
  127. /* flush write */
  128. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  129. }
  130. static void rt3883_pci_irq_mask(struct irq_data *d)
  131. {
  132. struct rt3883_pci_controller *rpc;
  133. u32 t;
  134. rpc = irq_data_get_irq_chip_data(d);
  135. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  136. rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
  137. /* flush write */
  138. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  139. }
  140. static struct irq_chip rt3883_pci_irq_chip = {
  141. .name = "RT3883 PCI",
  142. .irq_mask = rt3883_pci_irq_mask,
  143. .irq_unmask = rt3883_pci_irq_unmask,
  144. .irq_mask_ack = rt3883_pci_irq_mask,
  145. };
  146. static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
  147. irq_hw_number_t hw)
  148. {
  149. irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
  150. irq_set_chip_data(irq, d->host_data);
  151. return 0;
  152. }
  153. static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
  154. .map = rt3883_pci_irq_map,
  155. .xlate = irq_domain_xlate_onecell,
  156. };
  157. static int rt3883_pci_irq_init(struct device *dev,
  158. struct rt3883_pci_controller *rpc)
  159. {
  160. int irq;
  161. irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
  162. if (irq == 0) {
  163. dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
  164. return -EINVAL;
  165. }
  166. /* disable all interrupts */
  167. rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
  168. rpc->irq_domain =
  169. irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
  170. &rt3883_pci_irq_domain_ops,
  171. rpc);
  172. if (!rpc->irq_domain) {
  173. dev_err(dev, "unable to add IRQ domain\n");
  174. return -ENODEV;
  175. }
  176. irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
  177. return 0;
  178. }
  179. static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  180. int where, int size, u32 *val)
  181. {
  182. struct rt3883_pci_controller *rpc;
  183. unsigned long flags;
  184. u32 address;
  185. u32 data;
  186. rpc = pci_bus_to_rt3883_controller(bus);
  187. if (!rpc->pcie_ready && bus->number == 1)
  188. return PCIBIOS_DEVICE_NOT_FOUND;
  189. address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  190. PCI_FUNC(devfn), where);
  191. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  192. data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  193. switch (size) {
  194. case 1:
  195. *val = (data >> ((where & 3) << 3)) & 0xff;
  196. break;
  197. case 2:
  198. *val = (data >> ((where & 3) << 3)) & 0xffff;
  199. break;
  200. case 4:
  201. *val = data;
  202. break;
  203. }
  204. return PCIBIOS_SUCCESSFUL;
  205. }
  206. static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  207. int where, int size, u32 val)
  208. {
  209. struct rt3883_pci_controller *rpc;
  210. unsigned long flags;
  211. u32 address;
  212. u32 data;
  213. rpc = pci_bus_to_rt3883_controller(bus);
  214. if (!rpc->pcie_ready && bus->number == 1)
  215. return PCIBIOS_DEVICE_NOT_FOUND;
  216. address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  217. PCI_FUNC(devfn), where);
  218. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  219. data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  220. switch (size) {
  221. case 1:
  222. data = (data & ~(0xff << ((where & 3) << 3))) |
  223. (val << ((where & 3) << 3));
  224. break;
  225. case 2:
  226. data = (data & ~(0xffff << ((where & 3) << 3))) |
  227. (val << ((where & 3) << 3));
  228. break;
  229. case 4:
  230. data = val;
  231. break;
  232. }
  233. rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
  234. return PCIBIOS_SUCCESSFUL;
  235. }
  236. static struct pci_ops rt3883_pci_ops = {
  237. .read = rt3883_pci_config_read,
  238. .write = rt3883_pci_config_write,
  239. };
  240. static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
  241. {
  242. u32 syscfg1;
  243. u32 rstctrl;
  244. u32 clkcfg1;
  245. u32 t;
  246. rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
  247. syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
  248. clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
  249. if (mode & RT3883_PCI_MODE_PCIE) {
  250. rstctrl |= RT3883_RSTCTRL_PCIE;
  251. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  252. /* setup PCI PAD drive mode */
  253. syscfg1 &= ~(0x30);
  254. syscfg1 |= (2 << 4);
  255. rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
  256. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  257. t &= ~BIT(31);
  258. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  259. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
  260. t &= 0x80ffffff;
  261. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
  262. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
  263. t |= 0xa << 24;
  264. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
  265. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  266. t |= BIT(31);
  267. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  268. msleep(50);
  269. rstctrl &= ~RT3883_RSTCTRL_PCIE;
  270. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  271. }
  272. syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
  273. clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
  274. if (mode & RT3883_PCI_MODE_PCI) {
  275. clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
  276. rstctrl &= ~RT3883_RSTCTRL_PCI;
  277. }
  278. if (mode & RT3883_PCI_MODE_PCIE) {
  279. clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
  280. rstctrl &= ~RT3883_RSTCTRL_PCIE;
  281. }
  282. rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
  283. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  284. rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
  285. msleep(500);
  286. /*
  287. * setup the device number of the P2P bridge
  288. * and de-assert the reset line
  289. */
  290. t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
  291. rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
  292. /* flush write */
  293. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
  294. msleep(500);
  295. if (mode & RT3883_PCI_MODE_PCIE) {
  296. msleep(500);
  297. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
  298. rpc->pcie_ready = t & BIT(0);
  299. if (!rpc->pcie_ready) {
  300. /* reset the PCIe block */
  301. t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
  302. t |= RT3883_RSTCTRL_PCIE;
  303. rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
  304. t &= ~RT3883_RSTCTRL_PCIE;
  305. rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
  306. /* turn off PCIe clock */
  307. t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
  308. t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
  309. rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
  310. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  311. t &= ~0xf000c080;
  312. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  313. }
  314. }
  315. /* enable PCI arbiter */
  316. rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
  317. }
  318. static int rt3883_pci_probe(struct platform_device *pdev)
  319. {
  320. struct rt3883_pci_controller *rpc;
  321. struct device *dev = &pdev->dev;
  322. struct device_node *np = dev->of_node;
  323. struct resource *res;
  324. struct device_node *child;
  325. u32 val;
  326. int err;
  327. int mode;
  328. rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
  329. if (!rpc)
  330. return -ENOMEM;
  331. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  332. rpc->base = devm_ioremap_resource(dev, res);
  333. if (IS_ERR(rpc->base))
  334. return PTR_ERR(rpc->base);
  335. /* find the interrupt controller child node */
  336. for_each_child_of_node(np, child) {
  337. if (of_get_property(child, "interrupt-controller", NULL)) {
  338. rpc->intc_of_node = child;
  339. break;
  340. }
  341. }
  342. if (!rpc->intc_of_node) {
  343. dev_err(dev, "%pOF has no %s child node",
  344. rpc->intc_of_node,
  345. "interrupt controller");
  346. return -EINVAL;
  347. }
  348. /* find the PCI host bridge child node */
  349. for_each_child_of_node(np, child) {
  350. if (of_node_is_type(child, "pci")) {
  351. rpc->pci_controller.of_node = child;
  352. break;
  353. }
  354. }
  355. if (!rpc->pci_controller.of_node) {
  356. dev_err(dev, "%pOF has no %s child node",
  357. rpc->intc_of_node,
  358. "PCI host bridge");
  359. err = -EINVAL;
  360. goto err_put_intc_node;
  361. }
  362. mode = RT3883_PCI_MODE_NONE;
  363. for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
  364. int devfn;
  365. if (!of_node_is_type(child, "pci"))
  366. continue;
  367. devfn = of_pci_get_devfn(child);
  368. if (devfn < 0)
  369. continue;
  370. switch (PCI_SLOT(devfn)) {
  371. case 1:
  372. mode |= RT3883_PCI_MODE_PCIE;
  373. break;
  374. case 17:
  375. case 18:
  376. mode |= RT3883_PCI_MODE_PCI;
  377. break;
  378. }
  379. }
  380. if (mode == RT3883_PCI_MODE_NONE) {
  381. dev_err(dev, "unable to determine PCI mode\n");
  382. err = -EINVAL;
  383. goto err_put_hb_node;
  384. }
  385. dev_info(dev, "mode:%s%s\n",
  386. (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
  387. (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
  388. rt3883_pci_preinit(rpc, mode);
  389. rpc->pci_controller.pci_ops = &rt3883_pci_ops;
  390. rpc->pci_controller.io_resource = &rpc->io_res;
  391. rpc->pci_controller.mem_resource = &rpc->mem_res;
  392. /* Load PCI I/O and memory resources from DT */
  393. pci_load_of_ranges(&rpc->pci_controller,
  394. rpc->pci_controller.of_node);
  395. rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
  396. rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
  397. ioport_resource.start = rpc->io_res.start;
  398. ioport_resource.end = rpc->io_res.end;
  399. /* PCI */
  400. rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
  401. rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
  402. rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
  403. rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
  404. rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
  405. /* PCIe */
  406. rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
  407. rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
  408. rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
  409. rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
  410. rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
  411. err = rt3883_pci_irq_init(dev, rpc);
  412. if (err)
  413. goto err_put_hb_node;
  414. /* PCIe */
  415. val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
  416. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  417. rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
  418. /* PCI */
  419. val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
  420. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  421. rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
  422. if (mode == RT3883_PCI_MODE_PCIE) {
  423. rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
  424. rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
  425. rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  426. PCI_BASE_ADDRESS_0,
  427. RT3883_MEMORY_BASE);
  428. /* flush write */
  429. rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  430. PCI_BASE_ADDRESS_0);
  431. } else {
  432. rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  433. PCI_IO_BASE, 0x00000101);
  434. }
  435. register_pci_controller(&rpc->pci_controller);
  436. return 0;
  437. err_put_hb_node:
  438. of_node_put(rpc->pci_controller.of_node);
  439. err_put_intc_node:
  440. of_node_put(rpc->intc_of_node);
  441. return err;
  442. }
  443. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  444. {
  445. return of_irq_parse_and_map_pci(dev, slot, pin);
  446. }
  447. int pcibios_plat_dev_init(struct pci_dev *dev)
  448. {
  449. return 0;
  450. }
  451. static const struct of_device_id rt3883_pci_ids[] = {
  452. { .compatible = "ralink,rt3883-pci" },
  453. {},
  454. };
  455. static struct platform_driver rt3883_pci_driver = {
  456. .probe = rt3883_pci_probe,
  457. .driver = {
  458. .name = "rt3883-pci",
  459. .of_match_table = of_match_ptr(rt3883_pci_ids),
  460. },
  461. };
  462. static int __init rt3883_pci_init(void)
  463. {
  464. return platform_driver_register(&rt3883_pci_driver);
  465. }
  466. postcore_initcall(rt3883_pci_init);