pci-bcm63xx.c 9.7 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <linux/types.h>
  9. #include <linux/pci.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/clk.h>
  14. #include <asm/bootinfo.h>
  15. #include <bcm63xx_reset.h>
  16. #include "pci-bcm63xx.h"
  17. /*
  18. * Allow PCI to be disabled at runtime depending on board nvram
  19. * configuration
  20. */
  21. int bcm63xx_pci_enabled;
  22. static struct resource bcm_pci_mem_resource = {
  23. .name = "bcm63xx PCI memory space",
  24. .start = BCM_PCI_MEM_BASE_PA,
  25. .end = BCM_PCI_MEM_END_PA,
  26. .flags = IORESOURCE_MEM
  27. };
  28. static struct resource bcm_pci_io_resource = {
  29. .name = "bcm63xx PCI IO space",
  30. .start = BCM_PCI_IO_BASE_PA,
  31. #ifdef CONFIG_CARDBUS
  32. .end = BCM_PCI_IO_HALF_PA,
  33. #else
  34. .end = BCM_PCI_IO_END_PA,
  35. #endif
  36. .flags = IORESOURCE_IO
  37. };
  38. struct pci_controller bcm63xx_controller = {
  39. .pci_ops = &bcm63xx_pci_ops,
  40. .io_resource = &bcm_pci_io_resource,
  41. .mem_resource = &bcm_pci_mem_resource,
  42. };
  43. /*
  44. * We handle cardbus via a fake Cardbus bridge, memory and io spaces
  45. * have to be clearly separated from PCI one since we have different
  46. * memory decoder.
  47. */
  48. #ifdef CONFIG_CARDBUS
  49. static struct resource bcm_cb_mem_resource = {
  50. .name = "bcm63xx Cardbus memory space",
  51. .start = BCM_CB_MEM_BASE_PA,
  52. .end = BCM_CB_MEM_END_PA,
  53. .flags = IORESOURCE_MEM
  54. };
  55. static struct resource bcm_cb_io_resource = {
  56. .name = "bcm63xx Cardbus IO space",
  57. .start = BCM_PCI_IO_HALF_PA + 1,
  58. .end = BCM_PCI_IO_END_PA,
  59. .flags = IORESOURCE_IO
  60. };
  61. struct pci_controller bcm63xx_cb_controller = {
  62. .pci_ops = &bcm63xx_cb_ops,
  63. .io_resource = &bcm_cb_io_resource,
  64. .mem_resource = &bcm_cb_mem_resource,
  65. };
  66. #endif
  67. static struct resource bcm_pcie_mem_resource = {
  68. .name = "bcm63xx PCIe memory space",
  69. .start = BCM_PCIE_MEM_BASE_PA,
  70. .end = BCM_PCIE_MEM_END_PA,
  71. .flags = IORESOURCE_MEM,
  72. };
  73. static struct resource bcm_pcie_io_resource = {
  74. .name = "bcm63xx PCIe IO space",
  75. .start = 0,
  76. .end = 0,
  77. .flags = 0,
  78. };
  79. struct pci_controller bcm63xx_pcie_controller = {
  80. .pci_ops = &bcm63xx_pcie_ops,
  81. .io_resource = &bcm_pcie_io_resource,
  82. .mem_resource = &bcm_pcie_mem_resource,
  83. };
  84. static u32 bcm63xx_int_cfg_readl(u32 reg)
  85. {
  86. u32 tmp;
  87. tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  88. tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
  89. bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  90. iob();
  91. return bcm_mpi_readl(MPI_PCICFGDATA_REG);
  92. }
  93. static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
  94. {
  95. u32 tmp;
  96. tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
  97. tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
  98. bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
  99. bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
  100. }
  101. void __iomem *pci_iospace_start;
  102. static void __init bcm63xx_reset_pcie(void)
  103. {
  104. u32 val;
  105. u32 reg;
  106. /* enable SERDES */
  107. if (BCMCPU_IS_6328())
  108. reg = MISC_SERDES_CTRL_6328_REG;
  109. else
  110. reg = MISC_SERDES_CTRL_6362_REG;
  111. val = bcm_misc_readl(reg);
  112. val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
  113. bcm_misc_writel(val, reg);
  114. /* reset the PCIe core */
  115. bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
  116. bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
  117. mdelay(10);
  118. bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
  119. mdelay(10);
  120. bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
  121. mdelay(200);
  122. }
  123. static struct clk *pcie_clk;
  124. static int __init bcm63xx_register_pcie(void)
  125. {
  126. u32 val;
  127. /* enable clock */
  128. pcie_clk = clk_get(NULL, "pcie");
  129. if (IS_ERR_OR_NULL(pcie_clk))
  130. return -ENODEV;
  131. clk_prepare_enable(pcie_clk);
  132. bcm63xx_reset_pcie();
  133. /* configure the PCIe bridge */
  134. val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
  135. val |= OPT1_RD_BE_OPT_EN;
  136. val |= OPT1_RD_REPLY_BE_FIX_EN;
  137. val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
  138. val |= OPT1_L1_INT_STATUS_MASK_POL;
  139. bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
  140. /* setup the interrupts */
  141. val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
  142. val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
  143. bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
  144. val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
  145. /* enable credit checking and error checking */
  146. val |= OPT2_TX_CREDIT_CHK_EN;
  147. val |= OPT2_UBUS_UR_DECODE_DIS;
  148. /* set device bus/func for the pcie device */
  149. val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
  150. val |= OPT2_CFG_TYPE1_BD_SEL;
  151. bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
  152. /* setup class code as bridge */
  153. val = bcm_pcie_readl(PCIE_IDVAL3_REG);
  154. val &= ~IDVAL3_CLASS_CODE_MASK;
  155. val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
  156. bcm_pcie_writel(val, PCIE_IDVAL3_REG);
  157. /* disable bar1 size */
  158. val = bcm_pcie_readl(PCIE_CONFIG2_REG);
  159. val &= ~CONFIG2_BAR1_SIZE_MASK;
  160. bcm_pcie_writel(val, PCIE_CONFIG2_REG);
  161. /* set bar0 to little endian */
  162. val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
  163. val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
  164. val |= BASEMASK_REMAP_EN;
  165. bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
  166. val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
  167. bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
  168. register_pci_controller(&bcm63xx_pcie_controller);
  169. return 0;
  170. }
  171. static int __init bcm63xx_register_pci(void)
  172. {
  173. unsigned int mem_size;
  174. u32 val;
  175. /*
  176. * configuration access are done through IO space, remap 4
  177. * first bytes to access it from CPU.
  178. *
  179. * this means that no io access from CPU should happen while
  180. * we do a configuration cycle, but there's no way we can add
  181. * a spinlock for each io access, so this is currently kind of
  182. * broken on SMP.
  183. */
  184. pci_iospace_start = ioremap(BCM_PCI_IO_BASE_PA, 4);
  185. if (!pci_iospace_start)
  186. return -ENOMEM;
  187. /* setup local bus to PCI access (PCI memory) */
  188. val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
  189. bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
  190. bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
  191. bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
  192. /* set Cardbus IDSEL (type 0 cfg access on primary bus for
  193. * this IDSEL will be done on Cardbus instead) */
  194. val = bcm_pcmcia_readl(PCMCIA_C1_REG);
  195. val &= ~PCMCIA_C1_CBIDSEL_MASK;
  196. val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
  197. bcm_pcmcia_writel(val, PCMCIA_C1_REG);
  198. #ifdef CONFIG_CARDBUS
  199. /* setup local bus to PCI access (Cardbus memory) */
  200. val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
  201. bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
  202. bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
  203. val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
  204. bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
  205. #else
  206. /* disable second access windows */
  207. bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
  208. #endif
  209. /* setup local bus to PCI access (IO memory), we have only 1
  210. * IO window for both PCI and cardbus, but it cannot handle
  211. * both at the same time, assume standard PCI for now, if
  212. * cardbus card has IO zone, PCI fixup will change window to
  213. * cardbus */
  214. val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
  215. bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
  216. bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
  217. bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
  218. /* enable PCI related GPIO pins */
  219. bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
  220. /* setup PCI to local bus access, used by PCI device to target
  221. * local RAM while bus mastering */
  222. bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
  223. if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
  224. val = MPI_SP0_REMAP_ENABLE_MASK;
  225. else
  226. val = 0;
  227. bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
  228. bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
  229. bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
  230. mem_size = bcm63xx_get_memory_size();
  231. /* 6348 before rev b0 exposes only 16 MB of RAM memory through
  232. * PCI, throw a warning if we have more memory */
  233. if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
  234. if (mem_size > (16 * 1024 * 1024))
  235. printk(KERN_WARNING "bcm63xx: this CPU "
  236. "revision cannot handle more than 16MB "
  237. "of RAM for PCI bus mastering\n");
  238. } else {
  239. /* setup sp0 range to local RAM size */
  240. bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
  241. bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
  242. }
  243. /* change host bridge retry counter to infinite number of
  244. * retry, needed for some broadcom wifi cards with Silicon
  245. * Backplane bus where access to srom seems very slow */
  246. val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
  247. val &= ~REG_TIMER_RETRY_MASK;
  248. bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
  249. /* enable memory decoder and bus mastering */
  250. val = bcm63xx_int_cfg_readl(PCI_COMMAND);
  251. val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  252. bcm63xx_int_cfg_writel(val, PCI_COMMAND);
  253. /* enable read prefetching & disable byte swapping for bus
  254. * mastering transfers */
  255. val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
  256. val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
  257. val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
  258. val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
  259. val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
  260. bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
  261. /* enable pci interrupt */
  262. val = bcm_mpi_readl(MPI_LOCINT_REG);
  263. val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
  264. bcm_mpi_writel(val, MPI_LOCINT_REG);
  265. register_pci_controller(&bcm63xx_controller);
  266. #ifdef CONFIG_CARDBUS
  267. register_pci_controller(&bcm63xx_cb_controller);
  268. #endif
  269. /* mark memory space used for IO mapping as reserved */
  270. request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
  271. "bcm63xx PCI IO space");
  272. return 0;
  273. }
  274. static int __init bcm63xx_pci_init(void)
  275. {
  276. if (!bcm63xx_pci_enabled)
  277. return -ENODEV;
  278. switch (bcm63xx_get_cpu_id()) {
  279. case BCM6328_CPU_ID:
  280. case BCM6362_CPU_ID:
  281. return bcm63xx_register_pcie();
  282. case BCM3368_CPU_ID:
  283. case BCM6348_CPU_ID:
  284. case BCM6358_CPU_ID:
  285. case BCM6368_CPU_ID:
  286. return bcm63xx_register_pci();
  287. default:
  288. return -ENODEV;
  289. }
  290. }
  291. arch_initcall(bcm63xx_pci_init);