pci-ar724x.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR724X PCI host controller driver
  4. *
  5. * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
  6. * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  7. */
  8. #include <linux/irq.h>
  9. #include <linux/pci.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/platform_device.h>
  13. #include <asm/mach-ath79/ath79.h>
  14. #include <asm/mach-ath79/ar71xx_regs.h>
  15. #define AR724X_PCI_REG_APP 0x00
  16. #define AR724X_PCI_REG_RESET 0x18
  17. #define AR724X_PCI_REG_INT_STATUS 0x4c
  18. #define AR724X_PCI_REG_INT_MASK 0x50
  19. #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
  20. #define AR724X_PCI_RESET_LINK_UP BIT(0)
  21. #define AR724X_PCI_INT_DEV0 BIT(14)
  22. #define AR724X_PCI_IRQ_COUNT 1
  23. #define AR7240_BAR0_WAR_VALUE 0xffff
  24. #define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
  25. PCI_COMMAND_MASTER | \
  26. PCI_COMMAND_INVALIDATE | \
  27. PCI_COMMAND_PARITY | \
  28. PCI_COMMAND_SERR | \
  29. PCI_COMMAND_FAST_BACK)
  30. struct ar724x_pci_controller {
  31. void __iomem *devcfg_base;
  32. void __iomem *ctrl_base;
  33. void __iomem *crp_base;
  34. int irq;
  35. int irq_base;
  36. bool link_up;
  37. bool bar0_is_cached;
  38. u32 bar0_value;
  39. struct pci_controller pci_controller;
  40. struct resource io_res;
  41. struct resource mem_res;
  42. };
  43. static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
  44. {
  45. u32 reset;
  46. reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
  47. return reset & AR724X_PCI_RESET_LINK_UP;
  48. }
  49. static inline struct ar724x_pci_controller *
  50. pci_bus_to_ar724x_controller(struct pci_bus *bus)
  51. {
  52. struct pci_controller *hose;
  53. hose = (struct pci_controller *) bus->sysdata;
  54. return container_of(hose, struct ar724x_pci_controller, pci_controller);
  55. }
  56. static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
  57. int where, int size, u32 value)
  58. {
  59. void __iomem *base;
  60. u32 data;
  61. int s;
  62. WARN_ON(where & (size - 1));
  63. if (!apc->link_up)
  64. return PCIBIOS_DEVICE_NOT_FOUND;
  65. base = apc->crp_base;
  66. data = __raw_readl(base + (where & ~3));
  67. switch (size) {
  68. case 1:
  69. s = ((where & 3) * 8);
  70. data &= ~(0xff << s);
  71. data |= ((value & 0xff) << s);
  72. break;
  73. case 2:
  74. s = ((where & 2) * 8);
  75. data &= ~(0xffff << s);
  76. data |= ((value & 0xffff) << s);
  77. break;
  78. case 4:
  79. data = value;
  80. break;
  81. default:
  82. return PCIBIOS_BAD_REGISTER_NUMBER;
  83. }
  84. __raw_writel(data, base + (where & ~3));
  85. /* flush write */
  86. __raw_readl(base + (where & ~3));
  87. return PCIBIOS_SUCCESSFUL;
  88. }
  89. static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  90. int size, uint32_t *value)
  91. {
  92. struct ar724x_pci_controller *apc;
  93. void __iomem *base;
  94. u32 data;
  95. apc = pci_bus_to_ar724x_controller(bus);
  96. if (!apc->link_up)
  97. return PCIBIOS_DEVICE_NOT_FOUND;
  98. if (devfn)
  99. return PCIBIOS_DEVICE_NOT_FOUND;
  100. base = apc->devcfg_base;
  101. data = __raw_readl(base + (where & ~3));
  102. switch (size) {
  103. case 1:
  104. if (where & 1)
  105. data >>= 8;
  106. if (where & 2)
  107. data >>= 16;
  108. data &= 0xff;
  109. break;
  110. case 2:
  111. if (where & 2)
  112. data >>= 16;
  113. data &= 0xffff;
  114. break;
  115. case 4:
  116. break;
  117. default:
  118. return PCIBIOS_BAD_REGISTER_NUMBER;
  119. }
  120. if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
  121. apc->bar0_is_cached) {
  122. /* use the cached value */
  123. *value = apc->bar0_value;
  124. } else {
  125. *value = data;
  126. }
  127. return PCIBIOS_SUCCESSFUL;
  128. }
  129. static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
  130. int size, uint32_t value)
  131. {
  132. struct ar724x_pci_controller *apc;
  133. void __iomem *base;
  134. u32 data;
  135. int s;
  136. apc = pci_bus_to_ar724x_controller(bus);
  137. if (!apc->link_up)
  138. return PCIBIOS_DEVICE_NOT_FOUND;
  139. if (devfn)
  140. return PCIBIOS_DEVICE_NOT_FOUND;
  141. if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
  142. if (value != 0xffffffff) {
  143. /*
  144. * WAR for a hw issue. If the BAR0 register of the
  145. * device is set to the proper base address, the
  146. * memory space of the device is not accessible.
  147. *
  148. * Cache the intended value so it can be read back,
  149. * and write a SoC specific constant value to the
  150. * BAR0 register in order to make the device memory
  151. * accessible.
  152. */
  153. apc->bar0_is_cached = true;
  154. apc->bar0_value = value;
  155. value = AR7240_BAR0_WAR_VALUE;
  156. } else {
  157. apc->bar0_is_cached = false;
  158. }
  159. }
  160. base = apc->devcfg_base;
  161. data = __raw_readl(base + (where & ~3));
  162. switch (size) {
  163. case 1:
  164. s = ((where & 3) * 8);
  165. data &= ~(0xff << s);
  166. data |= ((value & 0xff) << s);
  167. break;
  168. case 2:
  169. s = ((where & 2) * 8);
  170. data &= ~(0xffff << s);
  171. data |= ((value & 0xffff) << s);
  172. break;
  173. case 4:
  174. data = value;
  175. break;
  176. default:
  177. return PCIBIOS_BAD_REGISTER_NUMBER;
  178. }
  179. __raw_writel(data, base + (where & ~3));
  180. /* flush write */
  181. __raw_readl(base + (where & ~3));
  182. return PCIBIOS_SUCCESSFUL;
  183. }
  184. static struct pci_ops ar724x_pci_ops = {
  185. .read = ar724x_pci_read,
  186. .write = ar724x_pci_write,
  187. };
  188. static void ar724x_pci_irq_handler(struct irq_desc *desc)
  189. {
  190. struct ar724x_pci_controller *apc;
  191. void __iomem *base;
  192. u32 pending;
  193. apc = irq_desc_get_handler_data(desc);
  194. base = apc->ctrl_base;
  195. pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
  196. __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  197. if (pending & AR724X_PCI_INT_DEV0)
  198. generic_handle_irq(apc->irq_base + 0);
  199. else
  200. spurious_interrupt();
  201. }
  202. static void ar724x_pci_irq_unmask(struct irq_data *d)
  203. {
  204. struct ar724x_pci_controller *apc;
  205. void __iomem *base;
  206. int offset;
  207. u32 t;
  208. apc = irq_data_get_irq_chip_data(d);
  209. base = apc->ctrl_base;
  210. offset = apc->irq_base - d->irq;
  211. switch (offset) {
  212. case 0:
  213. t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  214. __raw_writel(t | AR724X_PCI_INT_DEV0,
  215. base + AR724X_PCI_REG_INT_MASK);
  216. /* flush write */
  217. __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  218. }
  219. }
  220. static void ar724x_pci_irq_mask(struct irq_data *d)
  221. {
  222. struct ar724x_pci_controller *apc;
  223. void __iomem *base;
  224. int offset;
  225. u32 t;
  226. apc = irq_data_get_irq_chip_data(d);
  227. base = apc->ctrl_base;
  228. offset = apc->irq_base - d->irq;
  229. switch (offset) {
  230. case 0:
  231. t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  232. __raw_writel(t & ~AR724X_PCI_INT_DEV0,
  233. base + AR724X_PCI_REG_INT_MASK);
  234. /* flush write */
  235. __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  236. t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
  237. __raw_writel(t | AR724X_PCI_INT_DEV0,
  238. base + AR724X_PCI_REG_INT_STATUS);
  239. /* flush write */
  240. __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
  241. }
  242. }
  243. static struct irq_chip ar724x_pci_irq_chip = {
  244. .name = "AR724X PCI ",
  245. .irq_mask = ar724x_pci_irq_mask,
  246. .irq_unmask = ar724x_pci_irq_unmask,
  247. .irq_mask_ack = ar724x_pci_irq_mask,
  248. };
  249. static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
  250. int id)
  251. {
  252. void __iomem *base;
  253. int i;
  254. base = apc->ctrl_base;
  255. __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
  256. __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
  257. apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
  258. for (i = apc->irq_base;
  259. i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
  260. irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
  261. handle_level_irq);
  262. irq_set_chip_data(i, apc);
  263. }
  264. irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
  265. apc);
  266. }
  267. static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
  268. {
  269. u32 ppl, app;
  270. int wait = 0;
  271. /* deassert PCIe host controller and PCIe PHY reset */
  272. ath79_device_reset_clear(AR724X_RESET_PCIE);
  273. ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
  274. /* remove the reset of the PCIE PLL */
  275. ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  276. ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
  277. ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  278. /* deassert bypass for the PCIE PLL */
  279. ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  280. ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  281. ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  282. /* set PCIE Application Control to ready */
  283. app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
  284. app |= AR724X_PCI_APP_LTSSM_ENABLE;
  285. __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
  286. /* wait up to 100ms for PHY link up */
  287. do {
  288. mdelay(10);
  289. wait++;
  290. } while (wait < 10 && !ar724x_pci_check_link(apc));
  291. }
  292. static int ar724x_pci_probe(struct platform_device *pdev)
  293. {
  294. struct ar724x_pci_controller *apc;
  295. struct resource *res;
  296. int id;
  297. id = pdev->id;
  298. if (id == -1)
  299. id = 0;
  300. apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
  301. GFP_KERNEL);
  302. if (!apc)
  303. return -ENOMEM;
  304. apc->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl_base");
  305. if (IS_ERR(apc->ctrl_base))
  306. return PTR_ERR(apc->ctrl_base);
  307. apc->devcfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg_base");
  308. if (IS_ERR(apc->devcfg_base))
  309. return PTR_ERR(apc->devcfg_base);
  310. apc->crp_base = devm_platform_ioremap_resource_byname(pdev, "crp_base");
  311. if (IS_ERR(apc->crp_base))
  312. return PTR_ERR(apc->crp_base);
  313. apc->irq = platform_get_irq(pdev, 0);
  314. if (apc->irq < 0)
  315. return -EINVAL;
  316. res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
  317. if (!res)
  318. return -EINVAL;
  319. apc->io_res.parent = res;
  320. apc->io_res.name = "PCI IO space";
  321. apc->io_res.start = res->start;
  322. apc->io_res.end = res->end;
  323. apc->io_res.flags = IORESOURCE_IO;
  324. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
  325. if (!res)
  326. return -EINVAL;
  327. apc->mem_res.parent = res;
  328. apc->mem_res.name = "PCI memory space";
  329. apc->mem_res.start = res->start;
  330. apc->mem_res.end = res->end;
  331. apc->mem_res.flags = IORESOURCE_MEM;
  332. apc->pci_controller.pci_ops = &ar724x_pci_ops;
  333. apc->pci_controller.io_resource = &apc->io_res;
  334. apc->pci_controller.mem_resource = &apc->mem_res;
  335. /*
  336. * Do the full PCIE Root Complex Initialization Sequence if the PCIe
  337. * host controller is in reset.
  338. */
  339. if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
  340. ar724x_pci_hw_init(apc);
  341. apc->link_up = ar724x_pci_check_link(apc);
  342. if (!apc->link_up)
  343. dev_warn(&pdev->dev, "PCIe link is down\n");
  344. ar724x_pci_irq_init(apc, id);
  345. ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
  346. register_pci_controller(&apc->pci_controller);
  347. return 0;
  348. }
  349. static struct platform_driver ar724x_pci_driver = {
  350. .probe = ar724x_pci_probe,
  351. .driver = {
  352. .name = "ar724x-pci",
  353. },
  354. };
  355. static int __init ar724x_pci_init(void)
  356. {
  357. return platform_driver_register(&ar724x_pci_driver);
  358. }
  359. postcore_initcall(ar724x_pci_init);