pci-ar2315.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. */
  4. /**
  5. * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  6. * and interrupt. PCI interface supports MMIO access method, but does not
  7. * seem to support I/O ports.
  8. *
  9. * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  10. * a memory read/write command on the PCI bus. 30 LSBs of address on
  11. * the bus are taken from memory read/write request and 2 MSBs are
  12. * determined by PCI unit configuration.
  13. *
  14. * To work with the configuration space instead of memory is necessary set
  15. * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  16. *
  17. * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  18. * controller BARs are programmend as if an external device is programmed.
  19. * Which means that during configuration, IDSEL pin of the chip should be
  20. * asserted.
  21. *
  22. * We know (and support) only one board that uses the PCI interface -
  23. * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  24. * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  25. * and IDSEL pin of AR2315 is connected to AD[16] line.
  26. */
  27. #include <linux/types.h>
  28. #include <linux/pci.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/kernel.h>
  31. #include <linux/init.h>
  32. #include <linux/mm.h>
  33. #include <linux/delay.h>
  34. #include <linux/bitops.h>
  35. #include <linux/irq.h>
  36. #include <linux/irqdomain.h>
  37. #include <linux/io.h>
  38. #include <asm/paccess.h>
  39. /*
  40. * PCI Bus Interface Registers
  41. */
  42. #define AR2315_PCI_1MS_REG 0x0008
  43. #define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
  44. #define AR2315_PCI_MISC_CONFIG 0x000c
  45. #define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
  46. #define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
  47. #define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
  48. #define AR2315_PCIMISC_RST_MODE 0x00000030
  49. #define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
  50. #define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
  51. #define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
  52. #define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
  53. #define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
  54. #define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
  55. #define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
  56. #define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
  57. * disable */
  58. #define AR2315_PCI_OUT_TSTAMP 0x0010
  59. #define AR2315_PCI_UNCACHE_CFG 0x0014
  60. #define AR2315_PCI_IN_EN 0x0100
  61. #define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
  62. #define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
  63. #define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
  64. #define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
  65. #define AR2315_PCI_IN_DIS 0x0104
  66. #define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
  67. #define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
  68. #define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
  69. #define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
  70. #define AR2315_PCI_IN_PTR 0x0200
  71. #define AR2315_PCI_OUT_EN 0x0400
  72. #define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
  73. #define AR2315_PCI_OUT_DIS 0x0404
  74. #define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
  75. #define AR2315_PCI_OUT_PTR 0x0408
  76. /* PCI interrupt status (write one to clear) */
  77. #define AR2315_PCI_ISR 0x0500
  78. #define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
  79. #define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
  80. #define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
  81. #define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
  82. #define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
  83. #define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
  84. #define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
  85. #define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
  86. #define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
  87. #define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
  88. #define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
  89. #define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
  90. /* PCI interrupt mask */
  91. #define AR2315_PCI_IMR 0x0504
  92. /* Global PCI interrupt enable */
  93. #define AR2315_PCI_IER 0x0508
  94. #define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
  95. #define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
  96. #define AR2315_PCI_HOST_IN_EN 0x0800
  97. #define AR2315_PCI_HOST_IN_DIS 0x0804
  98. #define AR2315_PCI_HOST_IN_PTR 0x0810
  99. #define AR2315_PCI_HOST_OUT_EN 0x0900
  100. #define AR2315_PCI_HOST_OUT_DIS 0x0904
  101. #define AR2315_PCI_HOST_OUT_PTR 0x0908
  102. /*
  103. * PCI interrupts, which share IP5
  104. * Keep ordered according to AR2315_PCI_INT_XXX bits
  105. */
  106. #define AR2315_PCI_IRQ_EXT 25
  107. #define AR2315_PCI_IRQ_ABORT 26
  108. #define AR2315_PCI_IRQ_COUNT 27
  109. /* Arbitrary size of memory region to access the configuration space */
  110. #define AR2315_PCI_CFG_SIZE 0x00100000
  111. #define AR2315_PCI_HOST_SLOT 3
  112. #define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
  113. /*
  114. * We need some arbitrary non-zero value to be programmed to the BAR1 register
  115. * of PCI host controller to enable DMA. The same value should be used as the
  116. * offset to calculate the physical address of DMA buffer for PCI devices.
  117. */
  118. #define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
  119. /* ??? access BAR */
  120. #define AR2315_PCI_HOST_MBAR0 0x10000000
  121. /* RAM access BAR */
  122. #define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
  123. /* ??? access BAR */
  124. #define AR2315_PCI_HOST_MBAR2 0x30000000
  125. struct ar2315_pci_ctrl {
  126. void __iomem *cfg_mem;
  127. void __iomem *mmr_mem;
  128. unsigned irq;
  129. unsigned irq_ext;
  130. struct irq_domain *domain;
  131. struct pci_controller pci_ctrl;
  132. struct resource mem_res;
  133. struct resource io_res;
  134. };
  135. static inline dma_addr_t ar2315_dev_offset(struct device *dev)
  136. {
  137. if (dev && dev_is_pci(dev))
  138. return AR2315_PCI_HOST_SDRAM_BASEADDR;
  139. return 0;
  140. }
  141. dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
  142. {
  143. return paddr + ar2315_dev_offset(dev);
  144. }
  145. phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
  146. {
  147. return dma_addr - ar2315_dev_offset(dev);
  148. }
  149. static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
  150. {
  151. struct pci_controller *hose = bus->sysdata;
  152. return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
  153. }
  154. static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
  155. {
  156. return __raw_readl(apc->mmr_mem + reg);
  157. }
  158. static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
  159. u32 val)
  160. {
  161. __raw_writel(val, apc->mmr_mem + reg);
  162. }
  163. static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
  164. u32 mask, u32 val)
  165. {
  166. u32 ret = ar2315_pci_reg_read(apc, reg);
  167. ret &= ~mask;
  168. ret |= val;
  169. ar2315_pci_reg_write(apc, reg, ret);
  170. }
  171. static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
  172. int where, int size, u32 *ptr, bool write)
  173. {
  174. int func = PCI_FUNC(devfn);
  175. int dev = PCI_SLOT(devfn);
  176. u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
  177. u32 mask = 0xffffffff >> 8 * (4 - size);
  178. u32 sh = (where & 3) * 8;
  179. u32 value, isr;
  180. /* Prevent access past the remapped area */
  181. if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
  182. return PCIBIOS_DEVICE_NOT_FOUND;
  183. /* Clear pending errors */
  184. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  185. /* Select Configuration access */
  186. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
  187. AR2315_PCIMISC_CFG_SEL);
  188. mb(); /* PCI must see space change before we begin */
  189. value = __raw_readl(apc->cfg_mem + addr);
  190. isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
  191. if (isr & AR2315_PCI_INT_ABORT)
  192. goto exit_err;
  193. if (write) {
  194. value = (value & ~(mask << sh)) | *ptr << sh;
  195. __raw_writel(value, apc->cfg_mem + addr);
  196. isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
  197. if (isr & AR2315_PCI_INT_ABORT)
  198. goto exit_err;
  199. } else {
  200. *ptr = (value >> sh) & mask;
  201. }
  202. goto exit;
  203. exit_err:
  204. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  205. if (!write)
  206. *ptr = 0xffffffff;
  207. exit:
  208. /* Select Memory access */
  209. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
  210. 0);
  211. return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
  212. PCIBIOS_SUCCESSFUL;
  213. }
  214. static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
  215. unsigned devfn, int where, u32 *val)
  216. {
  217. return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
  218. false);
  219. }
  220. static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
  221. unsigned devfn, int where, u32 val)
  222. {
  223. return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
  224. true);
  225. }
  226. static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
  227. int size, u32 *value)
  228. {
  229. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
  230. if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
  231. return PCIBIOS_DEVICE_NOT_FOUND;
  232. return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
  233. }
  234. static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
  235. int size, u32 value)
  236. {
  237. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
  238. if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
  239. return PCIBIOS_DEVICE_NOT_FOUND;
  240. return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
  241. }
  242. static struct pci_ops ar2315_pci_ops = {
  243. .read = ar2315_pci_cfg_read,
  244. .write = ar2315_pci_cfg_write,
  245. };
  246. static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
  247. {
  248. unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
  249. int res;
  250. u32 id;
  251. res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
  252. if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
  253. return -ENODEV;
  254. /* Program MBARs */
  255. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
  256. AR2315_PCI_HOST_MBAR0);
  257. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
  258. AR2315_PCI_HOST_MBAR1);
  259. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
  260. AR2315_PCI_HOST_MBAR2);
  261. /* Run */
  262. ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
  263. PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
  264. PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
  265. PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
  266. return 0;
  267. }
  268. static void ar2315_pci_irq_handler(struct irq_desc *desc)
  269. {
  270. struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
  271. u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
  272. ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
  273. unsigned pci_irq = 0;
  274. if (pending)
  275. pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
  276. if (pci_irq)
  277. generic_handle_irq(pci_irq);
  278. else
  279. spurious_interrupt();
  280. }
  281. static void ar2315_pci_irq_mask(struct irq_data *d)
  282. {
  283. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  284. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
  285. }
  286. static void ar2315_pci_irq_mask_ack(struct irq_data *d)
  287. {
  288. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  289. u32 m = BIT(d->hwirq);
  290. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
  291. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
  292. }
  293. static void ar2315_pci_irq_unmask(struct irq_data *d)
  294. {
  295. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  296. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
  297. }
  298. static struct irq_chip ar2315_pci_irq_chip = {
  299. .name = "AR2315-PCI",
  300. .irq_mask = ar2315_pci_irq_mask,
  301. .irq_mask_ack = ar2315_pci_irq_mask_ack,
  302. .irq_unmask = ar2315_pci_irq_unmask,
  303. };
  304. static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
  305. irq_hw_number_t hw)
  306. {
  307. irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
  308. irq_set_chip_data(irq, d->host_data);
  309. return 0;
  310. }
  311. static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
  312. .map = ar2315_pci_irq_map,
  313. };
  314. static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
  315. {
  316. ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
  317. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
  318. AR2315_PCI_INT_EXT), 0);
  319. apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
  320. irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
  321. apc);
  322. /* Clear any pending Abort or external Interrupts
  323. * and enable interrupt processing */
  324. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
  325. AR2315_PCI_INT_EXT);
  326. ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
  327. }
  328. static int ar2315_pci_probe(struct platform_device *pdev)
  329. {
  330. struct ar2315_pci_ctrl *apc;
  331. struct device *dev = &pdev->dev;
  332. struct resource *res;
  333. int irq, err;
  334. apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
  335. if (!apc)
  336. return -ENOMEM;
  337. irq = platform_get_irq(pdev, 0);
  338. if (irq < 0)
  339. return -EINVAL;
  340. apc->irq = irq;
  341. apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
  342. "ar2315-pci-ctrl");
  343. if (IS_ERR(apc->mmr_mem))
  344. return PTR_ERR(apc->mmr_mem);
  345. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  346. "ar2315-pci-ext");
  347. if (!res)
  348. return -EINVAL;
  349. apc->mem_res.name = "AR2315 PCI mem space";
  350. apc->mem_res.parent = res;
  351. apc->mem_res.start = res->start;
  352. apc->mem_res.end = res->end;
  353. apc->mem_res.flags = IORESOURCE_MEM;
  354. /* Remap PCI config space */
  355. apc->cfg_mem = devm_ioremap(dev, res->start,
  356. AR2315_PCI_CFG_SIZE);
  357. if (!apc->cfg_mem) {
  358. dev_err(dev, "failed to remap PCI config space\n");
  359. return -ENOMEM;
  360. }
  361. /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
  362. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
  363. AR2315_PCIMISC_RST_MODE,
  364. AR2315_PCIRST_LOW);
  365. msleep(100);
  366. /* Bring the PCI out of reset */
  367. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
  368. AR2315_PCIMISC_RST_MODE,
  369. AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
  370. ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
  371. 0x1E | /* 1GB uncached */
  372. (1 << 5) | /* Enable uncached */
  373. (0x2 << 30) /* Base: 0x80000000 */);
  374. ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
  375. msleep(500);
  376. err = ar2315_pci_host_setup(apc);
  377. if (err)
  378. return err;
  379. apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
  380. &ar2315_pci_irq_domain_ops, apc);
  381. if (!apc->domain) {
  382. dev_err(dev, "failed to add IRQ domain\n");
  383. return -ENOMEM;
  384. }
  385. ar2315_pci_irq_init(apc);
  386. /* PCI controller does not support I/O ports */
  387. apc->io_res.name = "AR2315 IO space";
  388. apc->io_res.start = 0;
  389. apc->io_res.end = 0;
  390. apc->io_res.flags = IORESOURCE_IO,
  391. apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
  392. apc->pci_ctrl.mem_resource = &apc->mem_res,
  393. apc->pci_ctrl.io_resource = &apc->io_res,
  394. register_pci_controller(&apc->pci_ctrl);
  395. dev_info(dev, "register PCI controller\n");
  396. return 0;
  397. }
  398. static struct platform_driver ar2315_pci_driver = {
  399. .probe = ar2315_pci_probe,
  400. .driver = {
  401. .name = "ar2315-pci",
  402. },
  403. };
  404. static int __init ar2315_pci_init(void)
  405. {
  406. return platform_driver_register(&ar2315_pci_driver);
  407. }
  408. arch_initcall(ar2315_pci_init);
  409. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  410. {
  411. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
  412. return slot ? 0 : apc->irq_ext;
  413. }
  414. int pcibios_plat_dev_init(struct pci_dev *dev)
  415. {
  416. return 0;
  417. }