pci-alchemy.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Alchemy PCI host mode support.
  4. *
  5. * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc. <source@mvista.com>
  7. *
  8. * Support for all devices (greater than 16) added by David Gathright.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/export.h>
  12. #include <linux/types.h>
  13. #include <linux/pci.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/syscore_ops.h>
  18. #include <linux/vmalloc.h>
  19. #include <asm/dma-coherence.h>
  20. #include <asm/mach-au1x00/au1000.h>
  21. #include <asm/tlbmisc.h>
  22. #ifdef CONFIG_PCI_DEBUG
  23. #define DBG(x...) printk(KERN_DEBUG x)
  24. #else
  25. #define DBG(x...) do {} while (0)
  26. #endif
  27. #define PCI_ACCESS_READ 0
  28. #define PCI_ACCESS_WRITE 1
  29. struct alchemy_pci_context {
  30. struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
  31. void __iomem *regs; /* ctrl base */
  32. /* tools for wired entry for config space access */
  33. unsigned long last_elo0;
  34. unsigned long last_elo1;
  35. int wired_entry;
  36. struct vm_struct *pci_cfg_vm;
  37. unsigned long pm[12];
  38. int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
  39. int (*board_pci_idsel)(unsigned int devsel, int assert);
  40. };
  41. /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
  42. * should suffice for now.
  43. */
  44. static struct alchemy_pci_context *__alchemy_pci_ctx;
  45. /* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr
  46. * in arch/mips/alchemy/common/setup.c
  47. */
  48. static struct resource alchemy_pci_def_memres = {
  49. .start = ALCHEMY_PCI_MEMWIN_START,
  50. .end = ALCHEMY_PCI_MEMWIN_END,
  51. .name = "PCI memory space",
  52. .flags = IORESOURCE_MEM
  53. };
  54. static struct resource alchemy_pci_def_iores = {
  55. .start = ALCHEMY_PCI_IOWIN_START,
  56. .end = ALCHEMY_PCI_IOWIN_END,
  57. .name = "PCI IO space",
  58. .flags = IORESOURCE_IO
  59. };
  60. static void mod_wired_entry(int entry, unsigned long entrylo0,
  61. unsigned long entrylo1, unsigned long entryhi,
  62. unsigned long pagemask)
  63. {
  64. unsigned long old_pagemask;
  65. unsigned long old_ctx;
  66. /* Save old context and create impossible VPN2 value */
  67. old_ctx = read_c0_entryhi() & MIPS_ENTRYHI_ASID;
  68. old_pagemask = read_c0_pagemask();
  69. write_c0_index(entry);
  70. write_c0_pagemask(pagemask);
  71. write_c0_entryhi(entryhi);
  72. write_c0_entrylo0(entrylo0);
  73. write_c0_entrylo1(entrylo1);
  74. tlb_write_indexed();
  75. write_c0_entryhi(old_ctx);
  76. write_c0_pagemask(old_pagemask);
  77. }
  78. static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
  79. {
  80. ctx->wired_entry = read_c0_wired();
  81. add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
  82. ctx->last_elo0 = ctx->last_elo1 = ~0;
  83. }
  84. static int config_access(unsigned char access_type, struct pci_bus *bus,
  85. unsigned int dev_fn, unsigned char where, u32 *data)
  86. {
  87. struct alchemy_pci_context *ctx = bus->sysdata;
  88. unsigned int device = PCI_SLOT(dev_fn);
  89. unsigned int function = PCI_FUNC(dev_fn);
  90. unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
  91. int error = PCIBIOS_SUCCESSFUL;
  92. if (device > 19) {
  93. *data = 0xffffffff;
  94. return -1;
  95. }
  96. local_irq_save(flags);
  97. r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
  98. r |= PCI_STATCMD_STATUS(0x2000);
  99. __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
  100. wmb();
  101. /* Allow board vendors to implement their own off-chip IDSEL.
  102. * If it doesn't succeed, may as well bail out at this point.
  103. */
  104. if (ctx->board_pci_idsel(device, 1) == 0) {
  105. *data = 0xffffffff;
  106. local_irq_restore(flags);
  107. return -1;
  108. }
  109. /* Setup the config window */
  110. if (bus->number == 0)
  111. cfg_base = (1 << device) << 11;
  112. else
  113. cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
  114. /* Setup the lower bits of the 36-bit address */
  115. offset = (function << 8) | (where & ~0x3);
  116. /* Pick up any address that falls below the page mask */
  117. offset |= cfg_base & ~PAGE_MASK;
  118. /* Page boundary */
  119. cfg_base = cfg_base & PAGE_MASK;
  120. /* To improve performance, if the current device is the same as
  121. * the last device accessed, we don't touch the TLB.
  122. */
  123. entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
  124. entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
  125. if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
  126. mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
  127. (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
  128. ctx->last_elo0 = entryLo0;
  129. ctx->last_elo1 = entryLo1;
  130. }
  131. if (access_type == PCI_ACCESS_WRITE)
  132. __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
  133. else
  134. *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
  135. wmb();
  136. DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
  137. access_type, bus->number, device, where, *data, offset);
  138. /* check for errors, master abort */
  139. status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
  140. if (status & (1 << 29)) {
  141. *data = 0xffffffff;
  142. error = -1;
  143. DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
  144. access_type, bus->number, device);
  145. } else if ((status >> 28) & 0xf) {
  146. DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
  147. device, (status >> 28) & 0xf);
  148. /* clear errors */
  149. __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
  150. *data = 0xffffffff;
  151. error = -1;
  152. }
  153. /* Take away the IDSEL. */
  154. (void)ctx->board_pci_idsel(device, 0);
  155. local_irq_restore(flags);
  156. return error;
  157. }
  158. static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
  159. int where, u8 *val)
  160. {
  161. u32 data;
  162. int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  163. if (where & 1)
  164. data >>= 8;
  165. if (where & 2)
  166. data >>= 16;
  167. *val = data & 0xff;
  168. return ret;
  169. }
  170. static int read_config_word(struct pci_bus *bus, unsigned int devfn,
  171. int where, u16 *val)
  172. {
  173. u32 data;
  174. int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  175. if (where & 2)
  176. data >>= 16;
  177. *val = data & 0xffff;
  178. return ret;
  179. }
  180. static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
  181. int where, u32 *val)
  182. {
  183. return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
  184. }
  185. static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
  186. int where, u8 val)
  187. {
  188. u32 data = 0;
  189. if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  190. return -1;
  191. data = (data & ~(0xff << ((where & 3) << 3))) |
  192. (val << ((where & 3) << 3));
  193. if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  194. return -1;
  195. return PCIBIOS_SUCCESSFUL;
  196. }
  197. static int write_config_word(struct pci_bus *bus, unsigned int devfn,
  198. int where, u16 val)
  199. {
  200. u32 data = 0;
  201. if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  202. return -1;
  203. data = (data & ~(0xffff << ((where & 3) << 3))) |
  204. (val << ((where & 3) << 3));
  205. if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  206. return -1;
  207. return PCIBIOS_SUCCESSFUL;
  208. }
  209. static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
  210. int where, u32 val)
  211. {
  212. return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
  213. }
  214. static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
  215. int where, int size, u32 *val)
  216. {
  217. switch (size) {
  218. case 1: {
  219. u8 _val;
  220. int rc = read_config_byte(bus, devfn, where, &_val);
  221. *val = _val;
  222. return rc;
  223. }
  224. case 2: {
  225. u16 _val;
  226. int rc = read_config_word(bus, devfn, where, &_val);
  227. *val = _val;
  228. return rc;
  229. }
  230. default:
  231. return read_config_dword(bus, devfn, where, val);
  232. }
  233. }
  234. static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
  235. int where, int size, u32 val)
  236. {
  237. switch (size) {
  238. case 1:
  239. return write_config_byte(bus, devfn, where, (u8) val);
  240. case 2:
  241. return write_config_word(bus, devfn, where, (u16) val);
  242. default:
  243. return write_config_dword(bus, devfn, where, val);
  244. }
  245. }
  246. static struct pci_ops alchemy_pci_ops = {
  247. .read = alchemy_pci_read,
  248. .write = alchemy_pci_write,
  249. };
  250. static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
  251. {
  252. return 1; /* success */
  253. }
  254. /* save PCI controller register contents. */
  255. static int alchemy_pci_suspend(void)
  256. {
  257. struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
  258. if (!ctx)
  259. return 0;
  260. ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
  261. ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
  262. ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
  263. ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
  264. ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
  265. ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
  266. ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
  267. ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
  268. ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
  269. ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
  270. ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
  271. ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
  272. return 0;
  273. }
  274. static void alchemy_pci_resume(void)
  275. {
  276. struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
  277. if (!ctx)
  278. return;
  279. __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
  280. __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
  281. __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
  282. __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
  283. __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
  284. __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
  285. __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
  286. __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
  287. __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
  288. __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
  289. __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
  290. wmb();
  291. __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
  292. wmb();
  293. /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
  294. * on resume, making it necessary to recreate it as soon as possible.
  295. */
  296. ctx->wired_entry = 8191; /* impossibly high value */
  297. alchemy_pci_wired_entry(ctx); /* install it */
  298. }
  299. static struct syscore_ops alchemy_pci_pmops = {
  300. .suspend = alchemy_pci_suspend,
  301. .resume = alchemy_pci_resume,
  302. };
  303. static int alchemy_pci_probe(struct platform_device *pdev)
  304. {
  305. struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
  306. struct alchemy_pci_context *ctx;
  307. void __iomem *virt_io;
  308. unsigned long val;
  309. struct resource *r;
  310. struct clk *c;
  311. int ret;
  312. /* need at least PCI IRQ mapping table */
  313. if (!pd) {
  314. dev_err(&pdev->dev, "need platform data for PCI setup\n");
  315. ret = -ENODEV;
  316. goto out;
  317. }
  318. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  319. if (!ctx) {
  320. dev_err(&pdev->dev, "no memory for pcictl context\n");
  321. ret = -ENOMEM;
  322. goto out;
  323. }
  324. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  325. if (!r) {
  326. dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
  327. ret = -ENODEV;
  328. goto out1;
  329. }
  330. if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
  331. dev_err(&pdev->dev, "cannot claim pci regs\n");
  332. ret = -ENODEV;
  333. goto out1;
  334. }
  335. c = clk_get(&pdev->dev, "pci_clko");
  336. if (IS_ERR(c)) {
  337. dev_err(&pdev->dev, "unable to find PCI clock\n");
  338. ret = PTR_ERR(c);
  339. goto out2;
  340. }
  341. ret = clk_prepare_enable(c);
  342. if (ret) {
  343. dev_err(&pdev->dev, "cannot enable PCI clock\n");
  344. goto out6;
  345. }
  346. ctx->regs = ioremap(r->start, resource_size(r));
  347. if (!ctx->regs) {
  348. dev_err(&pdev->dev, "cannot map pci regs\n");
  349. ret = -ENODEV;
  350. goto out5;
  351. }
  352. /* map parts of the PCI IO area */
  353. /* REVISIT: if this changes with a newer variant (doubt it) make this
  354. * a platform resource.
  355. */
  356. virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
  357. if (!virt_io) {
  358. dev_err(&pdev->dev, "cannot remap pci io space\n");
  359. ret = -ENODEV;
  360. goto out3;
  361. }
  362. ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
  363. /* Au1500 revisions older than AD have borked coherent PCI */
  364. if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
  365. (read_c0_prid() < 0x01030202) &&
  366. (coherentio == IO_COHERENCE_DISABLED)) {
  367. val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
  368. val |= PCI_CONFIG_NC;
  369. __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
  370. wmb();
  371. dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
  372. }
  373. if (pd->board_map_irq)
  374. ctx->board_map_irq = pd->board_map_irq;
  375. if (pd->board_pci_idsel)
  376. ctx->board_pci_idsel = pd->board_pci_idsel;
  377. else
  378. ctx->board_pci_idsel = alchemy_pci_def_idsel;
  379. /* fill in relevant pci_controller members */
  380. ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
  381. ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
  382. ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
  383. /* we can't ioremap the entire pci config space because it's too large,
  384. * nor can we dynamically ioremap it because some drivers use the
  385. * PCI config routines from within atomic contex and that becomes a
  386. * problem in get_vm_area(). Instead we use one wired TLB entry to
  387. * handle all config accesses for all busses.
  388. */
  389. ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
  390. if (!ctx->pci_cfg_vm) {
  391. dev_err(&pdev->dev, "unable to get vm area\n");
  392. ret = -ENOMEM;
  393. goto out4;
  394. }
  395. ctx->wired_entry = 8191; /* impossibly high value */
  396. alchemy_pci_wired_entry(ctx); /* install it */
  397. set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
  398. /* board may want to modify bits in the config register, do it now */
  399. val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
  400. val &= ~pd->pci_cfg_clr;
  401. val |= pd->pci_cfg_set;
  402. val &= ~PCI_CONFIG_PD; /* clear disable bit */
  403. __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
  404. wmb();
  405. __alchemy_pci_ctx = ctx;
  406. platform_set_drvdata(pdev, ctx);
  407. register_syscore_ops(&alchemy_pci_pmops);
  408. register_pci_controller(&ctx->alchemy_pci_ctrl);
  409. dev_info(&pdev->dev, "PCI controller at %ld MHz\n",
  410. clk_get_rate(c) / 1000000);
  411. return 0;
  412. out4:
  413. iounmap(virt_io);
  414. out3:
  415. iounmap(ctx->regs);
  416. out5:
  417. clk_disable_unprepare(c);
  418. out6:
  419. clk_put(c);
  420. out2:
  421. release_mem_region(r->start, resource_size(r));
  422. out1:
  423. kfree(ctx);
  424. out:
  425. return ret;
  426. }
  427. static struct platform_driver alchemy_pcictl_driver = {
  428. .probe = alchemy_pci_probe,
  429. .driver = {
  430. .name = "alchemy-pci",
  431. },
  432. };
  433. static int __init alchemy_pci_init(void)
  434. {
  435. /* Au1500/Au1550 have PCI */
  436. switch (alchemy_get_cputype()) {
  437. case ALCHEMY_CPU_AU1500:
  438. case ALCHEMY_CPU_AU1550:
  439. return platform_driver_register(&alchemy_pcictl_driver);
  440. }
  441. return 0;
  442. }
  443. arch_initcall(alchemy_pci_init);
  444. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  445. {
  446. struct alchemy_pci_context *ctx = dev->sysdata;
  447. if (ctx && ctx->board_map_irq)
  448. return ctx->board_map_irq(dev, slot, pin);
  449. return -1;
  450. }
  451. int pcibios_plat_dev_init(struct pci_dev *dev)
  452. {
  453. return 0;
  454. }