ops-rc32434.c 5.2 KB

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  1. /*
  2. * BRIEF MODULE DESCRIPTION
  3. * pci_ops for IDT EB434 board
  4. *
  5. * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6. * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  16. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  17. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  19. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23. *
  24. * You should have received a copy of the GNU General Public License along
  25. * with this program; if not, write to the Free Software Foundation, Inc.,
  26. * 675 Mass Ave, Cambridge, MA 02139, USA.
  27. */
  28. #include <linux/delay.h>
  29. #include <linux/io.h>
  30. #include <linux/pci.h>
  31. #include <linux/types.h>
  32. #include <asm/cpu.h>
  33. #include <asm/mach-rc32434/rc32434.h>
  34. #include <asm/mach-rc32434/pci.h>
  35. #define PCI_ACCESS_READ 0
  36. #define PCI_ACCESS_WRITE 1
  37. #define PCI_CFG_SET(bus, slot, func, off) \
  38. (rc32434_pci->pcicfga = (0x80000000 | \
  39. ((bus) << 16) | ((slot)<<11) | \
  40. ((func)<<8) | (off)))
  41. static inline int config_access(unsigned char access_type,
  42. struct pci_bus *bus, unsigned int devfn,
  43. unsigned char where, u32 *data)
  44. {
  45. unsigned int slot = PCI_SLOT(devfn);
  46. u8 func = PCI_FUNC(devfn);
  47. /* Setup address */
  48. PCI_CFG_SET(bus->number, slot, func, where);
  49. rc32434_sync();
  50. if (access_type == PCI_ACCESS_WRITE)
  51. rc32434_pci->pcicfgd = *data;
  52. else
  53. *data = rc32434_pci->pcicfgd;
  54. rc32434_sync();
  55. return 0;
  56. }
  57. /*
  58. * We can't address 8 and 16 bit words directly. Instead we have to
  59. * read/write a 32bit word and mask/modify the data we actually want.
  60. */
  61. static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
  62. int where, u8 *val)
  63. {
  64. u32 data;
  65. int ret;
  66. ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  67. *val = (data >> ((where & 3) << 3)) & 0xff;
  68. return ret;
  69. }
  70. static int read_config_word(struct pci_bus *bus, unsigned int devfn,
  71. int where, u16 *val)
  72. {
  73. u32 data;
  74. int ret;
  75. ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  76. *val = (data >> ((where & 3) << 3)) & 0xffff;
  77. return ret;
  78. }
  79. static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
  80. int where, u32 *val)
  81. {
  82. int ret;
  83. int delay = 1;
  84. /*
  85. * Don't scan too far, else there will be errors with plugged in
  86. * daughterboard (rb564).
  87. */
  88. if (bus->number == 0 && PCI_SLOT(devfn) > 21)
  89. return 0;
  90. retry:
  91. ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
  92. /*
  93. * Certain devices react delayed at device scan time, this
  94. * gives them time to settle
  95. */
  96. if (where == PCI_VENDOR_ID) {
  97. if (ret == 0xffffffff || ret == 0x00000000 ||
  98. ret == 0x0000ffff || ret == 0xffff0000) {
  99. if (delay > 4)
  100. return 0;
  101. delay *= 2;
  102. msleep(delay);
  103. goto retry;
  104. }
  105. }
  106. return ret;
  107. }
  108. static int
  109. write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
  110. u8 val)
  111. {
  112. u32 data = 0;
  113. if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  114. return -1;
  115. data = (data & ~(0xff << ((where & 3) << 3))) |
  116. (val << ((where & 3) << 3));
  117. if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  118. return -1;
  119. return PCIBIOS_SUCCESSFUL;
  120. }
  121. static int
  122. write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
  123. u16 val)
  124. {
  125. u32 data = 0;
  126. if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  127. return -1;
  128. data = (data & ~(0xffff << ((where & 3) << 3))) |
  129. (val << ((where & 3) << 3));
  130. if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  131. return -1;
  132. return PCIBIOS_SUCCESSFUL;
  133. }
  134. static int
  135. write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
  136. u32 val)
  137. {
  138. if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
  139. return -1;
  140. return PCIBIOS_SUCCESSFUL;
  141. }
  142. static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
  143. int where, int size, u32 *val)
  144. {
  145. switch (size) {
  146. case 1:
  147. return read_config_byte(bus, devfn, where, (u8 *) val);
  148. case 2:
  149. return read_config_word(bus, devfn, where, (u16 *) val);
  150. default:
  151. return read_config_dword(bus, devfn, where, val);
  152. }
  153. }
  154. static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
  155. int where, int size, u32 val)
  156. {
  157. switch (size) {
  158. case 1:
  159. return write_config_byte(bus, devfn, where, (u8) val);
  160. case 2:
  161. return write_config_word(bus, devfn, where, (u16) val);
  162. default:
  163. return write_config_dword(bus, devfn, where, val);
  164. }
  165. }
  166. struct pci_ops rc32434_pci_ops = {
  167. .read = pci_config_read,
  168. .write = pci_config_write,
  169. };