op_model_mipsxx.c 10 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2004, 05, 06 by Ralf Baechle
  7. * Copyright (C) 2005 by MIPS Technologies, Inc.
  8. */
  9. #include <linux/cpumask.h>
  10. #include <linux/oprofile.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/smp.h>
  13. #include <asm/irq_regs.h>
  14. #include <asm/time.h>
  15. #include "op_impl.h"
  16. #define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
  17. MIPS_PERFCTRL_EVENT)
  18. #define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
  19. #define M_COUNTER_OVERFLOW (1UL << 31)
  20. static int (*save_perf_irq)(void);
  21. static int perfcount_irq;
  22. /*
  23. * XLR has only one set of counters per core. Designate the
  24. * first hardware thread in the core for setup and init.
  25. * Skip CPUs with non-zero hardware thread id (4 hwt per core)
  26. */
  27. #if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
  28. #define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
  29. #else
  30. #define oprofile_skip_cpu(c) 0
  31. #endif
  32. #ifdef CONFIG_MIPS_MT_SMP
  33. #define WHAT (MIPS_PERFCTRL_MT_EN_VPE | \
  34. M_PERFCTL_VPEID(cpu_vpe_id(&current_cpu_data)))
  35. #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
  36. 0 : cpu_vpe_id(&current_cpu_data))
  37. /*
  38. * The number of bits to shift to convert between counters per core and
  39. * counters per VPE. There is no reasonable interface atm to obtain the
  40. * number of VPEs used by Linux and in the 34K this number is fixed to two
  41. * anyways so we hardcore a few things here for the moment. The way it's
  42. * done here will ensure that oprofile VSMP kernel will run right on a lesser
  43. * core like a 24K also or with maxcpus=1.
  44. */
  45. static inline unsigned int vpe_shift(void)
  46. {
  47. if (num_possible_cpus() > 1)
  48. return 1;
  49. return 0;
  50. }
  51. #else
  52. #define WHAT 0
  53. #define vpe_id() 0
  54. static inline unsigned int vpe_shift(void)
  55. {
  56. return 0;
  57. }
  58. #endif
  59. static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
  60. {
  61. return counters >> vpe_shift();
  62. }
  63. static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
  64. {
  65. return counters << vpe_shift();
  66. }
  67. #define __define_perf_accessors(r, n, np) \
  68. \
  69. static inline unsigned int r_c0_ ## r ## n(void) \
  70. { \
  71. unsigned int cpu = vpe_id(); \
  72. \
  73. switch (cpu) { \
  74. case 0: \
  75. return read_c0_ ## r ## n(); \
  76. case 1: \
  77. return read_c0_ ## r ## np(); \
  78. default: \
  79. BUG(); \
  80. } \
  81. return 0; \
  82. } \
  83. \
  84. static inline void w_c0_ ## r ## n(unsigned int value) \
  85. { \
  86. unsigned int cpu = vpe_id(); \
  87. \
  88. switch (cpu) { \
  89. case 0: \
  90. write_c0_ ## r ## n(value); \
  91. return; \
  92. case 1: \
  93. write_c0_ ## r ## np(value); \
  94. return; \
  95. default: \
  96. BUG(); \
  97. } \
  98. return; \
  99. } \
  100. __define_perf_accessors(perfcntr, 0, 2)
  101. __define_perf_accessors(perfcntr, 1, 3)
  102. __define_perf_accessors(perfcntr, 2, 0)
  103. __define_perf_accessors(perfcntr, 3, 1)
  104. __define_perf_accessors(perfctrl, 0, 2)
  105. __define_perf_accessors(perfctrl, 1, 3)
  106. __define_perf_accessors(perfctrl, 2, 0)
  107. __define_perf_accessors(perfctrl, 3, 1)
  108. struct op_mips_model op_model_mipsxx_ops;
  109. static struct mipsxx_register_config {
  110. unsigned int control[4];
  111. unsigned int counter[4];
  112. } reg;
  113. /* Compute all of the registers in preparation for enabling profiling. */
  114. static void mipsxx_reg_setup(struct op_counter_config *ctr)
  115. {
  116. unsigned int counters = op_model_mipsxx_ops.num_counters;
  117. int i;
  118. /* Compute the performance counter control word. */
  119. for (i = 0; i < counters; i++) {
  120. reg.control[i] = 0;
  121. reg.counter[i] = 0;
  122. if (!ctr[i].enabled)
  123. continue;
  124. reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
  125. MIPS_PERFCTRL_IE;
  126. if (ctr[i].kernel)
  127. reg.control[i] |= MIPS_PERFCTRL_K;
  128. if (ctr[i].user)
  129. reg.control[i] |= MIPS_PERFCTRL_U;
  130. if (ctr[i].exl)
  131. reg.control[i] |= MIPS_PERFCTRL_EXL;
  132. if (boot_cpu_type() == CPU_XLR)
  133. reg.control[i] |= XLR_PERFCTRL_ALLTHREADS;
  134. reg.counter[i] = 0x80000000 - ctr[i].count;
  135. }
  136. }
  137. /* Program all of the registers in preparation for enabling profiling. */
  138. static void mipsxx_cpu_setup(void *args)
  139. {
  140. unsigned int counters = op_model_mipsxx_ops.num_counters;
  141. if (oprofile_skip_cpu(smp_processor_id()))
  142. return;
  143. switch (counters) {
  144. case 4:
  145. w_c0_perfctrl3(0);
  146. w_c0_perfcntr3(reg.counter[3]);
  147. fallthrough;
  148. case 3:
  149. w_c0_perfctrl2(0);
  150. w_c0_perfcntr2(reg.counter[2]);
  151. fallthrough;
  152. case 2:
  153. w_c0_perfctrl1(0);
  154. w_c0_perfcntr1(reg.counter[1]);
  155. fallthrough;
  156. case 1:
  157. w_c0_perfctrl0(0);
  158. w_c0_perfcntr0(reg.counter[0]);
  159. }
  160. }
  161. /* Start all counters on current CPU */
  162. static void mipsxx_cpu_start(void *args)
  163. {
  164. unsigned int counters = op_model_mipsxx_ops.num_counters;
  165. if (oprofile_skip_cpu(smp_processor_id()))
  166. return;
  167. switch (counters) {
  168. case 4:
  169. w_c0_perfctrl3(WHAT | reg.control[3]);
  170. fallthrough;
  171. case 3:
  172. w_c0_perfctrl2(WHAT | reg.control[2]);
  173. fallthrough;
  174. case 2:
  175. w_c0_perfctrl1(WHAT | reg.control[1]);
  176. fallthrough;
  177. case 1:
  178. w_c0_perfctrl0(WHAT | reg.control[0]);
  179. }
  180. }
  181. /* Stop all counters on current CPU */
  182. static void mipsxx_cpu_stop(void *args)
  183. {
  184. unsigned int counters = op_model_mipsxx_ops.num_counters;
  185. if (oprofile_skip_cpu(smp_processor_id()))
  186. return;
  187. switch (counters) {
  188. case 4:
  189. w_c0_perfctrl3(0);
  190. fallthrough;
  191. case 3:
  192. w_c0_perfctrl2(0);
  193. fallthrough;
  194. case 2:
  195. w_c0_perfctrl1(0);
  196. fallthrough;
  197. case 1:
  198. w_c0_perfctrl0(0);
  199. }
  200. }
  201. static int mipsxx_perfcount_handler(void)
  202. {
  203. unsigned int counters = op_model_mipsxx_ops.num_counters;
  204. unsigned int control;
  205. unsigned int counter;
  206. int handled = IRQ_NONE;
  207. if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
  208. return handled;
  209. switch (counters) {
  210. #define HANDLE_COUNTER(n) \
  211. case n + 1: \
  212. control = r_c0_perfctrl ## n(); \
  213. counter = r_c0_perfcntr ## n(); \
  214. if ((control & MIPS_PERFCTRL_IE) && \
  215. (counter & M_COUNTER_OVERFLOW)) { \
  216. oprofile_add_sample(get_irq_regs(), n); \
  217. w_c0_perfcntr ## n(reg.counter[n]); \
  218. handled = IRQ_HANDLED; \
  219. }
  220. HANDLE_COUNTER(3)
  221. fallthrough;
  222. HANDLE_COUNTER(2)
  223. fallthrough;
  224. HANDLE_COUNTER(1)
  225. fallthrough;
  226. HANDLE_COUNTER(0)
  227. }
  228. return handled;
  229. }
  230. static inline int __n_counters(void)
  231. {
  232. if (!cpu_has_perf)
  233. return 0;
  234. if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
  235. return 1;
  236. if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
  237. return 2;
  238. if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
  239. return 3;
  240. return 4;
  241. }
  242. static inline int n_counters(void)
  243. {
  244. int counters;
  245. switch (current_cpu_type()) {
  246. case CPU_R10000:
  247. counters = 2;
  248. break;
  249. case CPU_R12000:
  250. case CPU_R14000:
  251. case CPU_R16000:
  252. counters = 4;
  253. break;
  254. default:
  255. counters = __n_counters();
  256. }
  257. return counters;
  258. }
  259. static void reset_counters(void *arg)
  260. {
  261. int counters = (int)(long)arg;
  262. switch (counters) {
  263. case 4:
  264. w_c0_perfctrl3(0);
  265. w_c0_perfcntr3(0);
  266. fallthrough;
  267. case 3:
  268. w_c0_perfctrl2(0);
  269. w_c0_perfcntr2(0);
  270. fallthrough;
  271. case 2:
  272. w_c0_perfctrl1(0);
  273. w_c0_perfcntr1(0);
  274. fallthrough;
  275. case 1:
  276. w_c0_perfctrl0(0);
  277. w_c0_perfcntr0(0);
  278. }
  279. }
  280. static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
  281. {
  282. return mipsxx_perfcount_handler();
  283. }
  284. static int __init mipsxx_init(void)
  285. {
  286. int counters;
  287. counters = n_counters();
  288. if (counters == 0) {
  289. printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
  290. return -ENODEV;
  291. }
  292. #ifdef CONFIG_MIPS_MT_SMP
  293. if (!cpu_has_mipsmt_pertccounters)
  294. counters = counters_total_to_per_cpu(counters);
  295. #endif
  296. on_each_cpu(reset_counters, (void *)(long)counters, 1);
  297. op_model_mipsxx_ops.num_counters = counters;
  298. switch (current_cpu_type()) {
  299. case CPU_M14KC:
  300. op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
  301. break;
  302. case CPU_M14KEC:
  303. op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
  304. break;
  305. case CPU_20KC:
  306. op_model_mipsxx_ops.cpu_type = "mips/20K";
  307. break;
  308. case CPU_24K:
  309. op_model_mipsxx_ops.cpu_type = "mips/24K";
  310. break;
  311. case CPU_25KF:
  312. op_model_mipsxx_ops.cpu_type = "mips/25K";
  313. break;
  314. case CPU_1004K:
  315. case CPU_34K:
  316. op_model_mipsxx_ops.cpu_type = "mips/34K";
  317. break;
  318. case CPU_1074K:
  319. case CPU_74K:
  320. op_model_mipsxx_ops.cpu_type = "mips/74K";
  321. break;
  322. case CPU_INTERAPTIV:
  323. op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
  324. break;
  325. case CPU_PROAPTIV:
  326. op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
  327. break;
  328. case CPU_P5600:
  329. op_model_mipsxx_ops.cpu_type = "mips/P5600";
  330. break;
  331. case CPU_I6400:
  332. op_model_mipsxx_ops.cpu_type = "mips/I6400";
  333. break;
  334. case CPU_M5150:
  335. op_model_mipsxx_ops.cpu_type = "mips/M5150";
  336. break;
  337. case CPU_5KC:
  338. op_model_mipsxx_ops.cpu_type = "mips/5K";
  339. break;
  340. case CPU_R10000:
  341. if ((current_cpu_data.processor_id & 0xff) == 0x20)
  342. op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
  343. else
  344. op_model_mipsxx_ops.cpu_type = "mips/r10000";
  345. break;
  346. case CPU_R12000:
  347. case CPU_R14000:
  348. op_model_mipsxx_ops.cpu_type = "mips/r12000";
  349. break;
  350. case CPU_R16000:
  351. op_model_mipsxx_ops.cpu_type = "mips/r16000";
  352. break;
  353. case CPU_SB1:
  354. case CPU_SB1A:
  355. op_model_mipsxx_ops.cpu_type = "mips/sb1";
  356. break;
  357. case CPU_LOONGSON32:
  358. op_model_mipsxx_ops.cpu_type = "mips/loongson1";
  359. break;
  360. case CPU_XLR:
  361. op_model_mipsxx_ops.cpu_type = "mips/xlr";
  362. break;
  363. default:
  364. printk(KERN_ERR "Profiling unsupported for this CPU\n");
  365. return -ENODEV;
  366. }
  367. save_perf_irq = perf_irq;
  368. perf_irq = mipsxx_perfcount_handler;
  369. if (get_c0_perfcount_int)
  370. perfcount_irq = get_c0_perfcount_int();
  371. else if (cp0_perfcount_irq >= 0)
  372. perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
  373. else
  374. perfcount_irq = -1;
  375. if (perfcount_irq >= 0)
  376. return request_irq(perfcount_irq, mipsxx_perfcount_int,
  377. IRQF_PERCPU | IRQF_NOBALANCING |
  378. IRQF_NO_THREAD | IRQF_NO_SUSPEND |
  379. IRQF_SHARED,
  380. "Perfcounter", save_perf_irq);
  381. return 0;
  382. }
  383. static void mipsxx_exit(void)
  384. {
  385. int counters = op_model_mipsxx_ops.num_counters;
  386. if (perfcount_irq >= 0)
  387. free_irq(perfcount_irq, save_perf_irq);
  388. counters = counters_per_cpu_to_total(counters);
  389. on_each_cpu(reset_counters, (void *)(long)counters, 1);
  390. perf_irq = save_perf_irq;
  391. }
  392. struct op_mips_model op_model_mipsxx_ops = {
  393. .reg_setup = mipsxx_reg_setup,
  394. .cpu_setup = mipsxx_cpu_setup,
  395. .init = mipsxx_init,
  396. .exit = mipsxx_exit,
  397. .cpu_start = mipsxx_cpu_start,
  398. .cpu_stop = mipsxx_cpu_stop,
  399. };