op_model_loongson2.c 4.1 KB

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  1. /*
  2. * Loongson2 performance counter driver for oprofile
  3. *
  4. * Copyright (C) 2009 Lemote Inc.
  5. * Author: Yanhua <yanh@lemote.com>
  6. * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/oprofile.h>
  14. #include <linux/interrupt.h>
  15. #include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
  16. #include "op_impl.h"
  17. #define LOONGSON2_CPU_TYPE "mips/loongson2"
  18. #define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
  19. #define LOONGSON2_PERFCTRL_EXL (1UL << 0)
  20. #define LOONGSON2_PERFCTRL_KERNEL (1UL << 1)
  21. #define LOONGSON2_PERFCTRL_SUPERVISOR (1UL << 2)
  22. #define LOONGSON2_PERFCTRL_USER (1UL << 3)
  23. #define LOONGSON2_PERFCTRL_ENABLE (1UL << 4)
  24. #define LOONGSON2_PERFCTRL_EVENT(idx, event) \
  25. (((event) & 0x0f) << ((idx) ? 9 : 5))
  26. #define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
  27. #define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
  28. #define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
  29. #define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
  30. static struct loongson2_register_config {
  31. unsigned int ctrl;
  32. unsigned long long reset_counter1;
  33. unsigned long long reset_counter2;
  34. int cnt1_enabled, cnt2_enabled;
  35. } reg;
  36. static char *oprofid = "LoongsonPerf";
  37. static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
  38. static void reset_counters(void *arg)
  39. {
  40. write_c0_perfctrl(0);
  41. write_c0_perfcnt(0);
  42. }
  43. static void loongson2_reg_setup(struct op_counter_config *cfg)
  44. {
  45. unsigned int ctrl = 0;
  46. reg.reset_counter1 = 0;
  47. reg.reset_counter2 = 0;
  48. /*
  49. * Compute the performance counter ctrl word.
  50. * For now, count kernel and user mode.
  51. */
  52. if (cfg[0].enabled) {
  53. ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
  54. reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
  55. }
  56. if (cfg[1].enabled) {
  57. ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
  58. reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
  59. }
  60. if (cfg[0].enabled || cfg[1].enabled) {
  61. ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
  62. if (cfg[0].kernel || cfg[1].kernel)
  63. ctrl |= LOONGSON2_PERFCTRL_KERNEL;
  64. if (cfg[0].user || cfg[1].user)
  65. ctrl |= LOONGSON2_PERFCTRL_USER;
  66. }
  67. reg.ctrl = ctrl;
  68. reg.cnt1_enabled = cfg[0].enabled;
  69. reg.cnt2_enabled = cfg[1].enabled;
  70. }
  71. static void loongson2_cpu_setup(void *args)
  72. {
  73. write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
  74. }
  75. static void loongson2_cpu_start(void *args)
  76. {
  77. /* Start all counters on current CPU */
  78. if (reg.cnt1_enabled || reg.cnt2_enabled)
  79. write_c0_perfctrl(reg.ctrl);
  80. }
  81. static void loongson2_cpu_stop(void *args)
  82. {
  83. /* Stop all counters on current CPU */
  84. write_c0_perfctrl(0);
  85. memset(&reg, 0, sizeof(reg));
  86. }
  87. static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
  88. {
  89. uint64_t counter, counter1, counter2;
  90. struct pt_regs *regs = get_irq_regs();
  91. int enabled;
  92. /* Check whether the irq belongs to me */
  93. enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
  94. if (!enabled)
  95. return IRQ_NONE;
  96. enabled = reg.cnt1_enabled | reg.cnt2_enabled;
  97. if (!enabled)
  98. return IRQ_NONE;
  99. counter = read_c0_perfcnt();
  100. counter1 = counter & 0xffffffff;
  101. counter2 = counter >> 32;
  102. if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
  103. if (reg.cnt1_enabled)
  104. oprofile_add_sample(regs, 0);
  105. counter1 = reg.reset_counter1;
  106. }
  107. if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
  108. if (reg.cnt2_enabled)
  109. oprofile_add_sample(regs, 1);
  110. counter2 = reg.reset_counter2;
  111. }
  112. write_c0_perfcnt((counter2 << 32) | counter1);
  113. return IRQ_HANDLED;
  114. }
  115. static int __init loongson2_init(void)
  116. {
  117. return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
  118. IRQF_SHARED, "Perfcounter", oprofid);
  119. }
  120. static void loongson2_exit(void)
  121. {
  122. reset_counters(NULL);
  123. free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
  124. }
  125. struct op_mips_model op_model_loongson2_ops = {
  126. .reg_setup = loongson2_reg_setup,
  127. .cpu_setup = loongson2_cpu_setup,
  128. .init = loongson2_init,
  129. .exit = loongson2_exit,
  130. .cpu_start = loongson2_cpu_start,
  131. .cpu_stop = loongson2_cpu_stop,
  132. .cpu_type = LOONGSON2_CPU_TYPE,
  133. .num_counters = 2
  134. };