uasm-mips.c 12 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * A small micro-assembler. It is intentionally kept simple, does only
  7. * support a subset of instructions, and does not try to hide pipeline
  8. * effects like branch delay slots.
  9. *
  10. * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
  11. * Copyright (C) 2005, 2007 Maciej W. Rozycki
  12. * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
  13. * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <asm/inst.h>
  18. #include <asm/elf.h>
  19. #include <asm/bugs.h>
  20. #include <asm/uasm.h>
  21. #define RS_MASK 0x1f
  22. #define RS_SH 21
  23. #define RT_MASK 0x1f
  24. #define RT_SH 16
  25. #define SCIMM_MASK 0xfffff
  26. #define SCIMM_SH 6
  27. /* This macro sets the non-variable bits of an instruction. */
  28. #define M(a, b, c, d, e, f) \
  29. ((a) << OP_SH \
  30. | (b) << RS_SH \
  31. | (c) << RT_SH \
  32. | (d) << RD_SH \
  33. | (e) << RE_SH \
  34. | (f) << FUNC_SH)
  35. /* This macro sets the non-variable bits of an R6 instruction. */
  36. #define M6(a, b, c, d, e) \
  37. ((a) << OP_SH \
  38. | (b) << RS_SH \
  39. | (c) << RT_SH \
  40. | (d) << SIMM9_SH \
  41. | (e) << FUNC_SH)
  42. #include "uasm.c"
  43. static const struct insn insn_table[insn_invalid] = {
  44. [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  45. [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
  46. [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
  47. [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
  48. [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
  49. [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
  50. [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
  51. [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
  52. [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
  53. [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
  54. [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
  55. [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
  56. [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
  57. [insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
  58. [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
  59. [insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
  60. #ifndef CONFIG_CPU_MIPSR6
  61. [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  62. #else
  63. [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9},
  64. #endif
  65. [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
  66. [insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
  67. [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
  68. [insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
  69. [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  70. [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
  71. [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
  72. [insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
  73. RS | RT | RD},
  74. [insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
  75. [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
  76. [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
  77. [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
  78. [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
  79. [insn_divu_r6] = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
  80. RS | RT | RD},
  81. [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
  82. [insn_dmodu] = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
  83. RS | RT | RD},
  84. [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
  85. [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
  86. [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
  87. RS | RT | RD},
  88. [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
  89. [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
  90. [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
  91. [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
  92. [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
  93. [insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
  94. [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},
  95. [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
  96. [insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
  97. [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},
  98. [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
  99. [insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
  100. [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},
  101. [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
  102. [insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0},
  103. [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
  104. [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
  105. [insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM},
  106. [insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM},
  107. [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
  108. #ifndef CONFIG_CPU_MIPSR6
  109. [insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS},
  110. #else
  111. [insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS},
  112. #endif
  113. [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  114. [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  115. [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  116. [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
  117. [insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
  118. [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
  119. [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  120. [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  121. #ifndef CONFIG_CPU_MIPSR6
  122. [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  123. [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  124. #else
  125. [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9},
  126. [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9},
  127. #endif
  128. [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM},
  129. [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  130. [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  131. [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
  132. [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
  133. [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
  134. [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
  135. [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
  136. [insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
  137. RS | RT | RD},
  138. [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
  139. [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
  140. [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
  141. [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
  142. [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
  143. [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
  144. [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
  145. RS | RT | RD},
  146. #ifndef CONFIG_CPU_MIPSR6
  147. [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
  148. #else
  149. [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
  150. #endif
  151. [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
  152. [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},
  153. [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},
  154. [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
  155. #ifndef CONFIG_CPU_MIPSR6
  156. [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  157. #else
  158. [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9},
  159. #endif
  160. [insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0},
  161. [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE},
  162. [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  163. #ifndef CONFIG_CPU_MIPSR6
  164. [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  165. [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  166. #else
  167. [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9},
  168. [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},
  169. #endif
  170. [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  171. [insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
  172. [insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
  173. [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  174. [insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
  175. [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
  176. [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},
  177. [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  178. [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  179. [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
  180. [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},
  181. [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
  182. [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE},
  183. [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},
  184. [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
  185. [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
  186. [insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE},
  187. [insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
  188. [insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0},
  189. [insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0},
  190. [insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0},
  191. [insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0},
  192. [insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
  193. [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
  194. [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD},
  195. [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
  196. [insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
  197. };
  198. #undef M
  199. static inline u32 build_bimm(s32 arg)
  200. {
  201. WARN(arg > 0x1ffff || arg < -0x20000,
  202. KERN_WARNING "Micro-assembler field overflow\n");
  203. WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
  204. return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
  205. }
  206. static inline u32 build_jimm(u32 arg)
  207. {
  208. WARN(arg & ~(JIMM_MASK << 2),
  209. KERN_WARNING "Micro-assembler field overflow\n");
  210. return (arg >> 2) & JIMM_MASK;
  211. }
  212. /*
  213. * The order of opcode arguments is implicitly left to right,
  214. * starting with RS and ending with FUNC or IMM.
  215. */
  216. static void build_insn(u32 **buf, enum opcode opc, ...)
  217. {
  218. const struct insn *ip;
  219. va_list ap;
  220. u32 op;
  221. if (opc < 0 || opc >= insn_invalid ||
  222. (opc == insn_daddiu && r4k_daddiu_bug()) ||
  223. (insn_table[opc].match == 0 && insn_table[opc].fields == 0))
  224. panic("Unsupported Micro-assembler instruction %d", opc);
  225. ip = &insn_table[opc];
  226. op = ip->match;
  227. va_start(ap, opc);
  228. if (ip->fields & RS)
  229. op |= build_rs(va_arg(ap, u32));
  230. if (ip->fields & RT)
  231. op |= build_rt(va_arg(ap, u32));
  232. if (ip->fields & RD)
  233. op |= build_rd(va_arg(ap, u32));
  234. if (ip->fields & RE)
  235. op |= build_re(va_arg(ap, u32));
  236. if (ip->fields & SIMM)
  237. op |= build_simm(va_arg(ap, s32));
  238. if (ip->fields & UIMM)
  239. op |= build_uimm(va_arg(ap, u32));
  240. if (ip->fields & BIMM)
  241. op |= build_bimm(va_arg(ap, s32));
  242. if (ip->fields & JIMM)
  243. op |= build_jimm(va_arg(ap, u32));
  244. if (ip->fields & FUNC)
  245. op |= build_func(va_arg(ap, u32));
  246. if (ip->fields & SET)
  247. op |= build_set(va_arg(ap, u32));
  248. if (ip->fields & SCIMM)
  249. op |= build_scimm(va_arg(ap, u32));
  250. if (ip->fields & SIMM9)
  251. op |= build_scimm9(va_arg(ap, u32));
  252. va_end(ap);
  253. **buf = op;
  254. (*buf)++;
  255. }
  256. static inline void
  257. __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
  258. {
  259. long laddr = (long)lab->addr;
  260. long raddr = (long)rel->addr;
  261. switch (rel->type) {
  262. case R_MIPS_PC16:
  263. *rel->addr |= build_bimm(laddr - (raddr + 4));
  264. break;
  265. default:
  266. panic("Unsupported Micro-assembler relocation %d",
  267. rel->type);
  268. }
  269. }