tlbex.c 71 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Synthesize TLB refill handlers at runtime.
  7. *
  8. * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
  9. * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
  10. * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
  11. * Copyright (C) 2008, 2009 Cavium Networks, Inc.
  12. * Copyright (C) 2011 MIPS Technologies, Inc.
  13. *
  14. * ... and the days got worse and worse and now you see
  15. * I've gone completely out of my mind.
  16. *
  17. * They're coming to take me a away haha
  18. * they're coming to take me a away hoho hihi haha
  19. * to the funny farm where code is beautiful all the time ...
  20. *
  21. * (Condolences to Napoleon XIV)
  22. */
  23. #include <linux/bug.h>
  24. #include <linux/export.h>
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/smp.h>
  28. #include <linux/string.h>
  29. #include <linux/cache.h>
  30. #include <linux/pgtable.h>
  31. #include <asm/cacheflush.h>
  32. #include <asm/cpu-type.h>
  33. #include <asm/mmu_context.h>
  34. #include <asm/war.h>
  35. #include <asm/uasm.h>
  36. #include <asm/setup.h>
  37. #include <asm/tlbex.h>
  38. static int mips_xpa_disabled;
  39. static int __init xpa_disable(char *s)
  40. {
  41. mips_xpa_disabled = 1;
  42. return 1;
  43. }
  44. __setup("noxpa", xpa_disable);
  45. /*
  46. * TLB load/store/modify handlers.
  47. *
  48. * Only the fastpath gets synthesized at runtime, the slowpath for
  49. * do_page_fault remains normal asm.
  50. */
  51. extern void tlb_do_page_fault_0(void);
  52. extern void tlb_do_page_fault_1(void);
  53. struct work_registers {
  54. int r1;
  55. int r2;
  56. int r3;
  57. };
  58. struct tlb_reg_save {
  59. unsigned long a;
  60. unsigned long b;
  61. } ____cacheline_aligned_in_smp;
  62. static struct tlb_reg_save handler_reg_save[NR_CPUS];
  63. static inline int r45k_bvahwbug(void)
  64. {
  65. /* XXX: We should probe for the presence of this bug, but we don't. */
  66. return 0;
  67. }
  68. static inline int r4k_250MHZhwbug(void)
  69. {
  70. /* XXX: We should probe for the presence of this bug, but we don't. */
  71. return 0;
  72. }
  73. extern int sb1250_m3_workaround_needed(void);
  74. static inline int __maybe_unused bcm1250_m3_war(void)
  75. {
  76. if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
  77. return sb1250_m3_workaround_needed();
  78. return 0;
  79. }
  80. static inline int __maybe_unused r10000_llsc_war(void)
  81. {
  82. return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
  83. }
  84. static int use_bbit_insns(void)
  85. {
  86. switch (current_cpu_type()) {
  87. case CPU_CAVIUM_OCTEON:
  88. case CPU_CAVIUM_OCTEON_PLUS:
  89. case CPU_CAVIUM_OCTEON2:
  90. case CPU_CAVIUM_OCTEON3:
  91. return 1;
  92. default:
  93. return 0;
  94. }
  95. }
  96. static int use_lwx_insns(void)
  97. {
  98. switch (current_cpu_type()) {
  99. case CPU_CAVIUM_OCTEON2:
  100. case CPU_CAVIUM_OCTEON3:
  101. return 1;
  102. default:
  103. return 0;
  104. }
  105. }
  106. #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
  107. CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
  108. static bool scratchpad_available(void)
  109. {
  110. return true;
  111. }
  112. static int scratchpad_offset(int i)
  113. {
  114. /*
  115. * CVMSEG starts at address -32768 and extends for
  116. * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
  117. */
  118. i += 1; /* Kernel use starts at the top and works down. */
  119. return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
  120. }
  121. #else
  122. static bool scratchpad_available(void)
  123. {
  124. return false;
  125. }
  126. static int scratchpad_offset(int i)
  127. {
  128. BUG();
  129. /* Really unreachable, but evidently some GCC want this. */
  130. return 0;
  131. }
  132. #endif
  133. /*
  134. * Found by experiment: At least some revisions of the 4kc throw under
  135. * some circumstances a machine check exception, triggered by invalid
  136. * values in the index register. Delaying the tlbp instruction until
  137. * after the next branch, plus adding an additional nop in front of
  138. * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
  139. * why; it's not an issue caused by the core RTL.
  140. *
  141. */
  142. static int m4kc_tlbp_war(void)
  143. {
  144. return current_cpu_type() == CPU_4KC;
  145. }
  146. /* Handle labels (which must be positive integers). */
  147. enum label_id {
  148. label_second_part = 1,
  149. label_leave,
  150. label_vmalloc,
  151. label_vmalloc_done,
  152. label_tlbw_hazard_0,
  153. label_split = label_tlbw_hazard_0 + 8,
  154. label_tlbl_goaround1,
  155. label_tlbl_goaround2,
  156. label_nopage_tlbl,
  157. label_nopage_tlbs,
  158. label_nopage_tlbm,
  159. label_smp_pgtable_change,
  160. label_r3000_write_probe_fail,
  161. label_large_segbits_fault,
  162. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  163. label_tlb_huge_update,
  164. #endif
  165. };
  166. UASM_L_LA(_second_part)
  167. UASM_L_LA(_leave)
  168. UASM_L_LA(_vmalloc)
  169. UASM_L_LA(_vmalloc_done)
  170. /* _tlbw_hazard_x is handled differently. */
  171. UASM_L_LA(_split)
  172. UASM_L_LA(_tlbl_goaround1)
  173. UASM_L_LA(_tlbl_goaround2)
  174. UASM_L_LA(_nopage_tlbl)
  175. UASM_L_LA(_nopage_tlbs)
  176. UASM_L_LA(_nopage_tlbm)
  177. UASM_L_LA(_smp_pgtable_change)
  178. UASM_L_LA(_r3000_write_probe_fail)
  179. UASM_L_LA(_large_segbits_fault)
  180. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  181. UASM_L_LA(_tlb_huge_update)
  182. #endif
  183. static int hazard_instance;
  184. static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
  185. {
  186. switch (instance) {
  187. case 0 ... 7:
  188. uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
  189. return;
  190. default:
  191. BUG();
  192. }
  193. }
  194. static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
  195. {
  196. switch (instance) {
  197. case 0 ... 7:
  198. uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
  199. break;
  200. default:
  201. BUG();
  202. }
  203. }
  204. /*
  205. * pgtable bits are assigned dynamically depending on processor feature
  206. * and statically based on kernel configuration. This spits out the actual
  207. * values the kernel is using. Required to make sense from disassembled
  208. * TLB exception handlers.
  209. */
  210. static void output_pgtable_bits_defines(void)
  211. {
  212. #define pr_define(fmt, ...) \
  213. pr_debug("#define " fmt, ##__VA_ARGS__)
  214. pr_debug("#include <asm/asm.h>\n");
  215. pr_debug("#include <asm/regdef.h>\n");
  216. pr_debug("\n");
  217. pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
  218. pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
  219. pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
  220. pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
  221. pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
  222. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  223. pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
  224. #endif
  225. #ifdef _PAGE_NO_EXEC_SHIFT
  226. if (cpu_has_rixi)
  227. pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
  228. #endif
  229. pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
  230. pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
  231. pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
  232. pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
  233. pr_debug("\n");
  234. }
  235. static inline void dump_handler(const char *symbol, const void *start, const void *end)
  236. {
  237. unsigned int count = (end - start) / sizeof(u32);
  238. const u32 *handler = start;
  239. int i;
  240. pr_debug("LEAF(%s)\n", symbol);
  241. pr_debug("\t.set push\n");
  242. pr_debug("\t.set noreorder\n");
  243. for (i = 0; i < count; i++)
  244. pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
  245. pr_debug("\t.set\tpop\n");
  246. pr_debug("\tEND(%s)\n", symbol);
  247. }
  248. /* The only general purpose registers allowed in TLB handlers. */
  249. #define K0 26
  250. #define K1 27
  251. /* Some CP0 registers */
  252. #define C0_INDEX 0, 0
  253. #define C0_ENTRYLO0 2, 0
  254. #define C0_TCBIND 2, 2
  255. #define C0_ENTRYLO1 3, 0
  256. #define C0_CONTEXT 4, 0
  257. #define C0_PAGEMASK 5, 0
  258. #define C0_PWBASE 5, 5
  259. #define C0_PWFIELD 5, 6
  260. #define C0_PWSIZE 5, 7
  261. #define C0_PWCTL 6, 6
  262. #define C0_BADVADDR 8, 0
  263. #define C0_PGD 9, 7
  264. #define C0_ENTRYHI 10, 0
  265. #define C0_EPC 14, 0
  266. #define C0_XCONTEXT 20, 0
  267. #ifdef CONFIG_64BIT
  268. # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
  269. #else
  270. # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
  271. #endif
  272. /* The worst case length of the handler is around 18 instructions for
  273. * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
  274. * Maximum space available is 32 instructions for R3000 and 64
  275. * instructions for R4000.
  276. *
  277. * We deliberately chose a buffer size of 128, so we won't scribble
  278. * over anything important on overflow before we panic.
  279. */
  280. static u32 tlb_handler[128];
  281. /* simply assume worst case size for labels and relocs */
  282. static struct uasm_label labels[128];
  283. static struct uasm_reloc relocs[128];
  284. static int check_for_high_segbits;
  285. static bool fill_includes_sw_bits;
  286. static unsigned int kscratch_used_mask;
  287. static inline int __maybe_unused c0_kscratch(void)
  288. {
  289. switch (current_cpu_type()) {
  290. case CPU_XLP:
  291. case CPU_XLR:
  292. return 22;
  293. default:
  294. return 31;
  295. }
  296. }
  297. static int allocate_kscratch(void)
  298. {
  299. int r;
  300. unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
  301. r = ffs(a);
  302. if (r == 0)
  303. return -1;
  304. r--; /* make it zero based */
  305. kscratch_used_mask |= (1 << r);
  306. return r;
  307. }
  308. static int scratch_reg;
  309. int pgd_reg;
  310. EXPORT_SYMBOL_GPL(pgd_reg);
  311. enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
  312. static struct work_registers build_get_work_registers(u32 **p)
  313. {
  314. struct work_registers r;
  315. if (scratch_reg >= 0) {
  316. /* Save in CPU local C0_KScratch? */
  317. UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
  318. r.r1 = K0;
  319. r.r2 = K1;
  320. r.r3 = 1;
  321. return r;
  322. }
  323. if (num_possible_cpus() > 1) {
  324. /* Get smp_processor_id */
  325. UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
  326. UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
  327. /* handler_reg_save index in K0 */
  328. UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
  329. UASM_i_LA(p, K1, (long)&handler_reg_save);
  330. UASM_i_ADDU(p, K0, K0, K1);
  331. } else {
  332. UASM_i_LA(p, K0, (long)&handler_reg_save);
  333. }
  334. /* K0 now points to save area, save $1 and $2 */
  335. UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
  336. UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
  337. r.r1 = K1;
  338. r.r2 = 1;
  339. r.r3 = 2;
  340. return r;
  341. }
  342. static void build_restore_work_registers(u32 **p)
  343. {
  344. if (scratch_reg >= 0) {
  345. uasm_i_ehb(p);
  346. UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
  347. return;
  348. }
  349. /* K0 already points to save area, restore $1 and $2 */
  350. UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
  351. UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
  352. }
  353. #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  354. /*
  355. * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
  356. * we cannot do r3000 under these circumstances.
  357. *
  358. * The R3000 TLB handler is simple.
  359. */
  360. static void build_r3000_tlb_refill_handler(void)
  361. {
  362. long pgdc = (long)pgd_current;
  363. u32 *p;
  364. memset(tlb_handler, 0, sizeof(tlb_handler));
  365. p = tlb_handler;
  366. uasm_i_mfc0(&p, K0, C0_BADVADDR);
  367. uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
  368. uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
  369. uasm_i_srl(&p, K0, K0, 22); /* load delay */
  370. uasm_i_sll(&p, K0, K0, 2);
  371. uasm_i_addu(&p, K1, K1, K0);
  372. uasm_i_mfc0(&p, K0, C0_CONTEXT);
  373. uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
  374. uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
  375. uasm_i_addu(&p, K1, K1, K0);
  376. uasm_i_lw(&p, K0, 0, K1);
  377. uasm_i_nop(&p); /* load delay */
  378. uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
  379. uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
  380. uasm_i_tlbwr(&p); /* cp0 delay */
  381. uasm_i_jr(&p, K1);
  382. uasm_i_rfe(&p); /* branch delay */
  383. if (p > tlb_handler + 32)
  384. panic("TLB refill handler space exceeded");
  385. pr_debug("Wrote TLB refill handler (%u instructions).\n",
  386. (unsigned int)(p - tlb_handler));
  387. memcpy((void *)ebase, tlb_handler, 0x80);
  388. local_flush_icache_range(ebase, ebase + 0x80);
  389. dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80));
  390. }
  391. #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
  392. /*
  393. * The R4000 TLB handler is much more complicated. We have two
  394. * consecutive handler areas with 32 instructions space each.
  395. * Since they aren't used at the same time, we can overflow in the
  396. * other one.To keep things simple, we first assume linear space,
  397. * then we relocate it to the final handler layout as needed.
  398. */
  399. static u32 final_handler[64];
  400. /*
  401. * Hazards
  402. *
  403. * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
  404. * 2. A timing hazard exists for the TLBP instruction.
  405. *
  406. * stalling_instruction
  407. * TLBP
  408. *
  409. * The JTLB is being read for the TLBP throughout the stall generated by the
  410. * previous instruction. This is not really correct as the stalling instruction
  411. * can modify the address used to access the JTLB. The failure symptom is that
  412. * the TLBP instruction will use an address created for the stalling instruction
  413. * and not the address held in C0_ENHI and thus report the wrong results.
  414. *
  415. * The software work-around is to not allow the instruction preceding the TLBP
  416. * to stall - make it an NOP or some other instruction guaranteed not to stall.
  417. *
  418. * Errata 2 will not be fixed. This errata is also on the R5000.
  419. *
  420. * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
  421. */
  422. static void __maybe_unused build_tlb_probe_entry(u32 **p)
  423. {
  424. switch (current_cpu_type()) {
  425. /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
  426. case CPU_R4600:
  427. case CPU_R4700:
  428. case CPU_R5000:
  429. case CPU_NEVADA:
  430. uasm_i_nop(p);
  431. uasm_i_tlbp(p);
  432. break;
  433. default:
  434. uasm_i_tlbp(p);
  435. break;
  436. }
  437. }
  438. void build_tlb_write_entry(u32 **p, struct uasm_label **l,
  439. struct uasm_reloc **r,
  440. enum tlb_write_entry wmode)
  441. {
  442. void(*tlbw)(u32 **) = NULL;
  443. switch (wmode) {
  444. case tlb_random: tlbw = uasm_i_tlbwr; break;
  445. case tlb_indexed: tlbw = uasm_i_tlbwi; break;
  446. }
  447. if (cpu_has_mips_r2_r6) {
  448. if (cpu_has_mips_r2_exec_hazard)
  449. uasm_i_ehb(p);
  450. tlbw(p);
  451. return;
  452. }
  453. switch (current_cpu_type()) {
  454. case CPU_R4000PC:
  455. case CPU_R4000SC:
  456. case CPU_R4000MC:
  457. case CPU_R4400PC:
  458. case CPU_R4400SC:
  459. case CPU_R4400MC:
  460. /*
  461. * This branch uses up a mtc0 hazard nop slot and saves
  462. * two nops after the tlbw instruction.
  463. */
  464. uasm_bgezl_hazard(p, r, hazard_instance);
  465. tlbw(p);
  466. uasm_bgezl_label(l, p, hazard_instance);
  467. hazard_instance++;
  468. uasm_i_nop(p);
  469. break;
  470. case CPU_R4600:
  471. case CPU_R4700:
  472. uasm_i_nop(p);
  473. tlbw(p);
  474. uasm_i_nop(p);
  475. break;
  476. case CPU_R5000:
  477. case CPU_NEVADA:
  478. uasm_i_nop(p); /* QED specifies 2 nops hazard */
  479. uasm_i_nop(p); /* QED specifies 2 nops hazard */
  480. tlbw(p);
  481. break;
  482. case CPU_5KC:
  483. case CPU_TX49XX:
  484. case CPU_PR4450:
  485. case CPU_XLR:
  486. uasm_i_nop(p);
  487. tlbw(p);
  488. break;
  489. case CPU_R10000:
  490. case CPU_R12000:
  491. case CPU_R14000:
  492. case CPU_R16000:
  493. case CPU_4KC:
  494. case CPU_4KEC:
  495. case CPU_M14KC:
  496. case CPU_M14KEC:
  497. case CPU_SB1:
  498. case CPU_SB1A:
  499. case CPU_4KSC:
  500. case CPU_20KC:
  501. case CPU_25KF:
  502. case CPU_BMIPS32:
  503. case CPU_BMIPS3300:
  504. case CPU_BMIPS4350:
  505. case CPU_BMIPS4380:
  506. case CPU_BMIPS5000:
  507. case CPU_LOONGSON2EF:
  508. case CPU_LOONGSON64:
  509. case CPU_R5500:
  510. if (m4kc_tlbp_war())
  511. uasm_i_nop(p);
  512. fallthrough;
  513. case CPU_ALCHEMY:
  514. tlbw(p);
  515. break;
  516. case CPU_RM7000:
  517. uasm_i_nop(p);
  518. uasm_i_nop(p);
  519. uasm_i_nop(p);
  520. uasm_i_nop(p);
  521. tlbw(p);
  522. break;
  523. case CPU_VR4111:
  524. case CPU_VR4121:
  525. case CPU_VR4122:
  526. case CPU_VR4181:
  527. case CPU_VR4181A:
  528. uasm_i_nop(p);
  529. uasm_i_nop(p);
  530. tlbw(p);
  531. uasm_i_nop(p);
  532. uasm_i_nop(p);
  533. break;
  534. case CPU_VR4131:
  535. case CPU_VR4133:
  536. uasm_i_nop(p);
  537. uasm_i_nop(p);
  538. tlbw(p);
  539. break;
  540. case CPU_XBURST:
  541. tlbw(p);
  542. uasm_i_nop(p);
  543. break;
  544. default:
  545. panic("No TLB refill handler yet (CPU type: %d)",
  546. current_cpu_type());
  547. break;
  548. }
  549. }
  550. EXPORT_SYMBOL_GPL(build_tlb_write_entry);
  551. static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
  552. unsigned int reg)
  553. {
  554. if (_PAGE_GLOBAL_SHIFT == 0) {
  555. /* pte_t is already in EntryLo format */
  556. return;
  557. }
  558. if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
  559. if (fill_includes_sw_bits) {
  560. UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
  561. } else {
  562. UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
  563. UASM_i_ROTR(p, reg, reg,
  564. ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
  565. }
  566. } else {
  567. #ifdef CONFIG_PHYS_ADDR_T_64BIT
  568. uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
  569. #else
  570. UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
  571. #endif
  572. }
  573. }
  574. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  575. static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
  576. unsigned int tmp, enum label_id lid,
  577. int restore_scratch)
  578. {
  579. if (restore_scratch) {
  580. /*
  581. * Ensure the MFC0 below observes the value written to the
  582. * KScratch register by the prior MTC0.
  583. */
  584. if (scratch_reg >= 0)
  585. uasm_i_ehb(p);
  586. /* Reset default page size */
  587. if (PM_DEFAULT_MASK >> 16) {
  588. uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
  589. uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
  590. uasm_i_mtc0(p, tmp, C0_PAGEMASK);
  591. uasm_il_b(p, r, lid);
  592. } else if (PM_DEFAULT_MASK) {
  593. uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
  594. uasm_i_mtc0(p, tmp, C0_PAGEMASK);
  595. uasm_il_b(p, r, lid);
  596. } else {
  597. uasm_i_mtc0(p, 0, C0_PAGEMASK);
  598. uasm_il_b(p, r, lid);
  599. }
  600. if (scratch_reg >= 0)
  601. UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
  602. else
  603. UASM_i_LW(p, 1, scratchpad_offset(0), 0);
  604. } else {
  605. /* Reset default page size */
  606. if (PM_DEFAULT_MASK >> 16) {
  607. uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
  608. uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
  609. uasm_il_b(p, r, lid);
  610. uasm_i_mtc0(p, tmp, C0_PAGEMASK);
  611. } else if (PM_DEFAULT_MASK) {
  612. uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
  613. uasm_il_b(p, r, lid);
  614. uasm_i_mtc0(p, tmp, C0_PAGEMASK);
  615. } else {
  616. uasm_il_b(p, r, lid);
  617. uasm_i_mtc0(p, 0, C0_PAGEMASK);
  618. }
  619. }
  620. }
  621. static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
  622. struct uasm_reloc **r,
  623. unsigned int tmp,
  624. enum tlb_write_entry wmode,
  625. int restore_scratch)
  626. {
  627. /* Set huge page tlb entry size */
  628. uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
  629. uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
  630. uasm_i_mtc0(p, tmp, C0_PAGEMASK);
  631. build_tlb_write_entry(p, l, r, wmode);
  632. build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
  633. }
  634. /*
  635. * Check if Huge PTE is present, if so then jump to LABEL.
  636. */
  637. static void
  638. build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
  639. unsigned int pmd, int lid)
  640. {
  641. UASM_i_LW(p, tmp, 0, pmd);
  642. if (use_bbit_insns()) {
  643. uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
  644. } else {
  645. uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
  646. uasm_il_bnez(p, r, tmp, lid);
  647. }
  648. }
  649. static void build_huge_update_entries(u32 **p, unsigned int pte,
  650. unsigned int tmp)
  651. {
  652. int small_sequence;
  653. /*
  654. * A huge PTE describes an area the size of the
  655. * configured huge page size. This is twice the
  656. * of the large TLB entry size we intend to use.
  657. * A TLB entry half the size of the configured
  658. * huge page size is configured into entrylo0
  659. * and entrylo1 to cover the contiguous huge PTE
  660. * address space.
  661. */
  662. small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
  663. /* We can clobber tmp. It isn't used after this.*/
  664. if (!small_sequence)
  665. uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
  666. build_convert_pte_to_entrylo(p, pte);
  667. UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
  668. /* convert to entrylo1 */
  669. if (small_sequence)
  670. UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
  671. else
  672. UASM_i_ADDU(p, pte, pte, tmp);
  673. UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
  674. }
  675. static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
  676. struct uasm_label **l,
  677. unsigned int pte,
  678. unsigned int ptr,
  679. unsigned int flush)
  680. {
  681. #ifdef CONFIG_SMP
  682. UASM_i_SC(p, pte, 0, ptr);
  683. uasm_il_beqz(p, r, pte, label_tlb_huge_update);
  684. UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
  685. #else
  686. UASM_i_SW(p, pte, 0, ptr);
  687. #endif
  688. if (cpu_has_ftlb && flush) {
  689. BUG_ON(!cpu_has_tlbinv);
  690. UASM_i_MFC0(p, ptr, C0_ENTRYHI);
  691. uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
  692. UASM_i_MTC0(p, ptr, C0_ENTRYHI);
  693. build_tlb_write_entry(p, l, r, tlb_indexed);
  694. uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
  695. UASM_i_MTC0(p, ptr, C0_ENTRYHI);
  696. build_huge_update_entries(p, pte, ptr);
  697. build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
  698. return;
  699. }
  700. build_huge_update_entries(p, pte, ptr);
  701. build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
  702. }
  703. #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
  704. #ifdef CONFIG_64BIT
  705. /*
  706. * TMP and PTR are scratch.
  707. * TMP will be clobbered, PTR will hold the pmd entry.
  708. */
  709. void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
  710. unsigned int tmp, unsigned int ptr)
  711. {
  712. #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  713. long pgdc = (long)pgd_current;
  714. #endif
  715. /*
  716. * The vmalloc handling is not in the hotpath.
  717. */
  718. uasm_i_dmfc0(p, tmp, C0_BADVADDR);
  719. if (check_for_high_segbits) {
  720. /*
  721. * The kernel currently implicitely assumes that the
  722. * MIPS SEGBITS parameter for the processor is
  723. * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
  724. * allocate virtual addresses outside the maximum
  725. * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
  726. * that doesn't prevent user code from accessing the
  727. * higher xuseg addresses. Here, we make sure that
  728. * everything but the lower xuseg addresses goes down
  729. * the module_alloc/vmalloc path.
  730. */
  731. uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
  732. uasm_il_bnez(p, r, ptr, label_vmalloc);
  733. } else {
  734. uasm_il_bltz(p, r, tmp, label_vmalloc);
  735. }
  736. /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
  737. if (pgd_reg != -1) {
  738. /* pgd is in pgd_reg */
  739. if (cpu_has_ldpte)
  740. UASM_i_MFC0(p, ptr, C0_PWBASE);
  741. else
  742. UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
  743. } else {
  744. #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
  745. /*
  746. * &pgd << 11 stored in CONTEXT [23..63].
  747. */
  748. UASM_i_MFC0(p, ptr, C0_CONTEXT);
  749. /* Clear lower 23 bits of context. */
  750. uasm_i_dins(p, ptr, 0, 0, 23);
  751. /* 1 0 1 0 1 << 6 xkphys cached */
  752. uasm_i_ori(p, ptr, ptr, 0x540);
  753. uasm_i_drotr(p, ptr, ptr, 11);
  754. #elif defined(CONFIG_SMP)
  755. UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
  756. uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
  757. UASM_i_LA_mostly(p, tmp, pgdc);
  758. uasm_i_daddu(p, ptr, ptr, tmp);
  759. uasm_i_dmfc0(p, tmp, C0_BADVADDR);
  760. uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
  761. #else
  762. UASM_i_LA_mostly(p, ptr, pgdc);
  763. uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
  764. #endif
  765. }
  766. uasm_l_vmalloc_done(l, *p);
  767. /* get pgd offset in bytes */
  768. uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
  769. uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
  770. uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
  771. #ifndef __PAGETABLE_PUD_FOLDED
  772. uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
  773. uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
  774. uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
  775. uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
  776. uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
  777. #endif
  778. #ifndef __PAGETABLE_PMD_FOLDED
  779. uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
  780. uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
  781. uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
  782. uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
  783. uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
  784. #endif
  785. }
  786. EXPORT_SYMBOL_GPL(build_get_pmde64);
  787. /*
  788. * BVADDR is the faulting address, PTR is scratch.
  789. * PTR will hold the pgd for vmalloc.
  790. */
  791. static void
  792. build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
  793. unsigned int bvaddr, unsigned int ptr,
  794. enum vmalloc64_mode mode)
  795. {
  796. long swpd = (long)swapper_pg_dir;
  797. int single_insn_swpd;
  798. int did_vmalloc_branch = 0;
  799. single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
  800. uasm_l_vmalloc(l, *p);
  801. if (mode != not_refill && check_for_high_segbits) {
  802. if (single_insn_swpd) {
  803. uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
  804. uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
  805. did_vmalloc_branch = 1;
  806. /* fall through */
  807. } else {
  808. uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
  809. }
  810. }
  811. if (!did_vmalloc_branch) {
  812. if (single_insn_swpd) {
  813. uasm_il_b(p, r, label_vmalloc_done);
  814. uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
  815. } else {
  816. UASM_i_LA_mostly(p, ptr, swpd);
  817. uasm_il_b(p, r, label_vmalloc_done);
  818. if (uasm_in_compat_space_p(swpd))
  819. uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
  820. else
  821. uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
  822. }
  823. }
  824. if (mode != not_refill && check_for_high_segbits) {
  825. uasm_l_large_segbits_fault(l, *p);
  826. if (mode == refill_scratch && scratch_reg >= 0)
  827. uasm_i_ehb(p);
  828. /*
  829. * We get here if we are an xsseg address, or if we are
  830. * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
  831. *
  832. * Ignoring xsseg (assume disabled so would generate
  833. * (address errors?), the only remaining possibility
  834. * is the upper xuseg addresses. On processors with
  835. * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
  836. * addresses would have taken an address error. We try
  837. * to mimic that here by taking a load/istream page
  838. * fault.
  839. */
  840. if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
  841. uasm_i_sync(p, 0);
  842. UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
  843. uasm_i_jr(p, ptr);
  844. if (mode == refill_scratch) {
  845. if (scratch_reg >= 0)
  846. UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
  847. else
  848. UASM_i_LW(p, 1, scratchpad_offset(0), 0);
  849. } else {
  850. uasm_i_nop(p);
  851. }
  852. }
  853. }
  854. #else /* !CONFIG_64BIT */
  855. /*
  856. * TMP and PTR are scratch.
  857. * TMP will be clobbered, PTR will hold the pgd entry.
  858. */
  859. void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
  860. {
  861. if (pgd_reg != -1) {
  862. /* pgd is in pgd_reg */
  863. uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
  864. uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
  865. } else {
  866. long pgdc = (long)pgd_current;
  867. /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
  868. #ifdef CONFIG_SMP
  869. uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
  870. UASM_i_LA_mostly(p, tmp, pgdc);
  871. uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
  872. uasm_i_addu(p, ptr, tmp, ptr);
  873. #else
  874. UASM_i_LA_mostly(p, ptr, pgdc);
  875. #endif
  876. uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
  877. uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
  878. }
  879. uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
  880. uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
  881. uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
  882. }
  883. EXPORT_SYMBOL_GPL(build_get_pgde32);
  884. #endif /* !CONFIG_64BIT */
  885. static void build_adjust_context(u32 **p, unsigned int ctx)
  886. {
  887. unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
  888. unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
  889. switch (current_cpu_type()) {
  890. case CPU_VR41XX:
  891. case CPU_VR4111:
  892. case CPU_VR4121:
  893. case CPU_VR4122:
  894. case CPU_VR4131:
  895. case CPU_VR4181:
  896. case CPU_VR4181A:
  897. case CPU_VR4133:
  898. shift += 2;
  899. break;
  900. default:
  901. break;
  902. }
  903. if (shift)
  904. UASM_i_SRL(p, ctx, ctx, shift);
  905. uasm_i_andi(p, ctx, ctx, mask);
  906. }
  907. void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
  908. {
  909. /*
  910. * Bug workaround for the Nevada. It seems as if under certain
  911. * circumstances the move from cp0_context might produce a
  912. * bogus result when the mfc0 instruction and its consumer are
  913. * in a different cacheline or a load instruction, probably any
  914. * memory reference, is between them.
  915. */
  916. switch (current_cpu_type()) {
  917. case CPU_NEVADA:
  918. UASM_i_LW(p, ptr, 0, ptr);
  919. GET_CONTEXT(p, tmp); /* get context reg */
  920. break;
  921. default:
  922. GET_CONTEXT(p, tmp); /* get context reg */
  923. UASM_i_LW(p, ptr, 0, ptr);
  924. break;
  925. }
  926. build_adjust_context(p, tmp);
  927. UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
  928. }
  929. EXPORT_SYMBOL_GPL(build_get_ptep);
  930. void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
  931. {
  932. int pte_off_even = 0;
  933. int pte_off_odd = sizeof(pte_t);
  934. #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
  935. /* The low 32 bits of EntryLo is stored in pte_high */
  936. pte_off_even += offsetof(pte_t, pte_high);
  937. pte_off_odd += offsetof(pte_t, pte_high);
  938. #endif
  939. if (IS_ENABLED(CONFIG_XPA)) {
  940. uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
  941. UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
  942. UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
  943. if (cpu_has_xpa && !mips_xpa_disabled) {
  944. uasm_i_lw(p, tmp, 0, ptep);
  945. uasm_i_ext(p, tmp, tmp, 0, 24);
  946. uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
  947. }
  948. uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
  949. UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
  950. UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
  951. if (cpu_has_xpa && !mips_xpa_disabled) {
  952. uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
  953. uasm_i_ext(p, tmp, tmp, 0, 24);
  954. uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
  955. }
  956. return;
  957. }
  958. UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
  959. UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
  960. if (r45k_bvahwbug())
  961. build_tlb_probe_entry(p);
  962. build_convert_pte_to_entrylo(p, tmp);
  963. if (r4k_250MHZhwbug())
  964. UASM_i_MTC0(p, 0, C0_ENTRYLO0);
  965. UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
  966. build_convert_pte_to_entrylo(p, ptep);
  967. if (r45k_bvahwbug())
  968. uasm_i_mfc0(p, tmp, C0_INDEX);
  969. if (r4k_250MHZhwbug())
  970. UASM_i_MTC0(p, 0, C0_ENTRYLO1);
  971. UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
  972. }
  973. EXPORT_SYMBOL_GPL(build_update_entries);
  974. struct mips_huge_tlb_info {
  975. int huge_pte;
  976. int restore_scratch;
  977. bool need_reload_pte;
  978. };
  979. static struct mips_huge_tlb_info
  980. build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
  981. struct uasm_reloc **r, unsigned int tmp,
  982. unsigned int ptr, int c0_scratch_reg)
  983. {
  984. struct mips_huge_tlb_info rv;
  985. unsigned int even, odd;
  986. int vmalloc_branch_delay_filled = 0;
  987. const int scratch = 1; /* Our extra working register */
  988. rv.huge_pte = scratch;
  989. rv.restore_scratch = 0;
  990. rv.need_reload_pte = false;
  991. if (check_for_high_segbits) {
  992. UASM_i_MFC0(p, tmp, C0_BADVADDR);
  993. if (pgd_reg != -1)
  994. UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
  995. else
  996. UASM_i_MFC0(p, ptr, C0_CONTEXT);
  997. if (c0_scratch_reg >= 0)
  998. UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
  999. else
  1000. UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
  1001. uasm_i_dsrl_safe(p, scratch, tmp,
  1002. PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
  1003. uasm_il_bnez(p, r, scratch, label_vmalloc);
  1004. if (pgd_reg == -1) {
  1005. vmalloc_branch_delay_filled = 1;
  1006. /* Clear lower 23 bits of context. */
  1007. uasm_i_dins(p, ptr, 0, 0, 23);
  1008. }
  1009. } else {
  1010. if (pgd_reg != -1)
  1011. UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
  1012. else
  1013. UASM_i_MFC0(p, ptr, C0_CONTEXT);
  1014. UASM_i_MFC0(p, tmp, C0_BADVADDR);
  1015. if (c0_scratch_reg >= 0)
  1016. UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
  1017. else
  1018. UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
  1019. if (pgd_reg == -1)
  1020. /* Clear lower 23 bits of context. */
  1021. uasm_i_dins(p, ptr, 0, 0, 23);
  1022. uasm_il_bltz(p, r, tmp, label_vmalloc);
  1023. }
  1024. if (pgd_reg == -1) {
  1025. vmalloc_branch_delay_filled = 1;
  1026. /* 1 0 1 0 1 << 6 xkphys cached */
  1027. uasm_i_ori(p, ptr, ptr, 0x540);
  1028. uasm_i_drotr(p, ptr, ptr, 11);
  1029. }
  1030. #ifdef __PAGETABLE_PMD_FOLDED
  1031. #define LOC_PTEP scratch
  1032. #else
  1033. #define LOC_PTEP ptr
  1034. #endif
  1035. if (!vmalloc_branch_delay_filled)
  1036. /* get pgd offset in bytes */
  1037. uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
  1038. uasm_l_vmalloc_done(l, *p);
  1039. /*
  1040. * tmp ptr
  1041. * fall-through case = badvaddr *pgd_current
  1042. * vmalloc case = badvaddr swapper_pg_dir
  1043. */
  1044. if (vmalloc_branch_delay_filled)
  1045. /* get pgd offset in bytes */
  1046. uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
  1047. #ifdef __PAGETABLE_PMD_FOLDED
  1048. GET_CONTEXT(p, tmp); /* get context reg */
  1049. #endif
  1050. uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
  1051. if (use_lwx_insns()) {
  1052. UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
  1053. } else {
  1054. uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
  1055. uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
  1056. }
  1057. #ifndef __PAGETABLE_PUD_FOLDED
  1058. /* get pud offset in bytes */
  1059. uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
  1060. uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
  1061. if (use_lwx_insns()) {
  1062. UASM_i_LWX(p, ptr, scratch, ptr);
  1063. } else {
  1064. uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
  1065. UASM_i_LW(p, ptr, 0, ptr);
  1066. }
  1067. /* ptr contains a pointer to PMD entry */
  1068. /* tmp contains the address */
  1069. #endif
  1070. #ifndef __PAGETABLE_PMD_FOLDED
  1071. /* get pmd offset in bytes */
  1072. uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
  1073. uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
  1074. GET_CONTEXT(p, tmp); /* get context reg */
  1075. if (use_lwx_insns()) {
  1076. UASM_i_LWX(p, scratch, scratch, ptr);
  1077. } else {
  1078. uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
  1079. UASM_i_LW(p, scratch, 0, ptr);
  1080. }
  1081. #endif
  1082. /* Adjust the context during the load latency. */
  1083. build_adjust_context(p, tmp);
  1084. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1085. uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
  1086. /*
  1087. * The in the LWX case we don't want to do the load in the
  1088. * delay slot. It cannot issue in the same cycle and may be
  1089. * speculative and unneeded.
  1090. */
  1091. if (use_lwx_insns())
  1092. uasm_i_nop(p);
  1093. #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
  1094. /* build_update_entries */
  1095. if (use_lwx_insns()) {
  1096. even = ptr;
  1097. odd = tmp;
  1098. UASM_i_LWX(p, even, scratch, tmp);
  1099. UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
  1100. UASM_i_LWX(p, odd, scratch, tmp);
  1101. } else {
  1102. UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
  1103. even = tmp;
  1104. odd = ptr;
  1105. UASM_i_LW(p, even, 0, ptr); /* get even pte */
  1106. UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
  1107. }
  1108. if (cpu_has_rixi) {
  1109. uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
  1110. UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
  1111. uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
  1112. } else {
  1113. uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
  1114. UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
  1115. uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
  1116. }
  1117. UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
  1118. if (c0_scratch_reg >= 0) {
  1119. uasm_i_ehb(p);
  1120. UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
  1121. build_tlb_write_entry(p, l, r, tlb_random);
  1122. uasm_l_leave(l, *p);
  1123. rv.restore_scratch = 1;
  1124. } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
  1125. build_tlb_write_entry(p, l, r, tlb_random);
  1126. uasm_l_leave(l, *p);
  1127. UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
  1128. } else {
  1129. UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
  1130. build_tlb_write_entry(p, l, r, tlb_random);
  1131. uasm_l_leave(l, *p);
  1132. rv.restore_scratch = 1;
  1133. }
  1134. uasm_i_eret(p); /* return from trap */
  1135. return rv;
  1136. }
  1137. /*
  1138. * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
  1139. * because EXL == 0. If we wrap, we can also use the 32 instruction
  1140. * slots before the XTLB refill exception handler which belong to the
  1141. * unused TLB refill exception.
  1142. */
  1143. #define MIPS64_REFILL_INSNS 32
  1144. static void build_r4000_tlb_refill_handler(void)
  1145. {
  1146. u32 *p = tlb_handler;
  1147. struct uasm_label *l = labels;
  1148. struct uasm_reloc *r = relocs;
  1149. u32 *f;
  1150. unsigned int final_len;
  1151. struct mips_huge_tlb_info htlb_info __maybe_unused;
  1152. enum vmalloc64_mode vmalloc_mode __maybe_unused;
  1153. memset(tlb_handler, 0, sizeof(tlb_handler));
  1154. memset(labels, 0, sizeof(labels));
  1155. memset(relocs, 0, sizeof(relocs));
  1156. memset(final_handler, 0, sizeof(final_handler));
  1157. if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
  1158. htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
  1159. scratch_reg);
  1160. vmalloc_mode = refill_scratch;
  1161. } else {
  1162. htlb_info.huge_pte = K0;
  1163. htlb_info.restore_scratch = 0;
  1164. htlb_info.need_reload_pte = true;
  1165. vmalloc_mode = refill_noscratch;
  1166. /*
  1167. * create the plain linear handler
  1168. */
  1169. if (bcm1250_m3_war()) {
  1170. unsigned int segbits = 44;
  1171. uasm_i_dmfc0(&p, K0, C0_BADVADDR);
  1172. uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
  1173. uasm_i_xor(&p, K0, K0, K1);
  1174. uasm_i_dsrl_safe(&p, K1, K0, 62);
  1175. uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
  1176. uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
  1177. uasm_i_or(&p, K0, K0, K1);
  1178. uasm_il_bnez(&p, &r, K0, label_leave);
  1179. /* No need for uasm_i_nop */
  1180. }
  1181. #ifdef CONFIG_64BIT
  1182. build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
  1183. #else
  1184. build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
  1185. #endif
  1186. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1187. build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
  1188. #endif
  1189. build_get_ptep(&p, K0, K1);
  1190. build_update_entries(&p, K0, K1);
  1191. build_tlb_write_entry(&p, &l, &r, tlb_random);
  1192. uasm_l_leave(&l, p);
  1193. uasm_i_eret(&p); /* return from trap */
  1194. }
  1195. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1196. uasm_l_tlb_huge_update(&l, p);
  1197. if (htlb_info.need_reload_pte)
  1198. UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
  1199. build_huge_update_entries(&p, htlb_info.huge_pte, K1);
  1200. build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
  1201. htlb_info.restore_scratch);
  1202. #endif
  1203. #ifdef CONFIG_64BIT
  1204. build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
  1205. #endif
  1206. /*
  1207. * Overflow check: For the 64bit handler, we need at least one
  1208. * free instruction slot for the wrap-around branch. In worst
  1209. * case, if the intended insertion point is a delay slot, we
  1210. * need three, with the second nop'ed and the third being
  1211. * unused.
  1212. */
  1213. switch (boot_cpu_type()) {
  1214. default:
  1215. if (sizeof(long) == 4) {
  1216. case CPU_LOONGSON2EF:
  1217. /* Loongson2 ebase is different than r4k, we have more space */
  1218. if ((p - tlb_handler) > 64)
  1219. panic("TLB refill handler space exceeded");
  1220. /*
  1221. * Now fold the handler in the TLB refill handler space.
  1222. */
  1223. f = final_handler;
  1224. /* Simplest case, just copy the handler. */
  1225. uasm_copy_handler(relocs, labels, tlb_handler, p, f);
  1226. final_len = p - tlb_handler;
  1227. break;
  1228. } else {
  1229. if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
  1230. || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
  1231. && uasm_insn_has_bdelay(relocs,
  1232. tlb_handler + MIPS64_REFILL_INSNS - 3)))
  1233. panic("TLB refill handler space exceeded");
  1234. /*
  1235. * Now fold the handler in the TLB refill handler space.
  1236. */
  1237. f = final_handler + MIPS64_REFILL_INSNS;
  1238. if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
  1239. /* Just copy the handler. */
  1240. uasm_copy_handler(relocs, labels, tlb_handler, p, f);
  1241. final_len = p - tlb_handler;
  1242. } else {
  1243. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1244. const enum label_id ls = label_tlb_huge_update;
  1245. #else
  1246. const enum label_id ls = label_vmalloc;
  1247. #endif
  1248. u32 *split;
  1249. int ov = 0;
  1250. int i;
  1251. for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
  1252. ;
  1253. BUG_ON(i == ARRAY_SIZE(labels));
  1254. split = labels[i].addr;
  1255. /*
  1256. * See if we have overflown one way or the other.
  1257. */
  1258. if (split > tlb_handler + MIPS64_REFILL_INSNS ||
  1259. split < p - MIPS64_REFILL_INSNS)
  1260. ov = 1;
  1261. if (ov) {
  1262. /*
  1263. * Split two instructions before the end. One
  1264. * for the branch and one for the instruction
  1265. * in the delay slot.
  1266. */
  1267. split = tlb_handler + MIPS64_REFILL_INSNS - 2;
  1268. /*
  1269. * If the branch would fall in a delay slot,
  1270. * we must back up an additional instruction
  1271. * so that it is no longer in a delay slot.
  1272. */
  1273. if (uasm_insn_has_bdelay(relocs, split - 1))
  1274. split--;
  1275. }
  1276. /* Copy first part of the handler. */
  1277. uasm_copy_handler(relocs, labels, tlb_handler, split, f);
  1278. f += split - tlb_handler;
  1279. if (ov) {
  1280. /* Insert branch. */
  1281. uasm_l_split(&l, final_handler);
  1282. uasm_il_b(&f, &r, label_split);
  1283. if (uasm_insn_has_bdelay(relocs, split))
  1284. uasm_i_nop(&f);
  1285. else {
  1286. uasm_copy_handler(relocs, labels,
  1287. split, split + 1, f);
  1288. uasm_move_labels(labels, f, f + 1, -1);
  1289. f++;
  1290. split++;
  1291. }
  1292. }
  1293. /* Copy the rest of the handler. */
  1294. uasm_copy_handler(relocs, labels, split, p, final_handler);
  1295. final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
  1296. (p - split);
  1297. }
  1298. }
  1299. break;
  1300. }
  1301. uasm_resolve_relocs(relocs, labels);
  1302. pr_debug("Wrote TLB refill handler (%u instructions).\n",
  1303. final_len);
  1304. memcpy((void *)ebase, final_handler, 0x100);
  1305. local_flush_icache_range(ebase, ebase + 0x100);
  1306. dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100));
  1307. }
  1308. static void setup_pw(void)
  1309. {
  1310. unsigned int pwctl;
  1311. unsigned long pgd_i, pgd_w;
  1312. #ifndef __PAGETABLE_PMD_FOLDED
  1313. unsigned long pmd_i, pmd_w;
  1314. #endif
  1315. unsigned long pt_i, pt_w;
  1316. unsigned long pte_i, pte_w;
  1317. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1318. unsigned long psn;
  1319. psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
  1320. #endif
  1321. pgd_i = PGDIR_SHIFT; /* 1st level PGD */
  1322. #ifndef __PAGETABLE_PMD_FOLDED
  1323. pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
  1324. pmd_i = PMD_SHIFT; /* 2nd level PMD */
  1325. pmd_w = PMD_SHIFT - PAGE_SHIFT;
  1326. #else
  1327. pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
  1328. #endif
  1329. pt_i = PAGE_SHIFT; /* 3rd level PTE */
  1330. pt_w = PAGE_SHIFT - 3;
  1331. pte_i = ilog2(_PAGE_GLOBAL);
  1332. pte_w = 0;
  1333. pwctl = 1 << 30; /* Set PWDirExt */
  1334. #ifndef __PAGETABLE_PMD_FOLDED
  1335. write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
  1336. write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
  1337. #else
  1338. write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
  1339. write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
  1340. #endif
  1341. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1342. pwctl |= (1 << 6 | psn);
  1343. #endif
  1344. write_c0_pwctl(pwctl);
  1345. write_c0_kpgd((long)swapper_pg_dir);
  1346. kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
  1347. }
  1348. static void build_loongson3_tlb_refill_handler(void)
  1349. {
  1350. u32 *p = tlb_handler;
  1351. struct uasm_label *l = labels;
  1352. struct uasm_reloc *r = relocs;
  1353. memset(labels, 0, sizeof(labels));
  1354. memset(relocs, 0, sizeof(relocs));
  1355. memset(tlb_handler, 0, sizeof(tlb_handler));
  1356. if (check_for_high_segbits) {
  1357. uasm_i_dmfc0(&p, K0, C0_BADVADDR);
  1358. uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
  1359. uasm_il_beqz(&p, &r, K1, label_vmalloc);
  1360. uasm_i_nop(&p);
  1361. uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
  1362. uasm_i_nop(&p);
  1363. uasm_l_vmalloc(&l, p);
  1364. }
  1365. uasm_i_dmfc0(&p, K1, C0_PGD);
  1366. uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
  1367. #ifndef __PAGETABLE_PMD_FOLDED
  1368. uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
  1369. #endif
  1370. uasm_i_ldpte(&p, K1, 0); /* even */
  1371. uasm_i_ldpte(&p, K1, 1); /* odd */
  1372. uasm_i_tlbwr(&p);
  1373. /* restore page mask */
  1374. if (PM_DEFAULT_MASK >> 16) {
  1375. uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
  1376. uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
  1377. uasm_i_mtc0(&p, K0, C0_PAGEMASK);
  1378. } else if (PM_DEFAULT_MASK) {
  1379. uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
  1380. uasm_i_mtc0(&p, K0, C0_PAGEMASK);
  1381. } else {
  1382. uasm_i_mtc0(&p, 0, C0_PAGEMASK);
  1383. }
  1384. uasm_i_eret(&p);
  1385. if (check_for_high_segbits) {
  1386. uasm_l_large_segbits_fault(&l, p);
  1387. UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
  1388. uasm_i_jr(&p, K1);
  1389. uasm_i_nop(&p);
  1390. }
  1391. uasm_resolve_relocs(relocs, labels);
  1392. memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
  1393. local_flush_icache_range(ebase + 0x80, ebase + 0x100);
  1394. dump_handler("loongson3_tlb_refill",
  1395. (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100));
  1396. }
  1397. static void build_setup_pgd(void)
  1398. {
  1399. const int a0 = 4;
  1400. const int __maybe_unused a1 = 5;
  1401. const int __maybe_unused a2 = 6;
  1402. u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd);
  1403. #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  1404. long pgdc = (long)pgd_current;
  1405. #endif
  1406. memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p);
  1407. memset(labels, 0, sizeof(labels));
  1408. memset(relocs, 0, sizeof(relocs));
  1409. pgd_reg = allocate_kscratch();
  1410. #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  1411. if (pgd_reg == -1) {
  1412. struct uasm_label *l = labels;
  1413. struct uasm_reloc *r = relocs;
  1414. /* PGD << 11 in c0_Context */
  1415. /*
  1416. * If it is a ckseg0 address, convert to a physical
  1417. * address. Shifting right by 29 and adding 4 will
  1418. * result in zero for these addresses.
  1419. *
  1420. */
  1421. UASM_i_SRA(&p, a1, a0, 29);
  1422. UASM_i_ADDIU(&p, a1, a1, 4);
  1423. uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
  1424. uasm_i_nop(&p);
  1425. uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
  1426. uasm_l_tlbl_goaround1(&l, p);
  1427. UASM_i_SLL(&p, a0, a0, 11);
  1428. UASM_i_MTC0(&p, a0, C0_CONTEXT);
  1429. uasm_i_jr(&p, 31);
  1430. uasm_i_ehb(&p);
  1431. } else {
  1432. /* PGD in c0_KScratch */
  1433. if (cpu_has_ldpte)
  1434. UASM_i_MTC0(&p, a0, C0_PWBASE);
  1435. else
  1436. UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
  1437. uasm_i_jr(&p, 31);
  1438. uasm_i_ehb(&p);
  1439. }
  1440. #else
  1441. #ifdef CONFIG_SMP
  1442. /* Save PGD to pgd_current[smp_processor_id()] */
  1443. UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
  1444. UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
  1445. UASM_i_LA_mostly(&p, a2, pgdc);
  1446. UASM_i_ADDU(&p, a2, a2, a1);
  1447. UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
  1448. #else
  1449. UASM_i_LA_mostly(&p, a2, pgdc);
  1450. UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
  1451. #endif /* SMP */
  1452. /* if pgd_reg is allocated, save PGD also to scratch register */
  1453. if (pgd_reg != -1) {
  1454. UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
  1455. uasm_i_jr(&p, 31);
  1456. uasm_i_ehb(&p);
  1457. } else {
  1458. uasm_i_jr(&p, 31);
  1459. uasm_i_nop(&p);
  1460. }
  1461. #endif
  1462. if (p >= (u32 *)tlbmiss_handler_setup_pgd_end)
  1463. panic("tlbmiss_handler_setup_pgd space exceeded");
  1464. uasm_resolve_relocs(relocs, labels);
  1465. pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
  1466. (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd));
  1467. dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
  1468. tlbmiss_handler_setup_pgd_end);
  1469. }
  1470. static void
  1471. iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
  1472. {
  1473. #ifdef CONFIG_SMP
  1474. if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
  1475. uasm_i_sync(p, 0);
  1476. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1477. if (cpu_has_64bits)
  1478. uasm_i_lld(p, pte, 0, ptr);
  1479. else
  1480. # endif
  1481. UASM_i_LL(p, pte, 0, ptr);
  1482. #else
  1483. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1484. if (cpu_has_64bits)
  1485. uasm_i_ld(p, pte, 0, ptr);
  1486. else
  1487. # endif
  1488. UASM_i_LW(p, pte, 0, ptr);
  1489. #endif
  1490. }
  1491. static void
  1492. iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
  1493. unsigned int mode, unsigned int scratch)
  1494. {
  1495. unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
  1496. unsigned int swmode = mode & ~hwmode;
  1497. if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
  1498. uasm_i_lui(p, scratch, swmode >> 16);
  1499. uasm_i_or(p, pte, pte, scratch);
  1500. BUG_ON(swmode & 0xffff);
  1501. } else {
  1502. uasm_i_ori(p, pte, pte, mode);
  1503. }
  1504. #ifdef CONFIG_SMP
  1505. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1506. if (cpu_has_64bits)
  1507. uasm_i_scd(p, pte, 0, ptr);
  1508. else
  1509. # endif
  1510. UASM_i_SC(p, pte, 0, ptr);
  1511. if (r10000_llsc_war())
  1512. uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
  1513. else
  1514. uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
  1515. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1516. if (!cpu_has_64bits) {
  1517. /* no uasm_i_nop needed */
  1518. uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
  1519. uasm_i_ori(p, pte, pte, hwmode);
  1520. BUG_ON(hwmode & ~0xffff);
  1521. uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
  1522. uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
  1523. /* no uasm_i_nop needed */
  1524. uasm_i_lw(p, pte, 0, ptr);
  1525. } else
  1526. uasm_i_nop(p);
  1527. # else
  1528. uasm_i_nop(p);
  1529. # endif
  1530. #else
  1531. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1532. if (cpu_has_64bits)
  1533. uasm_i_sd(p, pte, 0, ptr);
  1534. else
  1535. # endif
  1536. UASM_i_SW(p, pte, 0, ptr);
  1537. # ifdef CONFIG_PHYS_ADDR_T_64BIT
  1538. if (!cpu_has_64bits) {
  1539. uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
  1540. uasm_i_ori(p, pte, pte, hwmode);
  1541. BUG_ON(hwmode & ~0xffff);
  1542. uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
  1543. uasm_i_lw(p, pte, 0, ptr);
  1544. }
  1545. # endif
  1546. #endif
  1547. }
  1548. /*
  1549. * Check if PTE is present, if not then jump to LABEL. PTR points to
  1550. * the page table where this PTE is located, PTE will be re-loaded
  1551. * with it's original value.
  1552. */
  1553. static void
  1554. build_pte_present(u32 **p, struct uasm_reloc **r,
  1555. int pte, int ptr, int scratch, enum label_id lid)
  1556. {
  1557. int t = scratch >= 0 ? scratch : pte;
  1558. int cur = pte;
  1559. if (cpu_has_rixi) {
  1560. if (use_bbit_insns()) {
  1561. uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
  1562. uasm_i_nop(p);
  1563. } else {
  1564. if (_PAGE_PRESENT_SHIFT) {
  1565. uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
  1566. cur = t;
  1567. }
  1568. uasm_i_andi(p, t, cur, 1);
  1569. uasm_il_beqz(p, r, t, lid);
  1570. if (pte == t)
  1571. /* You lose the SMP race :-(*/
  1572. iPTE_LW(p, pte, ptr);
  1573. }
  1574. } else {
  1575. if (_PAGE_PRESENT_SHIFT) {
  1576. uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
  1577. cur = t;
  1578. }
  1579. uasm_i_andi(p, t, cur,
  1580. (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
  1581. uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
  1582. uasm_il_bnez(p, r, t, lid);
  1583. if (pte == t)
  1584. /* You lose the SMP race :-(*/
  1585. iPTE_LW(p, pte, ptr);
  1586. }
  1587. }
  1588. /* Make PTE valid, store result in PTR. */
  1589. static void
  1590. build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
  1591. unsigned int ptr, unsigned int scratch)
  1592. {
  1593. unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
  1594. iPTE_SW(p, r, pte, ptr, mode, scratch);
  1595. }
  1596. /*
  1597. * Check if PTE can be written to, if not branch to LABEL. Regardless
  1598. * restore PTE with value from PTR when done.
  1599. */
  1600. static void
  1601. build_pte_writable(u32 **p, struct uasm_reloc **r,
  1602. unsigned int pte, unsigned int ptr, int scratch,
  1603. enum label_id lid)
  1604. {
  1605. int t = scratch >= 0 ? scratch : pte;
  1606. int cur = pte;
  1607. if (_PAGE_PRESENT_SHIFT) {
  1608. uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
  1609. cur = t;
  1610. }
  1611. uasm_i_andi(p, t, cur,
  1612. (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
  1613. uasm_i_xori(p, t, t,
  1614. (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
  1615. uasm_il_bnez(p, r, t, lid);
  1616. if (pte == t)
  1617. /* You lose the SMP race :-(*/
  1618. iPTE_LW(p, pte, ptr);
  1619. else
  1620. uasm_i_nop(p);
  1621. }
  1622. /* Make PTE writable, update software status bits as well, then store
  1623. * at PTR.
  1624. */
  1625. static void
  1626. build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
  1627. unsigned int ptr, unsigned int scratch)
  1628. {
  1629. unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
  1630. | _PAGE_DIRTY);
  1631. iPTE_SW(p, r, pte, ptr, mode, scratch);
  1632. }
  1633. /*
  1634. * Check if PTE can be modified, if not branch to LABEL. Regardless
  1635. * restore PTE with value from PTR when done.
  1636. */
  1637. static void
  1638. build_pte_modifiable(u32 **p, struct uasm_reloc **r,
  1639. unsigned int pte, unsigned int ptr, int scratch,
  1640. enum label_id lid)
  1641. {
  1642. if (use_bbit_insns()) {
  1643. uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
  1644. uasm_i_nop(p);
  1645. } else {
  1646. int t = scratch >= 0 ? scratch : pte;
  1647. uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
  1648. uasm_i_andi(p, t, t, 1);
  1649. uasm_il_beqz(p, r, t, lid);
  1650. if (pte == t)
  1651. /* You lose the SMP race :-(*/
  1652. iPTE_LW(p, pte, ptr);
  1653. }
  1654. }
  1655. #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  1656. /*
  1657. * R3000 style TLB load/store/modify handlers.
  1658. */
  1659. /*
  1660. * This places the pte into ENTRYLO0 and writes it with tlbwi.
  1661. * Then it returns.
  1662. */
  1663. static void
  1664. build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
  1665. {
  1666. uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
  1667. uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
  1668. uasm_i_tlbwi(p);
  1669. uasm_i_jr(p, tmp);
  1670. uasm_i_rfe(p); /* branch delay */
  1671. }
  1672. /*
  1673. * This places the pte into ENTRYLO0 and writes it with tlbwi
  1674. * or tlbwr as appropriate. This is because the index register
  1675. * may have the probe fail bit set as a result of a trap on a
  1676. * kseg2 access, i.e. without refill. Then it returns.
  1677. */
  1678. static void
  1679. build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
  1680. struct uasm_reloc **r, unsigned int pte,
  1681. unsigned int tmp)
  1682. {
  1683. uasm_i_mfc0(p, tmp, C0_INDEX);
  1684. uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
  1685. uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
  1686. uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
  1687. uasm_i_tlbwi(p); /* cp0 delay */
  1688. uasm_i_jr(p, tmp);
  1689. uasm_i_rfe(p); /* branch delay */
  1690. uasm_l_r3000_write_probe_fail(l, *p);
  1691. uasm_i_tlbwr(p); /* cp0 delay */
  1692. uasm_i_jr(p, tmp);
  1693. uasm_i_rfe(p); /* branch delay */
  1694. }
  1695. static void
  1696. build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
  1697. unsigned int ptr)
  1698. {
  1699. long pgdc = (long)pgd_current;
  1700. uasm_i_mfc0(p, pte, C0_BADVADDR);
  1701. uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
  1702. uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
  1703. uasm_i_srl(p, pte, pte, 22); /* load delay */
  1704. uasm_i_sll(p, pte, pte, 2);
  1705. uasm_i_addu(p, ptr, ptr, pte);
  1706. uasm_i_mfc0(p, pte, C0_CONTEXT);
  1707. uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
  1708. uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
  1709. uasm_i_addu(p, ptr, ptr, pte);
  1710. uasm_i_lw(p, pte, 0, ptr);
  1711. uasm_i_tlbp(p); /* load delay */
  1712. }
  1713. static void build_r3000_tlb_load_handler(void)
  1714. {
  1715. u32 *p = (u32 *)handle_tlbl;
  1716. struct uasm_label *l = labels;
  1717. struct uasm_reloc *r = relocs;
  1718. memset(p, 0, handle_tlbl_end - (char *)p);
  1719. memset(labels, 0, sizeof(labels));
  1720. memset(relocs, 0, sizeof(relocs));
  1721. build_r3000_tlbchange_handler_head(&p, K0, K1);
  1722. build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
  1723. uasm_i_nop(&p); /* load delay */
  1724. build_make_valid(&p, &r, K0, K1, -1);
  1725. build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
  1726. uasm_l_nopage_tlbl(&l, p);
  1727. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
  1728. uasm_i_nop(&p);
  1729. if (p >= (u32 *)handle_tlbl_end)
  1730. panic("TLB load handler fastpath space exceeded");
  1731. uasm_resolve_relocs(relocs, labels);
  1732. pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
  1733. (unsigned int)(p - (u32 *)handle_tlbl));
  1734. dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end);
  1735. }
  1736. static void build_r3000_tlb_store_handler(void)
  1737. {
  1738. u32 *p = (u32 *)handle_tlbs;
  1739. struct uasm_label *l = labels;
  1740. struct uasm_reloc *r = relocs;
  1741. memset(p, 0, handle_tlbs_end - (char *)p);
  1742. memset(labels, 0, sizeof(labels));
  1743. memset(relocs, 0, sizeof(relocs));
  1744. build_r3000_tlbchange_handler_head(&p, K0, K1);
  1745. build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
  1746. uasm_i_nop(&p); /* load delay */
  1747. build_make_write(&p, &r, K0, K1, -1);
  1748. build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
  1749. uasm_l_nopage_tlbs(&l, p);
  1750. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
  1751. uasm_i_nop(&p);
  1752. if (p >= (u32 *)handle_tlbs_end)
  1753. panic("TLB store handler fastpath space exceeded");
  1754. uasm_resolve_relocs(relocs, labels);
  1755. pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
  1756. (unsigned int)(p - (u32 *)handle_tlbs));
  1757. dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end);
  1758. }
  1759. static void build_r3000_tlb_modify_handler(void)
  1760. {
  1761. u32 *p = (u32 *)handle_tlbm;
  1762. struct uasm_label *l = labels;
  1763. struct uasm_reloc *r = relocs;
  1764. memset(p, 0, handle_tlbm_end - (char *)p);
  1765. memset(labels, 0, sizeof(labels));
  1766. memset(relocs, 0, sizeof(relocs));
  1767. build_r3000_tlbchange_handler_head(&p, K0, K1);
  1768. build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
  1769. uasm_i_nop(&p); /* load delay */
  1770. build_make_write(&p, &r, K0, K1, -1);
  1771. build_r3000_pte_reload_tlbwi(&p, K0, K1);
  1772. uasm_l_nopage_tlbm(&l, p);
  1773. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
  1774. uasm_i_nop(&p);
  1775. if (p >= (u32 *)handle_tlbm_end)
  1776. panic("TLB modify handler fastpath space exceeded");
  1777. uasm_resolve_relocs(relocs, labels);
  1778. pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
  1779. (unsigned int)(p - (u32 *)handle_tlbm));
  1780. dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end);
  1781. }
  1782. #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
  1783. static bool cpu_has_tlbex_tlbp_race(void)
  1784. {
  1785. /*
  1786. * When a Hardware Table Walker is running it can replace TLB entries
  1787. * at any time, leading to a race between it & the CPU.
  1788. */
  1789. if (cpu_has_htw)
  1790. return true;
  1791. /*
  1792. * If the CPU shares FTLB RAM with its siblings then our entry may be
  1793. * replaced at any time by a sibling performing a write to the FTLB.
  1794. */
  1795. if (cpu_has_shared_ftlb_ram)
  1796. return true;
  1797. /* In all other cases there ought to be no race condition to handle */
  1798. return false;
  1799. }
  1800. /*
  1801. * R4000 style TLB load/store/modify handlers.
  1802. */
  1803. static struct work_registers
  1804. build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
  1805. struct uasm_reloc **r)
  1806. {
  1807. struct work_registers wr = build_get_work_registers(p);
  1808. #ifdef CONFIG_64BIT
  1809. build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
  1810. #else
  1811. build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
  1812. #endif
  1813. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1814. /*
  1815. * For huge tlb entries, pmd doesn't contain an address but
  1816. * instead contains the tlb pte. Check the PAGE_HUGE bit and
  1817. * see if we need to jump to huge tlb processing.
  1818. */
  1819. build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
  1820. #endif
  1821. UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
  1822. UASM_i_LW(p, wr.r2, 0, wr.r2);
  1823. UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
  1824. uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
  1825. UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
  1826. #ifdef CONFIG_SMP
  1827. uasm_l_smp_pgtable_change(l, *p);
  1828. #endif
  1829. iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
  1830. if (!m4kc_tlbp_war()) {
  1831. build_tlb_probe_entry(p);
  1832. if (cpu_has_tlbex_tlbp_race()) {
  1833. /* race condition happens, leaving */
  1834. uasm_i_ehb(p);
  1835. uasm_i_mfc0(p, wr.r3, C0_INDEX);
  1836. uasm_il_bltz(p, r, wr.r3, label_leave);
  1837. uasm_i_nop(p);
  1838. }
  1839. }
  1840. return wr;
  1841. }
  1842. static void
  1843. build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
  1844. struct uasm_reloc **r, unsigned int tmp,
  1845. unsigned int ptr)
  1846. {
  1847. uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
  1848. uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
  1849. build_update_entries(p, tmp, ptr);
  1850. build_tlb_write_entry(p, l, r, tlb_indexed);
  1851. uasm_l_leave(l, *p);
  1852. build_restore_work_registers(p);
  1853. uasm_i_eret(p); /* return from trap */
  1854. #ifdef CONFIG_64BIT
  1855. build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
  1856. #endif
  1857. }
  1858. static void build_r4000_tlb_load_handler(void)
  1859. {
  1860. u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
  1861. struct uasm_label *l = labels;
  1862. struct uasm_reloc *r = relocs;
  1863. struct work_registers wr;
  1864. memset(p, 0, handle_tlbl_end - (char *)p);
  1865. memset(labels, 0, sizeof(labels));
  1866. memset(relocs, 0, sizeof(relocs));
  1867. if (bcm1250_m3_war()) {
  1868. unsigned int segbits = 44;
  1869. uasm_i_dmfc0(&p, K0, C0_BADVADDR);
  1870. uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
  1871. uasm_i_xor(&p, K0, K0, K1);
  1872. uasm_i_dsrl_safe(&p, K1, K0, 62);
  1873. uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
  1874. uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
  1875. uasm_i_or(&p, K0, K0, K1);
  1876. uasm_il_bnez(&p, &r, K0, label_leave);
  1877. /* No need for uasm_i_nop */
  1878. }
  1879. wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
  1880. build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
  1881. if (m4kc_tlbp_war())
  1882. build_tlb_probe_entry(&p);
  1883. if (cpu_has_rixi && !cpu_has_rixiex) {
  1884. /*
  1885. * If the page is not _PAGE_VALID, RI or XI could not
  1886. * have triggered it. Skip the expensive test..
  1887. */
  1888. if (use_bbit_insns()) {
  1889. uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
  1890. label_tlbl_goaround1);
  1891. } else {
  1892. uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
  1893. uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
  1894. }
  1895. uasm_i_nop(&p);
  1896. /*
  1897. * Warn if something may race with us & replace the TLB entry
  1898. * before we read it here. Everything with such races should
  1899. * also have dedicated RiXi exception handlers, so this
  1900. * shouldn't be hit.
  1901. */
  1902. WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
  1903. uasm_i_tlbr(&p);
  1904. switch (current_cpu_type()) {
  1905. default:
  1906. if (cpu_has_mips_r2_exec_hazard) {
  1907. uasm_i_ehb(&p);
  1908. case CPU_CAVIUM_OCTEON:
  1909. case CPU_CAVIUM_OCTEON_PLUS:
  1910. case CPU_CAVIUM_OCTEON2:
  1911. break;
  1912. }
  1913. }
  1914. /* Examine entrylo 0 or 1 based on ptr. */
  1915. if (use_bbit_insns()) {
  1916. uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
  1917. } else {
  1918. uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
  1919. uasm_i_beqz(&p, wr.r3, 8);
  1920. }
  1921. /* load it in the delay slot*/
  1922. UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
  1923. /* load it if ptr is odd */
  1924. UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
  1925. /*
  1926. * If the entryLo (now in wr.r3) is valid (bit 1), RI or
  1927. * XI must have triggered it.
  1928. */
  1929. if (use_bbit_insns()) {
  1930. uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
  1931. uasm_i_nop(&p);
  1932. uasm_l_tlbl_goaround1(&l, p);
  1933. } else {
  1934. uasm_i_andi(&p, wr.r3, wr.r3, 2);
  1935. uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
  1936. uasm_i_nop(&p);
  1937. }
  1938. uasm_l_tlbl_goaround1(&l, p);
  1939. }
  1940. build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
  1941. build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
  1942. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  1943. /*
  1944. * This is the entry point when build_r4000_tlbchange_handler_head
  1945. * spots a huge page.
  1946. */
  1947. uasm_l_tlb_huge_update(&l, p);
  1948. iPTE_LW(&p, wr.r1, wr.r2);
  1949. build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
  1950. build_tlb_probe_entry(&p);
  1951. if (cpu_has_rixi && !cpu_has_rixiex) {
  1952. /*
  1953. * If the page is not _PAGE_VALID, RI or XI could not
  1954. * have triggered it. Skip the expensive test..
  1955. */
  1956. if (use_bbit_insns()) {
  1957. uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
  1958. label_tlbl_goaround2);
  1959. } else {
  1960. uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
  1961. uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
  1962. }
  1963. uasm_i_nop(&p);
  1964. /*
  1965. * Warn if something may race with us & replace the TLB entry
  1966. * before we read it here. Everything with such races should
  1967. * also have dedicated RiXi exception handlers, so this
  1968. * shouldn't be hit.
  1969. */
  1970. WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
  1971. uasm_i_tlbr(&p);
  1972. switch (current_cpu_type()) {
  1973. default:
  1974. if (cpu_has_mips_r2_exec_hazard) {
  1975. uasm_i_ehb(&p);
  1976. case CPU_CAVIUM_OCTEON:
  1977. case CPU_CAVIUM_OCTEON_PLUS:
  1978. case CPU_CAVIUM_OCTEON2:
  1979. break;
  1980. }
  1981. }
  1982. /* Examine entrylo 0 or 1 based on ptr. */
  1983. if (use_bbit_insns()) {
  1984. uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
  1985. } else {
  1986. uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
  1987. uasm_i_beqz(&p, wr.r3, 8);
  1988. }
  1989. /* load it in the delay slot*/
  1990. UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
  1991. /* load it if ptr is odd */
  1992. UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
  1993. /*
  1994. * If the entryLo (now in wr.r3) is valid (bit 1), RI or
  1995. * XI must have triggered it.
  1996. */
  1997. if (use_bbit_insns()) {
  1998. uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
  1999. } else {
  2000. uasm_i_andi(&p, wr.r3, wr.r3, 2);
  2001. uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
  2002. }
  2003. if (PM_DEFAULT_MASK == 0)
  2004. uasm_i_nop(&p);
  2005. /*
  2006. * We clobbered C0_PAGEMASK, restore it. On the other branch
  2007. * it is restored in build_huge_tlb_write_entry.
  2008. */
  2009. build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
  2010. uasm_l_tlbl_goaround2(&l, p);
  2011. }
  2012. uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
  2013. build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
  2014. #endif
  2015. uasm_l_nopage_tlbl(&l, p);
  2016. if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
  2017. uasm_i_sync(&p, 0);
  2018. build_restore_work_registers(&p);
  2019. #ifdef CONFIG_CPU_MICROMIPS
  2020. if ((unsigned long)tlb_do_page_fault_0 & 1) {
  2021. uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
  2022. uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
  2023. uasm_i_jr(&p, K0);
  2024. } else
  2025. #endif
  2026. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
  2027. uasm_i_nop(&p);
  2028. if (p >= (u32 *)handle_tlbl_end)
  2029. panic("TLB load handler fastpath space exceeded");
  2030. uasm_resolve_relocs(relocs, labels);
  2031. pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
  2032. (unsigned int)(p - (u32 *)handle_tlbl));
  2033. dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end);
  2034. }
  2035. static void build_r4000_tlb_store_handler(void)
  2036. {
  2037. u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
  2038. struct uasm_label *l = labels;
  2039. struct uasm_reloc *r = relocs;
  2040. struct work_registers wr;
  2041. memset(p, 0, handle_tlbs_end - (char *)p);
  2042. memset(labels, 0, sizeof(labels));
  2043. memset(relocs, 0, sizeof(relocs));
  2044. wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
  2045. build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
  2046. if (m4kc_tlbp_war())
  2047. build_tlb_probe_entry(&p);
  2048. build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
  2049. build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
  2050. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  2051. /*
  2052. * This is the entry point when
  2053. * build_r4000_tlbchange_handler_head spots a huge page.
  2054. */
  2055. uasm_l_tlb_huge_update(&l, p);
  2056. iPTE_LW(&p, wr.r1, wr.r2);
  2057. build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
  2058. build_tlb_probe_entry(&p);
  2059. uasm_i_ori(&p, wr.r1, wr.r1,
  2060. _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
  2061. build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
  2062. #endif
  2063. uasm_l_nopage_tlbs(&l, p);
  2064. if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
  2065. uasm_i_sync(&p, 0);
  2066. build_restore_work_registers(&p);
  2067. #ifdef CONFIG_CPU_MICROMIPS
  2068. if ((unsigned long)tlb_do_page_fault_1 & 1) {
  2069. uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
  2070. uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
  2071. uasm_i_jr(&p, K0);
  2072. } else
  2073. #endif
  2074. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
  2075. uasm_i_nop(&p);
  2076. if (p >= (u32 *)handle_tlbs_end)
  2077. panic("TLB store handler fastpath space exceeded");
  2078. uasm_resolve_relocs(relocs, labels);
  2079. pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
  2080. (unsigned int)(p - (u32 *)handle_tlbs));
  2081. dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end);
  2082. }
  2083. static void build_r4000_tlb_modify_handler(void)
  2084. {
  2085. u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
  2086. struct uasm_label *l = labels;
  2087. struct uasm_reloc *r = relocs;
  2088. struct work_registers wr;
  2089. memset(p, 0, handle_tlbm_end - (char *)p);
  2090. memset(labels, 0, sizeof(labels));
  2091. memset(relocs, 0, sizeof(relocs));
  2092. wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
  2093. build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
  2094. if (m4kc_tlbp_war())
  2095. build_tlb_probe_entry(&p);
  2096. /* Present and writable bits set, set accessed and dirty bits. */
  2097. build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
  2098. build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
  2099. #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
  2100. /*
  2101. * This is the entry point when
  2102. * build_r4000_tlbchange_handler_head spots a huge page.
  2103. */
  2104. uasm_l_tlb_huge_update(&l, p);
  2105. iPTE_LW(&p, wr.r1, wr.r2);
  2106. build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
  2107. build_tlb_probe_entry(&p);
  2108. uasm_i_ori(&p, wr.r1, wr.r1,
  2109. _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
  2110. build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
  2111. #endif
  2112. uasm_l_nopage_tlbm(&l, p);
  2113. if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
  2114. uasm_i_sync(&p, 0);
  2115. build_restore_work_registers(&p);
  2116. #ifdef CONFIG_CPU_MICROMIPS
  2117. if ((unsigned long)tlb_do_page_fault_1 & 1) {
  2118. uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
  2119. uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
  2120. uasm_i_jr(&p, K0);
  2121. } else
  2122. #endif
  2123. uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
  2124. uasm_i_nop(&p);
  2125. if (p >= (u32 *)handle_tlbm_end)
  2126. panic("TLB modify handler fastpath space exceeded");
  2127. uasm_resolve_relocs(relocs, labels);
  2128. pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
  2129. (unsigned int)(p - (u32 *)handle_tlbm));
  2130. dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end);
  2131. }
  2132. static void flush_tlb_handlers(void)
  2133. {
  2134. local_flush_icache_range((unsigned long)handle_tlbl,
  2135. (unsigned long)handle_tlbl_end);
  2136. local_flush_icache_range((unsigned long)handle_tlbs,
  2137. (unsigned long)handle_tlbs_end);
  2138. local_flush_icache_range((unsigned long)handle_tlbm,
  2139. (unsigned long)handle_tlbm_end);
  2140. local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
  2141. (unsigned long)tlbmiss_handler_setup_pgd_end);
  2142. }
  2143. static void print_htw_config(void)
  2144. {
  2145. unsigned long config;
  2146. unsigned int pwctl;
  2147. const int field = 2 * sizeof(unsigned long);
  2148. config = read_c0_pwfield();
  2149. pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
  2150. field, config,
  2151. (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
  2152. (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
  2153. (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
  2154. (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
  2155. (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
  2156. config = read_c0_pwsize();
  2157. pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
  2158. field, config,
  2159. (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
  2160. (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
  2161. (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
  2162. (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
  2163. (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
  2164. (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
  2165. pwctl = read_c0_pwctl();
  2166. pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
  2167. pwctl,
  2168. (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
  2169. (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
  2170. (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
  2171. (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
  2172. (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
  2173. (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
  2174. (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
  2175. }
  2176. static void config_htw_params(void)
  2177. {
  2178. unsigned long pwfield, pwsize, ptei;
  2179. unsigned int config;
  2180. /*
  2181. * We are using 2-level page tables, so we only need to
  2182. * setup GDW and PTW appropriately. UDW and MDW will remain 0.
  2183. * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
  2184. * write values less than 0xc in these fields because the entire
  2185. * write will be dropped. As a result of which, we must preserve
  2186. * the original reset values and overwrite only what we really want.
  2187. */
  2188. pwfield = read_c0_pwfield();
  2189. /* re-initialize the GDI field */
  2190. pwfield &= ~MIPS_PWFIELD_GDI_MASK;
  2191. pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
  2192. /* re-initialize the PTI field including the even/odd bit */
  2193. pwfield &= ~MIPS_PWFIELD_PTI_MASK;
  2194. pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
  2195. if (CONFIG_PGTABLE_LEVELS >= 3) {
  2196. pwfield &= ~MIPS_PWFIELD_MDI_MASK;
  2197. pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
  2198. }
  2199. /* Set the PTEI right shift */
  2200. ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
  2201. pwfield |= ptei;
  2202. write_c0_pwfield(pwfield);
  2203. /* Check whether the PTEI value is supported */
  2204. back_to_back_c0_hazard();
  2205. pwfield = read_c0_pwfield();
  2206. if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
  2207. != ptei) {
  2208. pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
  2209. ptei);
  2210. /*
  2211. * Drop option to avoid HTW being enabled via another path
  2212. * (eg htw_reset())
  2213. */
  2214. current_cpu_data.options &= ~MIPS_CPU_HTW;
  2215. return;
  2216. }
  2217. pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
  2218. pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
  2219. if (CONFIG_PGTABLE_LEVELS >= 3)
  2220. pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
  2221. /* Set pointer size to size of directory pointers */
  2222. if (IS_ENABLED(CONFIG_64BIT))
  2223. pwsize |= MIPS_PWSIZE_PS_MASK;
  2224. /* PTEs may be multiple pointers long (e.g. with XPA) */
  2225. pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
  2226. & MIPS_PWSIZE_PTEW_MASK;
  2227. write_c0_pwsize(pwsize);
  2228. /* Make sure everything is set before we enable the HTW */
  2229. back_to_back_c0_hazard();
  2230. /*
  2231. * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
  2232. * the pwctl fields.
  2233. */
  2234. config = 1 << MIPS_PWCTL_PWEN_SHIFT;
  2235. if (IS_ENABLED(CONFIG_64BIT))
  2236. config |= MIPS_PWCTL_XU_MASK;
  2237. write_c0_pwctl(config);
  2238. pr_info("Hardware Page Table Walker enabled\n");
  2239. print_htw_config();
  2240. }
  2241. static void config_xpa_params(void)
  2242. {
  2243. #ifdef CONFIG_XPA
  2244. unsigned int pagegrain;
  2245. if (mips_xpa_disabled) {
  2246. pr_info("Extended Physical Addressing (XPA) disabled\n");
  2247. return;
  2248. }
  2249. pagegrain = read_c0_pagegrain();
  2250. write_c0_pagegrain(pagegrain | PG_ELPA);
  2251. back_to_back_c0_hazard();
  2252. pagegrain = read_c0_pagegrain();
  2253. if (pagegrain & PG_ELPA)
  2254. pr_info("Extended Physical Addressing (XPA) enabled\n");
  2255. else
  2256. panic("Extended Physical Addressing (XPA) disabled");
  2257. #endif
  2258. }
  2259. static void check_pabits(void)
  2260. {
  2261. unsigned long entry;
  2262. unsigned pabits, fillbits;
  2263. if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
  2264. /*
  2265. * We'll only be making use of the fact that we can rotate bits
  2266. * into the fill if the CPU supports RIXI, so don't bother
  2267. * probing this for CPUs which don't.
  2268. */
  2269. return;
  2270. }
  2271. write_c0_entrylo0(~0ul);
  2272. back_to_back_c0_hazard();
  2273. entry = read_c0_entrylo0();
  2274. /* clear all non-PFN bits */
  2275. entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
  2276. entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
  2277. /* find a lower bound on PABITS, and upper bound on fill bits */
  2278. pabits = fls_long(entry) + 6;
  2279. fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
  2280. /* minus the RI & XI bits */
  2281. fillbits -= min_t(unsigned, fillbits, 2);
  2282. if (fillbits >= ilog2(_PAGE_NO_EXEC))
  2283. fill_includes_sw_bits = true;
  2284. pr_debug("Entry* registers contain %u fill bits\n", fillbits);
  2285. }
  2286. void build_tlb_refill_handler(void)
  2287. {
  2288. /*
  2289. * The refill handler is generated per-CPU, multi-node systems
  2290. * may have local storage for it. The other handlers are only
  2291. * needed once.
  2292. */
  2293. static int run_once = 0;
  2294. if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
  2295. panic("Kernels supporting XPA currently require CPUs with RIXI");
  2296. output_pgtable_bits_defines();
  2297. check_pabits();
  2298. #ifdef CONFIG_64BIT
  2299. check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
  2300. #endif
  2301. if (cpu_has_3kex) {
  2302. #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  2303. if (!run_once) {
  2304. build_setup_pgd();
  2305. build_r3000_tlb_refill_handler();
  2306. build_r3000_tlb_load_handler();
  2307. build_r3000_tlb_store_handler();
  2308. build_r3000_tlb_modify_handler();
  2309. flush_tlb_handlers();
  2310. run_once++;
  2311. }
  2312. #else
  2313. panic("No R3000 TLB refill handler");
  2314. #endif
  2315. return;
  2316. }
  2317. if (cpu_has_ldpte)
  2318. setup_pw();
  2319. if (!run_once) {
  2320. scratch_reg = allocate_kscratch();
  2321. build_setup_pgd();
  2322. build_r4000_tlb_load_handler();
  2323. build_r4000_tlb_store_handler();
  2324. build_r4000_tlb_modify_handler();
  2325. if (cpu_has_ldpte)
  2326. build_loongson3_tlb_refill_handler();
  2327. else
  2328. build_r4000_tlb_refill_handler();
  2329. flush_tlb_handlers();
  2330. run_once++;
  2331. }
  2332. if (cpu_has_xpa)
  2333. config_xpa_params();
  2334. if (cpu_has_htw)
  2335. config_htw_params();
  2336. }