sc-mips.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2006 Chris Dearman (chris@mips.com),
  4. */
  5. #include <linux/init.h>
  6. #include <linux/kernel.h>
  7. #include <linux/sched.h>
  8. #include <linux/mm.h>
  9. #include <asm/cpu-type.h>
  10. #include <asm/mipsregs.h>
  11. #include <asm/bcache.h>
  12. #include <asm/cacheops.h>
  13. #include <asm/page.h>
  14. #include <asm/mmu_context.h>
  15. #include <asm/r4kcache.h>
  16. #include <asm/mips-cps.h>
  17. #include <asm/bootinfo.h>
  18. /*
  19. * MIPS32/MIPS64 L2 cache handling
  20. */
  21. /*
  22. * Writeback and invalidate the secondary cache before DMA.
  23. */
  24. static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
  25. {
  26. blast_scache_range(addr, addr + size);
  27. }
  28. /*
  29. * Invalidate the secondary cache before DMA.
  30. */
  31. static void mips_sc_inv(unsigned long addr, unsigned long size)
  32. {
  33. unsigned long lsize = cpu_scache_line_size();
  34. unsigned long almask = ~(lsize - 1);
  35. cache_op(Hit_Writeback_Inv_SD, addr & almask);
  36. cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
  37. blast_inv_scache_range(addr, addr + size);
  38. }
  39. static void mips_sc_enable(void)
  40. {
  41. /* L2 cache is permanently enabled */
  42. }
  43. static void mips_sc_disable(void)
  44. {
  45. /* L2 cache is permanently enabled */
  46. }
  47. static void mips_sc_prefetch_enable(void)
  48. {
  49. unsigned long pftctl;
  50. if (mips_cm_revision() < CM_REV_CM2_5)
  51. return;
  52. /*
  53. * If there is one or more L2 prefetch unit present then enable
  54. * prefetching for both code & data, for all ports.
  55. */
  56. pftctl = read_gcr_l2_pft_control();
  57. if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT) {
  58. pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK;
  59. pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK;
  60. pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN;
  61. write_gcr_l2_pft_control(pftctl);
  62. set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
  63. CM_GCR_L2_PFT_CONTROL_B_CEN);
  64. }
  65. }
  66. static void mips_sc_prefetch_disable(void)
  67. {
  68. if (mips_cm_revision() < CM_REV_CM2_5)
  69. return;
  70. clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN);
  71. clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
  72. CM_GCR_L2_PFT_CONTROL_B_CEN);
  73. }
  74. static bool mips_sc_prefetch_is_enabled(void)
  75. {
  76. unsigned long pftctl;
  77. if (mips_cm_revision() < CM_REV_CM2_5)
  78. return false;
  79. pftctl = read_gcr_l2_pft_control();
  80. if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT))
  81. return false;
  82. return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN);
  83. }
  84. static struct bcache_ops mips_sc_ops = {
  85. .bc_enable = mips_sc_enable,
  86. .bc_disable = mips_sc_disable,
  87. .bc_wback_inv = mips_sc_wback_inv,
  88. .bc_inv = mips_sc_inv,
  89. .bc_prefetch_enable = mips_sc_prefetch_enable,
  90. .bc_prefetch_disable = mips_sc_prefetch_disable,
  91. .bc_prefetch_is_enabled = mips_sc_prefetch_is_enabled,
  92. };
  93. /*
  94. * Check if the L2 cache controller is activated on a particular platform.
  95. * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
  96. * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
  97. * cache being disabled. However there is no guarantee for this to be
  98. * true on all platforms. In an act of stupidity the spec defined bits
  99. * 12..15 as implementation defined so below function will eventually have
  100. * to be replaced by a platform specific probe.
  101. */
  102. static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
  103. {
  104. unsigned int config2 = read_c0_config2();
  105. unsigned int tmp;
  106. /* Check the bypass bit (L2B) */
  107. switch (current_cpu_type()) {
  108. case CPU_34K:
  109. case CPU_74K:
  110. case CPU_1004K:
  111. case CPU_1074K:
  112. case CPU_INTERAPTIV:
  113. case CPU_PROAPTIV:
  114. case CPU_P5600:
  115. case CPU_BMIPS5000:
  116. case CPU_QEMU_GENERIC:
  117. case CPU_P6600:
  118. if (config2 & (1 << 12))
  119. return 0;
  120. }
  121. tmp = (config2 >> 4) & 0x0f;
  122. if (0 < tmp && tmp <= 7)
  123. c->scache.linesz = 2 << tmp;
  124. else
  125. return 0;
  126. return 1;
  127. }
  128. static int mips_sc_probe_cm3(void)
  129. {
  130. struct cpuinfo_mips *c = &current_cpu_data;
  131. unsigned long cfg = read_gcr_l2_config();
  132. unsigned long sets, line_sz, assoc;
  133. if (cfg & CM_GCR_L2_CONFIG_BYPASS)
  134. return 0;
  135. sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE;
  136. sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE);
  137. if (sets)
  138. c->scache.sets = 64 << sets;
  139. line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE;
  140. line_sz >>= __ffs(CM_GCR_L2_CONFIG_LINE_SIZE);
  141. if (line_sz)
  142. c->scache.linesz = 2 << line_sz;
  143. assoc = cfg & CM_GCR_L2_CONFIG_ASSOC;
  144. assoc >>= __ffs(CM_GCR_L2_CONFIG_ASSOC);
  145. c->scache.ways = assoc + 1;
  146. c->scache.waysize = c->scache.sets * c->scache.linesz;
  147. c->scache.waybit = __ffs(c->scache.waysize);
  148. if (c->scache.linesz) {
  149. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  150. c->options |= MIPS_CPU_INCLUSIVE_CACHES;
  151. return 1;
  152. }
  153. return 0;
  154. }
  155. static inline int mips_sc_probe(void)
  156. {
  157. struct cpuinfo_mips *c = &current_cpu_data;
  158. unsigned int config1, config2;
  159. unsigned int tmp;
  160. /* Mark as not present until probe completed */
  161. c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
  162. if (mips_cm_revision() >= CM_REV_CM3)
  163. return mips_sc_probe_cm3();
  164. /* Ignore anything but MIPSxx processors */
  165. if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
  166. MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
  167. MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
  168. MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)))
  169. return 0;
  170. /* Does this MIPS32/MIPS64 CPU have a config2 register? */
  171. config1 = read_c0_config1();
  172. if (!(config1 & MIPS_CONF_M))
  173. return 0;
  174. config2 = read_c0_config2();
  175. if (!mips_sc_is_activated(c))
  176. return 0;
  177. tmp = (config2 >> 8) & 0x0f;
  178. if (tmp <= 7)
  179. c->scache.sets = 64 << tmp;
  180. else
  181. return 0;
  182. tmp = (config2 >> 0) & 0x0f;
  183. if (tmp <= 7)
  184. c->scache.ways = tmp + 1;
  185. else
  186. return 0;
  187. if (current_cpu_type() == CPU_XBURST) {
  188. switch (mips_machtype) {
  189. /*
  190. * According to config2 it would be 5-ways, but that is
  191. * contradicted by all documentation.
  192. */
  193. case MACH_INGENIC_JZ4770:
  194. case MACH_INGENIC_JZ4775:
  195. c->scache.ways = 4;
  196. break;
  197. /*
  198. * According to config2 it would be 5-ways and 512-sets,
  199. * but that is contradicted by all documentation.
  200. */
  201. case MACH_INGENIC_X1000:
  202. case MACH_INGENIC_X1000E:
  203. c->scache.sets = 256;
  204. c->scache.ways = 4;
  205. break;
  206. }
  207. }
  208. c->scache.waysize = c->scache.sets * c->scache.linesz;
  209. c->scache.waybit = __ffs(c->scache.waysize);
  210. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  211. return 1;
  212. }
  213. int mips_sc_init(void)
  214. {
  215. int found = mips_sc_probe();
  216. if (found) {
  217. mips_sc_enable();
  218. mips_sc_prefetch_enable();
  219. bcops = &mips_sc_ops;
  220. }
  221. return found;
  222. }