c-tx39.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r2300.c: R2000 and R3000 specific mmu/cache code.
  4. *
  5. * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  6. *
  7. * with a lot of changes to make this thing work for R3000s
  8. * Tx39XX R4k style caches added. HK
  9. * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
  10. * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/smp.h>
  16. #include <linux/mm.h>
  17. #include <asm/cacheops.h>
  18. #include <asm/page.h>
  19. #include <asm/mmu_context.h>
  20. #include <asm/isadep.h>
  21. #include <asm/io.h>
  22. #include <asm/bootinfo.h>
  23. #include <asm/cpu.h>
  24. /* For R3000 cores with R4000 style caches */
  25. static unsigned long icache_size, dcache_size; /* Size in bytes */
  26. #include <asm/r4kcache.h>
  27. /* This sequence is required to ensure icache is disabled immediately */
  28. #define TX39_STOP_STREAMING() \
  29. __asm__ __volatile__( \
  30. ".set push\n\t" \
  31. ".set noreorder\n\t" \
  32. "b 1f\n\t" \
  33. "nop\n\t" \
  34. "1:\n\t" \
  35. ".set pop" \
  36. )
  37. /* TX39H-style cache flush routines. */
  38. static void tx39h_flush_icache_all(void)
  39. {
  40. unsigned long flags, config;
  41. /* disable icache (set ICE#) */
  42. local_irq_save(flags);
  43. config = read_c0_conf();
  44. write_c0_conf(config & ~TX39_CONF_ICE);
  45. TX39_STOP_STREAMING();
  46. blast_icache16();
  47. write_c0_conf(config);
  48. local_irq_restore(flags);
  49. }
  50. static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
  51. {
  52. /* Catch bad driver code */
  53. BUG_ON(size == 0);
  54. iob();
  55. blast_inv_dcache_range(addr, addr + size);
  56. }
  57. /* TX39H2,TX39H3 */
  58. static inline void tx39_blast_dcache_page(unsigned long addr)
  59. {
  60. if (current_cpu_type() != CPU_TX3912)
  61. blast_dcache16_page(addr);
  62. }
  63. static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
  64. {
  65. blast_dcache16_page_indexed(addr);
  66. }
  67. static inline void tx39_blast_dcache(void)
  68. {
  69. blast_dcache16();
  70. }
  71. static inline void tx39_blast_icache_page(unsigned long addr)
  72. {
  73. unsigned long flags, config;
  74. /* disable icache (set ICE#) */
  75. local_irq_save(flags);
  76. config = read_c0_conf();
  77. write_c0_conf(config & ~TX39_CONF_ICE);
  78. TX39_STOP_STREAMING();
  79. blast_icache16_page(addr);
  80. write_c0_conf(config);
  81. local_irq_restore(flags);
  82. }
  83. static inline void tx39_blast_icache_page_indexed(unsigned long addr)
  84. {
  85. unsigned long flags, config;
  86. /* disable icache (set ICE#) */
  87. local_irq_save(flags);
  88. config = read_c0_conf();
  89. write_c0_conf(config & ~TX39_CONF_ICE);
  90. TX39_STOP_STREAMING();
  91. blast_icache16_page_indexed(addr);
  92. write_c0_conf(config);
  93. local_irq_restore(flags);
  94. }
  95. static inline void tx39_blast_icache(void)
  96. {
  97. unsigned long flags, config;
  98. /* disable icache (set ICE#) */
  99. local_irq_save(flags);
  100. config = read_c0_conf();
  101. write_c0_conf(config & ~TX39_CONF_ICE);
  102. TX39_STOP_STREAMING();
  103. blast_icache16();
  104. write_c0_conf(config);
  105. local_irq_restore(flags);
  106. }
  107. static void tx39__flush_cache_vmap(void)
  108. {
  109. tx39_blast_dcache();
  110. }
  111. static void tx39__flush_cache_vunmap(void)
  112. {
  113. tx39_blast_dcache();
  114. }
  115. static inline void tx39_flush_cache_all(void)
  116. {
  117. if (!cpu_has_dc_aliases)
  118. return;
  119. tx39_blast_dcache();
  120. }
  121. static inline void tx39___flush_cache_all(void)
  122. {
  123. tx39_blast_dcache();
  124. tx39_blast_icache();
  125. }
  126. static void tx39_flush_cache_mm(struct mm_struct *mm)
  127. {
  128. if (!cpu_has_dc_aliases)
  129. return;
  130. if (cpu_context(smp_processor_id(), mm) != 0)
  131. tx39_blast_dcache();
  132. }
  133. static void tx39_flush_cache_range(struct vm_area_struct *vma,
  134. unsigned long start, unsigned long end)
  135. {
  136. if (!cpu_has_dc_aliases)
  137. return;
  138. if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
  139. return;
  140. tx39_blast_dcache();
  141. }
  142. static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
  143. {
  144. int exec = vma->vm_flags & VM_EXEC;
  145. struct mm_struct *mm = vma->vm_mm;
  146. pmd_t *pmdp;
  147. pte_t *ptep;
  148. /*
  149. * If ownes no valid ASID yet, cannot possibly have gotten
  150. * this page into the cache.
  151. */
  152. if (cpu_context(smp_processor_id(), mm) == 0)
  153. return;
  154. page &= PAGE_MASK;
  155. pmdp = pmd_off(mm, page);
  156. ptep = pte_offset_kernel(pmdp, page);
  157. /*
  158. * If the page isn't marked valid, the page cannot possibly be
  159. * in the cache.
  160. */
  161. if (!(pte_val(*ptep) & _PAGE_PRESENT))
  162. return;
  163. /*
  164. * Doing flushes for another ASID than the current one is
  165. * too difficult since stupid R4k caches do a TLB translation
  166. * for every cache flush operation. So we do indexed flushes
  167. * in that case, which doesn't overly flush the cache too much.
  168. */
  169. if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
  170. if (cpu_has_dc_aliases || exec)
  171. tx39_blast_dcache_page(page);
  172. if (exec)
  173. tx39_blast_icache_page(page);
  174. return;
  175. }
  176. /*
  177. * Do indexed flush, too much work to get the (possible) TLB refills
  178. * to work correctly.
  179. */
  180. if (cpu_has_dc_aliases || exec)
  181. tx39_blast_dcache_page_indexed(page);
  182. if (exec)
  183. tx39_blast_icache_page_indexed(page);
  184. }
  185. static void local_tx39_flush_data_cache_page(void * addr)
  186. {
  187. tx39_blast_dcache_page((unsigned long)addr);
  188. }
  189. static void tx39_flush_data_cache_page(unsigned long addr)
  190. {
  191. tx39_blast_dcache_page(addr);
  192. }
  193. static void tx39_flush_icache_range(unsigned long start, unsigned long end)
  194. {
  195. if (end - start > dcache_size)
  196. tx39_blast_dcache();
  197. else
  198. protected_blast_dcache_range(start, end);
  199. if (end - start > icache_size)
  200. tx39_blast_icache();
  201. else {
  202. unsigned long flags, config;
  203. /* disable icache (set ICE#) */
  204. local_irq_save(flags);
  205. config = read_c0_conf();
  206. write_c0_conf(config & ~TX39_CONF_ICE);
  207. TX39_STOP_STREAMING();
  208. protected_blast_icache_range(start, end);
  209. write_c0_conf(config);
  210. local_irq_restore(flags);
  211. }
  212. }
  213. static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
  214. {
  215. BUG();
  216. }
  217. static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
  218. {
  219. unsigned long end;
  220. if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
  221. end = addr + size;
  222. do {
  223. tx39_blast_dcache_page(addr);
  224. addr += PAGE_SIZE;
  225. } while(addr != end);
  226. } else if (size > dcache_size) {
  227. tx39_blast_dcache();
  228. } else {
  229. blast_dcache_range(addr, addr + size);
  230. }
  231. }
  232. static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
  233. {
  234. unsigned long end;
  235. if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
  236. end = addr + size;
  237. do {
  238. tx39_blast_dcache_page(addr);
  239. addr += PAGE_SIZE;
  240. } while(addr != end);
  241. } else if (size > dcache_size) {
  242. tx39_blast_dcache();
  243. } else {
  244. blast_inv_dcache_range(addr, addr + size);
  245. }
  246. }
  247. static __init void tx39_probe_cache(void)
  248. {
  249. unsigned long config;
  250. config = read_c0_conf();
  251. icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
  252. TX39_CONF_ICS_SHIFT));
  253. dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
  254. TX39_CONF_DCS_SHIFT));
  255. current_cpu_data.icache.linesz = 16;
  256. switch (current_cpu_type()) {
  257. case CPU_TX3912:
  258. current_cpu_data.icache.ways = 1;
  259. current_cpu_data.dcache.ways = 1;
  260. current_cpu_data.dcache.linesz = 4;
  261. break;
  262. case CPU_TX3927:
  263. current_cpu_data.icache.ways = 2;
  264. current_cpu_data.dcache.ways = 2;
  265. current_cpu_data.dcache.linesz = 16;
  266. break;
  267. case CPU_TX3922:
  268. default:
  269. current_cpu_data.icache.ways = 1;
  270. current_cpu_data.dcache.ways = 1;
  271. current_cpu_data.dcache.linesz = 16;
  272. break;
  273. }
  274. }
  275. void tx39_cache_init(void)
  276. {
  277. extern void build_clear_page(void);
  278. extern void build_copy_page(void);
  279. unsigned long config;
  280. config = read_c0_conf();
  281. config &= ~TX39_CONF_WBON;
  282. write_c0_conf(config);
  283. tx39_probe_cache();
  284. switch (current_cpu_type()) {
  285. case CPU_TX3912:
  286. /* TX39/H core (writethru direct-map cache) */
  287. __flush_cache_vmap = tx39__flush_cache_vmap;
  288. __flush_cache_vunmap = tx39__flush_cache_vunmap;
  289. flush_cache_all = tx39h_flush_icache_all;
  290. __flush_cache_all = tx39h_flush_icache_all;
  291. flush_cache_mm = (void *) tx39h_flush_icache_all;
  292. flush_cache_range = (void *) tx39h_flush_icache_all;
  293. flush_cache_page = (void *) tx39h_flush_icache_all;
  294. flush_icache_range = (void *) tx39h_flush_icache_all;
  295. local_flush_icache_range = (void *) tx39h_flush_icache_all;
  296. local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
  297. flush_data_cache_page = (void *) tx39h_flush_icache_all;
  298. _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
  299. shm_align_mask = PAGE_SIZE - 1;
  300. break;
  301. case CPU_TX3922:
  302. case CPU_TX3927:
  303. default:
  304. /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
  305. /* board-dependent init code may set WBON */
  306. __flush_cache_vmap = tx39__flush_cache_vmap;
  307. __flush_cache_vunmap = tx39__flush_cache_vunmap;
  308. flush_cache_all = tx39_flush_cache_all;
  309. __flush_cache_all = tx39___flush_cache_all;
  310. flush_cache_mm = tx39_flush_cache_mm;
  311. flush_cache_range = tx39_flush_cache_range;
  312. flush_cache_page = tx39_flush_cache_page;
  313. flush_icache_range = tx39_flush_icache_range;
  314. local_flush_icache_range = tx39_flush_icache_range;
  315. __flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
  316. local_flush_data_cache_page = local_tx39_flush_data_cache_page;
  317. flush_data_cache_page = tx39_flush_data_cache_page;
  318. _dma_cache_wback_inv = tx39_dma_cache_wback_inv;
  319. _dma_cache_wback = tx39_dma_cache_wback_inv;
  320. _dma_cache_inv = tx39_dma_cache_inv;
  321. shm_align_mask = max_t(unsigned long,
  322. (dcache_size / current_cpu_data.dcache.ways) - 1,
  323. PAGE_SIZE - 1);
  324. break;
  325. }
  326. __flush_icache_user_range = flush_icache_range;
  327. __local_flush_icache_user_range = local_flush_icache_range;
  328. current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
  329. current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
  330. current_cpu_data.icache.sets =
  331. current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
  332. current_cpu_data.dcache.sets =
  333. current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
  334. if (current_cpu_data.dcache.waysize > PAGE_SIZE)
  335. current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
  336. current_cpu_data.icache.waybit = 0;
  337. current_cpu_data.dcache.waybit = 0;
  338. pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
  339. icache_size >> 10, current_cpu_data.icache.linesz);
  340. pr_info("Primary data cache %ldkB, linesize %d bytes\n",
  341. dcache_size >> 10, current_cpu_data.dcache.linesz);
  342. build_clear_page();
  343. build_copy_page();
  344. tx39h_flush_icache_all();
  345. }