setup.c 24 KB

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  1. /*
  2. * System-specific setup, especially interrupts.
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1998 Harald Koerfgen
  9. * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020 Maciej W. Rozycki
  10. */
  11. #include <linux/console.h>
  12. #include <linux/export.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/ioport.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqnr.h>
  18. #include <linux/memblock.h>
  19. #include <linux/param.h>
  20. #include <linux/percpu-defs.h>
  21. #include <linux/sched.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/types.h>
  24. #include <linux/pm.h>
  25. #include <asm/addrspace.h>
  26. #include <asm/bootinfo.h>
  27. #include <asm/cpu.h>
  28. #include <asm/cpu-features.h>
  29. #include <asm/cpu-type.h>
  30. #include <asm/irq.h>
  31. #include <asm/irq_cpu.h>
  32. #include <asm/mipsregs.h>
  33. #include <asm/page.h>
  34. #include <asm/reboot.h>
  35. #include <asm/sections.h>
  36. #include <asm/time.h>
  37. #include <asm/traps.h>
  38. #include <asm/wbflush.h>
  39. #include <asm/dec/interrupts.h>
  40. #include <asm/dec/ioasic.h>
  41. #include <asm/dec/ioasic_addrs.h>
  42. #include <asm/dec/ioasic_ints.h>
  43. #include <asm/dec/kn01.h>
  44. #include <asm/dec/kn02.h>
  45. #include <asm/dec/kn02ba.h>
  46. #include <asm/dec/kn02ca.h>
  47. #include <asm/dec/kn03.h>
  48. #include <asm/dec/kn230.h>
  49. #include <asm/dec/system.h>
  50. extern void dec_machine_restart(char *command);
  51. extern void dec_machine_halt(void);
  52. extern void dec_machine_power_off(void);
  53. extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
  54. unsigned long dec_kn_slot_base, dec_kn_slot_size;
  55. EXPORT_SYMBOL(dec_kn_slot_base);
  56. EXPORT_SYMBOL(dec_kn_slot_size);
  57. int dec_tc_bus;
  58. DEFINE_SPINLOCK(ioasic_ssr_lock);
  59. EXPORT_SYMBOL(ioasic_ssr_lock);
  60. volatile u32 *ioasic_base;
  61. EXPORT_SYMBOL(ioasic_base);
  62. /*
  63. * IRQ routing and priority tables. Priorites are set as follows:
  64. *
  65. * KN01 KN230 KN02 KN02-BA KN02-CA KN03
  66. *
  67. * MEMORY CPU CPU CPU ASIC CPU CPU
  68. * RTC CPU CPU CPU ASIC CPU CPU
  69. * DMA - - - ASIC ASIC ASIC
  70. * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
  71. * SERIAL1 - - - ASIC - ASIC
  72. * SCSI CPU CPU CSR ASIC ASIC ASIC
  73. * ETHERNET CPU * CSR ASIC ASIC ASIC
  74. * other - - - ASIC - -
  75. * TC2 - - CSR CPU ASIC ASIC
  76. * TC1 - - CSR CPU ASIC ASIC
  77. * TC0 - - CSR CPU ASIC ASIC
  78. * other - CPU - CPU ASIC ASIC
  79. * other - - - - CPU CPU
  80. *
  81. * * -- shared with SCSI
  82. */
  83. int dec_interrupt[DEC_NR_INTS] = {
  84. [0 ... DEC_NR_INTS - 1] = -1
  85. };
  86. EXPORT_SYMBOL(dec_interrupt);
  87. int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
  88. { { .i = ~0 }, { .p = dec_intr_unimplemented } },
  89. };
  90. int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
  91. { { .i = ~0 }, { .p = asic_intr_unimplemented } },
  92. };
  93. int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
  94. int *fpu_kstat_irq;
  95. static irq_handler_t busirq_handler;
  96. static unsigned int busirq_flags = IRQF_NO_THREAD;
  97. /*
  98. * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
  99. */
  100. static void __init dec_be_init(void)
  101. {
  102. switch (mips_machtype) {
  103. case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
  104. board_be_handler = dec_kn01_be_handler;
  105. busirq_handler = dec_kn01_be_interrupt;
  106. busirq_flags |= IRQF_SHARED;
  107. dec_kn01_be_init();
  108. break;
  109. case MACH_DS5000_1XX: /* DS5000/1xx 3min */
  110. case MACH_DS5000_XX: /* DS5000/xx Maxine */
  111. board_be_handler = dec_kn02xa_be_handler;
  112. busirq_handler = dec_kn02xa_be_interrupt;
  113. dec_kn02xa_be_init();
  114. break;
  115. case MACH_DS5000_200: /* DS5000/200 3max */
  116. case MACH_DS5000_2X0: /* DS5000/240 3max+ */
  117. case MACH_DS5900: /* DS5900 bigmax */
  118. board_be_handler = dec_ecc_be_handler;
  119. busirq_handler = dec_ecc_be_interrupt;
  120. dec_ecc_be_init();
  121. break;
  122. }
  123. }
  124. void __init plat_mem_setup(void)
  125. {
  126. board_be_init = dec_be_init;
  127. wbflush_setup();
  128. _machine_restart = dec_machine_restart;
  129. _machine_halt = dec_machine_halt;
  130. pm_power_off = dec_machine_power_off;
  131. ioport_resource.start = ~0UL;
  132. ioport_resource.end = 0UL;
  133. /* Stay away from the firmware working memory area for now. */
  134. memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET);
  135. }
  136. /*
  137. * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
  138. * or DS3100 (aka Pmax).
  139. */
  140. static int kn01_interrupt[DEC_NR_INTS] __initdata = {
  141. [DEC_IRQ_CASCADE] = -1,
  142. [DEC_IRQ_AB_RECV] = -1,
  143. [DEC_IRQ_AB_XMIT] = -1,
  144. [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
  145. [DEC_IRQ_ASC] = -1,
  146. [DEC_IRQ_FLOPPY] = -1,
  147. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  148. [DEC_IRQ_HALT] = -1,
  149. [DEC_IRQ_ISDN] = -1,
  150. [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
  151. [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
  152. [DEC_IRQ_PSU] = -1,
  153. [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
  154. [DEC_IRQ_SCC0] = -1,
  155. [DEC_IRQ_SCC1] = -1,
  156. [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
  157. [DEC_IRQ_TC0] = -1,
  158. [DEC_IRQ_TC1] = -1,
  159. [DEC_IRQ_TC2] = -1,
  160. [DEC_IRQ_TIMER] = -1,
  161. [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
  162. [DEC_IRQ_ASC_MERR] = -1,
  163. [DEC_IRQ_ASC_ERR] = -1,
  164. [DEC_IRQ_ASC_DMA] = -1,
  165. [DEC_IRQ_FLOPPY_ERR] = -1,
  166. [DEC_IRQ_ISDN_ERR] = -1,
  167. [DEC_IRQ_ISDN_RXDMA] = -1,
  168. [DEC_IRQ_ISDN_TXDMA] = -1,
  169. [DEC_IRQ_LANCE_MERR] = -1,
  170. [DEC_IRQ_SCC0A_RXERR] = -1,
  171. [DEC_IRQ_SCC0A_RXDMA] = -1,
  172. [DEC_IRQ_SCC0A_TXERR] = -1,
  173. [DEC_IRQ_SCC0A_TXDMA] = -1,
  174. [DEC_IRQ_AB_RXERR] = -1,
  175. [DEC_IRQ_AB_RXDMA] = -1,
  176. [DEC_IRQ_AB_TXERR] = -1,
  177. [DEC_IRQ_AB_TXDMA] = -1,
  178. [DEC_IRQ_SCC1A_RXERR] = -1,
  179. [DEC_IRQ_SCC1A_RXDMA] = -1,
  180. [DEC_IRQ_SCC1A_TXERR] = -1,
  181. [DEC_IRQ_SCC1A_TXDMA] = -1,
  182. };
  183. static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
  184. { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
  185. { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
  186. { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
  187. { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
  188. { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
  189. { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
  190. { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
  191. { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
  192. { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
  193. { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
  194. { { .i = DEC_CPU_IRQ_ALL },
  195. { .p = cpu_all_int } },
  196. };
  197. static void __init dec_init_kn01(void)
  198. {
  199. /* IRQ routing. */
  200. memcpy(&dec_interrupt, &kn01_interrupt,
  201. sizeof(kn01_interrupt));
  202. /* CPU IRQ priorities. */
  203. memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
  204. sizeof(kn01_cpu_mask_nr_tbl));
  205. mips_cpu_irq_init();
  206. } /* dec_init_kn01 */
  207. /*
  208. * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
  209. */
  210. static int kn230_interrupt[DEC_NR_INTS] __initdata = {
  211. [DEC_IRQ_CASCADE] = -1,
  212. [DEC_IRQ_AB_RECV] = -1,
  213. [DEC_IRQ_AB_XMIT] = -1,
  214. [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
  215. [DEC_IRQ_ASC] = -1,
  216. [DEC_IRQ_FLOPPY] = -1,
  217. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  218. [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
  219. [DEC_IRQ_ISDN] = -1,
  220. [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
  221. [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
  222. [DEC_IRQ_PSU] = -1,
  223. [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
  224. [DEC_IRQ_SCC0] = -1,
  225. [DEC_IRQ_SCC1] = -1,
  226. [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
  227. [DEC_IRQ_TC0] = -1,
  228. [DEC_IRQ_TC1] = -1,
  229. [DEC_IRQ_TC2] = -1,
  230. [DEC_IRQ_TIMER] = -1,
  231. [DEC_IRQ_VIDEO] = -1,
  232. [DEC_IRQ_ASC_MERR] = -1,
  233. [DEC_IRQ_ASC_ERR] = -1,
  234. [DEC_IRQ_ASC_DMA] = -1,
  235. [DEC_IRQ_FLOPPY_ERR] = -1,
  236. [DEC_IRQ_ISDN_ERR] = -1,
  237. [DEC_IRQ_ISDN_RXDMA] = -1,
  238. [DEC_IRQ_ISDN_TXDMA] = -1,
  239. [DEC_IRQ_LANCE_MERR] = -1,
  240. [DEC_IRQ_SCC0A_RXERR] = -1,
  241. [DEC_IRQ_SCC0A_RXDMA] = -1,
  242. [DEC_IRQ_SCC0A_TXERR] = -1,
  243. [DEC_IRQ_SCC0A_TXDMA] = -1,
  244. [DEC_IRQ_AB_RXERR] = -1,
  245. [DEC_IRQ_AB_RXDMA] = -1,
  246. [DEC_IRQ_AB_TXERR] = -1,
  247. [DEC_IRQ_AB_TXDMA] = -1,
  248. [DEC_IRQ_SCC1A_RXERR] = -1,
  249. [DEC_IRQ_SCC1A_RXDMA] = -1,
  250. [DEC_IRQ_SCC1A_TXERR] = -1,
  251. [DEC_IRQ_SCC1A_TXDMA] = -1,
  252. };
  253. static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
  254. { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
  255. { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
  256. { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
  257. { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
  258. { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
  259. { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
  260. { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
  261. { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
  262. { { .i = DEC_CPU_IRQ_ALL },
  263. { .p = cpu_all_int } },
  264. };
  265. static void __init dec_init_kn230(void)
  266. {
  267. /* IRQ routing. */
  268. memcpy(&dec_interrupt, &kn230_interrupt,
  269. sizeof(kn230_interrupt));
  270. /* CPU IRQ priorities. */
  271. memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
  272. sizeof(kn230_cpu_mask_nr_tbl));
  273. mips_cpu_irq_init();
  274. } /* dec_init_kn230 */
  275. /*
  276. * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
  277. */
  278. static int kn02_interrupt[DEC_NR_INTS] __initdata = {
  279. [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
  280. [DEC_IRQ_AB_RECV] = -1,
  281. [DEC_IRQ_AB_XMIT] = -1,
  282. [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
  283. [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
  284. [DEC_IRQ_FLOPPY] = -1,
  285. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  286. [DEC_IRQ_HALT] = -1,
  287. [DEC_IRQ_ISDN] = -1,
  288. [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
  289. [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
  290. [DEC_IRQ_PSU] = -1,
  291. [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
  292. [DEC_IRQ_SCC0] = -1,
  293. [DEC_IRQ_SCC1] = -1,
  294. [DEC_IRQ_SII] = -1,
  295. [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
  296. [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
  297. [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
  298. [DEC_IRQ_TIMER] = -1,
  299. [DEC_IRQ_VIDEO] = -1,
  300. [DEC_IRQ_ASC_MERR] = -1,
  301. [DEC_IRQ_ASC_ERR] = -1,
  302. [DEC_IRQ_ASC_DMA] = -1,
  303. [DEC_IRQ_FLOPPY_ERR] = -1,
  304. [DEC_IRQ_ISDN_ERR] = -1,
  305. [DEC_IRQ_ISDN_RXDMA] = -1,
  306. [DEC_IRQ_ISDN_TXDMA] = -1,
  307. [DEC_IRQ_LANCE_MERR] = -1,
  308. [DEC_IRQ_SCC0A_RXERR] = -1,
  309. [DEC_IRQ_SCC0A_RXDMA] = -1,
  310. [DEC_IRQ_SCC0A_TXERR] = -1,
  311. [DEC_IRQ_SCC0A_TXDMA] = -1,
  312. [DEC_IRQ_AB_RXERR] = -1,
  313. [DEC_IRQ_AB_RXDMA] = -1,
  314. [DEC_IRQ_AB_TXERR] = -1,
  315. [DEC_IRQ_AB_TXDMA] = -1,
  316. [DEC_IRQ_SCC1A_RXERR] = -1,
  317. [DEC_IRQ_SCC1A_RXDMA] = -1,
  318. [DEC_IRQ_SCC1A_TXERR] = -1,
  319. [DEC_IRQ_SCC1A_TXDMA] = -1,
  320. };
  321. static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
  322. { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
  323. { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
  324. { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
  325. { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
  326. { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
  327. { .p = kn02_io_int } },
  328. { { .i = DEC_CPU_IRQ_ALL },
  329. { .p = cpu_all_int } },
  330. };
  331. static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
  332. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
  333. { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
  334. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
  335. { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
  336. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
  337. { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
  338. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
  339. { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
  340. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
  341. { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
  342. { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
  343. { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
  344. { { .i = KN02_IRQ_ALL },
  345. { .p = kn02_all_int } },
  346. };
  347. static void __init dec_init_kn02(void)
  348. {
  349. /* IRQ routing. */
  350. memcpy(&dec_interrupt, &kn02_interrupt,
  351. sizeof(kn02_interrupt));
  352. /* CPU IRQ priorities. */
  353. memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
  354. sizeof(kn02_cpu_mask_nr_tbl));
  355. /* KN02 CSR IRQ priorities. */
  356. memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
  357. sizeof(kn02_asic_mask_nr_tbl));
  358. mips_cpu_irq_init();
  359. init_kn02_irqs(KN02_IRQ_BASE);
  360. } /* dec_init_kn02 */
  361. /*
  362. * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
  363. * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
  364. * DS5000/150, aka 4min.
  365. */
  366. static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
  367. [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
  368. [DEC_IRQ_AB_RECV] = -1,
  369. [DEC_IRQ_AB_XMIT] = -1,
  370. [DEC_IRQ_DZ11] = -1,
  371. [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
  372. [DEC_IRQ_FLOPPY] = -1,
  373. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  374. [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
  375. [DEC_IRQ_ISDN] = -1,
  376. [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
  377. [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
  378. [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
  379. [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
  380. [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
  381. [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
  382. [DEC_IRQ_SII] = -1,
  383. [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
  384. [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
  385. [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
  386. [DEC_IRQ_TIMER] = -1,
  387. [DEC_IRQ_VIDEO] = -1,
  388. [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
  389. [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
  390. [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
  391. [DEC_IRQ_FLOPPY_ERR] = -1,
  392. [DEC_IRQ_ISDN_ERR] = -1,
  393. [DEC_IRQ_ISDN_RXDMA] = -1,
  394. [DEC_IRQ_ISDN_TXDMA] = -1,
  395. [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
  396. [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
  397. [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
  398. [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
  399. [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
  400. [DEC_IRQ_AB_RXERR] = -1,
  401. [DEC_IRQ_AB_RXDMA] = -1,
  402. [DEC_IRQ_AB_TXERR] = -1,
  403. [DEC_IRQ_AB_TXDMA] = -1,
  404. [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
  405. [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
  406. [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
  407. [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
  408. };
  409. static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
  410. { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
  411. { .p = kn02xa_io_int } },
  412. { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
  413. { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
  414. { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
  415. { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
  416. { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
  417. { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
  418. { { .i = DEC_CPU_IRQ_ALL },
  419. { .p = cpu_all_int } },
  420. };
  421. static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
  422. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
  423. { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
  424. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
  425. { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
  426. { { .i = IO_IRQ_DMA },
  427. { .p = asic_dma_int } },
  428. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
  429. { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
  430. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
  431. { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
  432. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
  433. { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
  434. { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
  435. { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
  436. { { .i = IO_IRQ_ALL },
  437. { .p = asic_all_int } },
  438. };
  439. static void __init dec_init_kn02ba(void)
  440. {
  441. /* IRQ routing. */
  442. memcpy(&dec_interrupt, &kn02ba_interrupt,
  443. sizeof(kn02ba_interrupt));
  444. /* CPU IRQ priorities. */
  445. memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
  446. sizeof(kn02ba_cpu_mask_nr_tbl));
  447. /* I/O ASIC IRQ priorities. */
  448. memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
  449. sizeof(kn02ba_asic_mask_nr_tbl));
  450. mips_cpu_irq_init();
  451. init_ioasic_irqs(IO_IRQ_BASE);
  452. } /* dec_init_kn02ba */
  453. /*
  454. * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
  455. * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
  456. * DS5000/50, aka 4MAXine.
  457. */
  458. static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
  459. [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
  460. [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
  461. [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
  462. [DEC_IRQ_DZ11] = -1,
  463. [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
  464. [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
  465. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  466. [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
  467. [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
  468. [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
  469. [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
  470. [DEC_IRQ_PSU] = -1,
  471. [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
  472. [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
  473. [DEC_IRQ_SCC1] = -1,
  474. [DEC_IRQ_SII] = -1,
  475. [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
  476. [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
  477. [DEC_IRQ_TC2] = -1,
  478. [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
  479. [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
  480. [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
  481. [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
  482. [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
  483. [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
  484. [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
  485. [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
  486. [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
  487. [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
  488. [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
  489. [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
  490. [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
  491. [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
  492. [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
  493. [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
  494. [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
  495. [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
  496. [DEC_IRQ_SCC1A_RXERR] = -1,
  497. [DEC_IRQ_SCC1A_RXDMA] = -1,
  498. [DEC_IRQ_SCC1A_TXERR] = -1,
  499. [DEC_IRQ_SCC1A_TXDMA] = -1,
  500. };
  501. static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
  502. { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
  503. { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
  504. { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
  505. { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
  506. { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
  507. { .p = kn02xa_io_int } },
  508. { { .i = DEC_CPU_IRQ_ALL },
  509. { .p = cpu_all_int } },
  510. };
  511. static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
  512. { { .i = IO_IRQ_DMA },
  513. { .p = asic_dma_int } },
  514. { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
  515. { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
  516. { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
  517. { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
  518. { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
  519. { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
  520. { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
  521. { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
  522. { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
  523. { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
  524. { { .i = IO_IRQ_ALL },
  525. { .p = asic_all_int } },
  526. };
  527. static void __init dec_init_kn02ca(void)
  528. {
  529. /* IRQ routing. */
  530. memcpy(&dec_interrupt, &kn02ca_interrupt,
  531. sizeof(kn02ca_interrupt));
  532. /* CPU IRQ priorities. */
  533. memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
  534. sizeof(kn02ca_cpu_mask_nr_tbl));
  535. /* I/O ASIC IRQ priorities. */
  536. memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
  537. sizeof(kn02ca_asic_mask_nr_tbl));
  538. mips_cpu_irq_init();
  539. init_ioasic_irqs(IO_IRQ_BASE);
  540. } /* dec_init_kn02ca */
  541. /*
  542. * Machine-specific initialisation for KN03, aka DS5000/240,
  543. * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
  544. * DS5000/260, aka 4max+ and DS5900/260.
  545. */
  546. static int kn03_interrupt[DEC_NR_INTS] __initdata = {
  547. [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
  548. [DEC_IRQ_AB_RECV] = -1,
  549. [DEC_IRQ_AB_XMIT] = -1,
  550. [DEC_IRQ_DZ11] = -1,
  551. [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
  552. [DEC_IRQ_FLOPPY] = -1,
  553. [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
  554. [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
  555. [DEC_IRQ_ISDN] = -1,
  556. [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
  557. [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
  558. [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
  559. [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
  560. [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
  561. [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
  562. [DEC_IRQ_SII] = -1,
  563. [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
  564. [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
  565. [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
  566. [DEC_IRQ_TIMER] = -1,
  567. [DEC_IRQ_VIDEO] = -1,
  568. [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
  569. [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
  570. [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
  571. [DEC_IRQ_FLOPPY_ERR] = -1,
  572. [DEC_IRQ_ISDN_ERR] = -1,
  573. [DEC_IRQ_ISDN_RXDMA] = -1,
  574. [DEC_IRQ_ISDN_TXDMA] = -1,
  575. [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
  576. [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
  577. [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
  578. [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
  579. [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
  580. [DEC_IRQ_AB_RXERR] = -1,
  581. [DEC_IRQ_AB_RXDMA] = -1,
  582. [DEC_IRQ_AB_TXERR] = -1,
  583. [DEC_IRQ_AB_TXDMA] = -1,
  584. [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
  585. [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
  586. [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
  587. [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
  588. };
  589. static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
  590. { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
  591. { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
  592. { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
  593. { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
  594. { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
  595. { .p = kn03_io_int } },
  596. { { .i = DEC_CPU_IRQ_ALL },
  597. { .p = cpu_all_int } },
  598. };
  599. static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
  600. { { .i = IO_IRQ_DMA },
  601. { .p = asic_dma_int } },
  602. { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
  603. { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
  604. { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
  605. { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
  606. { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
  607. { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
  608. { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
  609. { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
  610. { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
  611. { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
  612. { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
  613. { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
  614. { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
  615. { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
  616. { { .i = IO_IRQ_ALL },
  617. { .p = asic_all_int } },
  618. };
  619. static void __init dec_init_kn03(void)
  620. {
  621. /* IRQ routing. */
  622. memcpy(&dec_interrupt, &kn03_interrupt,
  623. sizeof(kn03_interrupt));
  624. /* CPU IRQ priorities. */
  625. memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
  626. sizeof(kn03_cpu_mask_nr_tbl));
  627. /* I/O ASIC IRQ priorities. */
  628. memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
  629. sizeof(kn03_asic_mask_nr_tbl));
  630. mips_cpu_irq_init();
  631. init_ioasic_irqs(IO_IRQ_BASE);
  632. } /* dec_init_kn03 */
  633. void __init arch_init_irq(void)
  634. {
  635. switch (mips_machtype) {
  636. case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
  637. dec_init_kn01();
  638. break;
  639. case MACH_DS5100: /* DS5100 MIPSmate */
  640. dec_init_kn230();
  641. break;
  642. case MACH_DS5000_200: /* DS5000/200 3max */
  643. dec_init_kn02();
  644. break;
  645. case MACH_DS5000_1XX: /* DS5000/1xx 3min */
  646. dec_init_kn02ba();
  647. break;
  648. case MACH_DS5000_2X0: /* DS5000/240 3max+ */
  649. case MACH_DS5900: /* DS5900 bigmax */
  650. dec_init_kn03();
  651. break;
  652. case MACH_DS5000_XX: /* Personal DS5000/xx */
  653. dec_init_kn02ca();
  654. break;
  655. case MACH_DS5800: /* DS5800 Isis */
  656. panic("Don't know how to set this up!");
  657. break;
  658. case MACH_DS5400: /* DS5400 MIPSfair */
  659. panic("Don't know how to set this up!");
  660. break;
  661. case MACH_DS5500: /* DS5500 MIPSfair-2 */
  662. panic("Don't know how to set this up!");
  663. break;
  664. }
  665. /* Free the FPU interrupt if the exception is present. */
  666. if (!cpu_has_nofpuex) {
  667. cpu_fpu_mask = 0;
  668. dec_interrupt[DEC_IRQ_FPU] = -1;
  669. }
  670. /* Free the halt interrupt unused on R4k systems. */
  671. if (current_cpu_type() == CPU_R4000SC ||
  672. current_cpu_type() == CPU_R4400SC)
  673. dec_interrupt[DEC_IRQ_HALT] = -1;
  674. /* Register board interrupts: FPU and cascade. */
  675. if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) &&
  676. dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
  677. struct irq_desc *desc_fpu;
  678. int irq_fpu;
  679. irq_fpu = dec_interrupt[DEC_IRQ_FPU];
  680. if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu",
  681. NULL))
  682. pr_err("Failed to register fpu interrupt\n");
  683. desc_fpu = irq_to_desc(irq_fpu);
  684. fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
  685. }
  686. if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) {
  687. if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action,
  688. IRQF_NO_THREAD, "cascade", NULL))
  689. pr_err("Failed to register cascade interrupt\n");
  690. }
  691. /* Register the bus error interrupt. */
  692. if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) {
  693. if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler,
  694. busirq_flags, "bus error", busirq_handler))
  695. pr_err("Failed to register bus error interrupt\n");
  696. }
  697. /* Register the HALT interrupt. */
  698. if (dec_interrupt[DEC_IRQ_HALT] >= 0) {
  699. if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt,
  700. IRQF_NO_THREAD, "halt", NULL))
  701. pr_err("Failed to register halt interrupt\n");
  702. }
  703. }
  704. asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
  705. {
  706. do_IRQ(irq);
  707. return 0;
  708. }