kn01-berr.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Bus error event handling code for DECstation/DECsystem 3100
  4. * and 2100 (KN01) systems equipped with parity error detection
  5. * logic.
  6. *
  7. * Copyright (c) 2005 Maciej W. Rozycki
  8. */
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/types.h>
  14. #include <asm/inst.h>
  15. #include <asm/irq_regs.h>
  16. #include <asm/mipsregs.h>
  17. #include <asm/page.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/traps.h>
  20. #include <linux/uaccess.h>
  21. #include <asm/dec/kn01.h>
  22. /* CP0 hazard avoidance. */
  23. #define BARRIER \
  24. __asm__ __volatile__( \
  25. ".set push\n\t" \
  26. ".set noreorder\n\t" \
  27. "nop\n\t" \
  28. ".set pop\n\t")
  29. /*
  30. * Bits 7:0 of the Control Register are write-only -- the
  31. * corresponding bits of the Status Register have a different
  32. * meaning. Hence we use a cache. It speeds up things a bit
  33. * as well.
  34. *
  35. * There is no default value -- it has to be initialized.
  36. */
  37. u16 cached_kn01_csr;
  38. static DEFINE_RAW_SPINLOCK(kn01_lock);
  39. static inline void dec_kn01_be_ack(void)
  40. {
  41. volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
  42. unsigned long flags;
  43. raw_spin_lock_irqsave(&kn01_lock, flags);
  44. *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
  45. iob();
  46. raw_spin_unlock_irqrestore(&kn01_lock, flags);
  47. }
  48. static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
  49. {
  50. volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
  51. KN01_ERRADDR);
  52. static const char excstr[] = "exception";
  53. static const char intstr[] = "interrupt";
  54. static const char cpustr[] = "CPU";
  55. static const char mreadstr[] = "memory read";
  56. static const char readstr[] = "read";
  57. static const char writestr[] = "write";
  58. static const char timestr[] = "timeout";
  59. static const char paritystr[] = "parity error";
  60. int data = regs->cp0_cause & 4;
  61. unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
  62. ((regs->cp0_cause & CAUSEF_BD) != 0);
  63. union mips_instruction insn;
  64. unsigned long entrylo, offset;
  65. long asid, entryhi, vaddr;
  66. const char *kind, *agent, *cycle, *event;
  67. unsigned long address;
  68. u32 erraddr = *kn01_erraddr;
  69. int action = MIPS_BE_FATAL;
  70. /* Ack ASAP, so that any subsequent errors get caught. */
  71. dec_kn01_be_ack();
  72. kind = invoker ? intstr : excstr;
  73. agent = cpustr;
  74. if (invoker)
  75. address = erraddr;
  76. else {
  77. /* Bloody hardware doesn't record the address for reads... */
  78. if (data) {
  79. /* This never faults. */
  80. __get_user(insn.word, pc);
  81. vaddr = regs->regs[insn.i_format.rs] +
  82. insn.i_format.simmediate;
  83. } else
  84. vaddr = (long)pc;
  85. if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
  86. address = CPHYSADDR(vaddr);
  87. else {
  88. /* Peek at what physical address the CPU used. */
  89. asid = read_c0_entryhi();
  90. entryhi = asid & (PAGE_SIZE - 1);
  91. entryhi |= vaddr & ~(PAGE_SIZE - 1);
  92. write_c0_entryhi(entryhi);
  93. BARRIER;
  94. tlb_probe();
  95. /* No need to check for presence. */
  96. tlb_read();
  97. entrylo = read_c0_entrylo0();
  98. write_c0_entryhi(asid);
  99. offset = vaddr & (PAGE_SIZE - 1);
  100. address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
  101. }
  102. }
  103. /* Treat low 256MB as memory, high -- as I/O. */
  104. if (address < 0x10000000) {
  105. cycle = mreadstr;
  106. event = paritystr;
  107. } else {
  108. cycle = invoker ? writestr : readstr;
  109. event = timestr;
  110. }
  111. if (is_fixup)
  112. action = MIPS_BE_FIXUP;
  113. if (action != MIPS_BE_FIXUP)
  114. printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
  115. kind, agent, cycle, event, address);
  116. return action;
  117. }
  118. int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
  119. {
  120. return dec_kn01_be_backend(regs, is_fixup, 0);
  121. }
  122. irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id)
  123. {
  124. volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
  125. struct pt_regs *regs = get_irq_regs();
  126. int action;
  127. if (!(*csr & KN01_CSR_MEMERR))
  128. return IRQ_NONE; /* Must have been video. */
  129. action = dec_kn01_be_backend(regs, 0, 1);
  130. if (action == MIPS_BE_DISCARD)
  131. return IRQ_HANDLED;
  132. /*
  133. * FIXME: Find the affected processes and kill them, otherwise
  134. * we must die.
  135. *
  136. * The interrupt is asynchronously delivered thus EPC and RA
  137. * may be irrelevant, but are printed for a reference.
  138. */
  139. printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
  140. regs->cp0_epc, regs->regs[31]);
  141. die("Unrecoverable bus error", regs);
  142. }
  143. void __init dec_kn01_be_init(void)
  144. {
  145. volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
  146. unsigned long flags;
  147. raw_spin_lock_irqsave(&kn01_lock, flags);
  148. /* Preset write-only bits of the Control Register cache. */
  149. cached_kn01_csr = *csr;
  150. cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
  151. cached_kn01_csr |= KN01_CSR_LEDS;
  152. /* Enable parity error detection. */
  153. cached_kn01_csr &= ~KN01_CSR_PARDIS;
  154. *csr = cached_kn01_csr;
  155. iob();
  156. raw_spin_unlock_irqrestore(&kn01_lock, flags);
  157. /* Clear any leftover errors from the firmware. */
  158. dec_kn01_be_ack();
  159. }