ioasic-irq.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DEC I/O ASIC interrupts.
  4. *
  5. * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki
  6. */
  7. #include <linux/init.h>
  8. #include <linux/irq.h>
  9. #include <linux/types.h>
  10. #include <asm/dec/ioasic.h>
  11. #include <asm/dec/ioasic_addrs.h>
  12. #include <asm/dec/ioasic_ints.h>
  13. static int ioasic_irq_base;
  14. static void unmask_ioasic_irq(struct irq_data *d)
  15. {
  16. u32 simr;
  17. simr = ioasic_read(IO_REG_SIMR);
  18. simr |= (1 << (d->irq - ioasic_irq_base));
  19. ioasic_write(IO_REG_SIMR, simr);
  20. }
  21. static void mask_ioasic_irq(struct irq_data *d)
  22. {
  23. u32 simr;
  24. simr = ioasic_read(IO_REG_SIMR);
  25. simr &= ~(1 << (d->irq - ioasic_irq_base));
  26. ioasic_write(IO_REG_SIMR, simr);
  27. }
  28. static void ack_ioasic_irq(struct irq_data *d)
  29. {
  30. mask_ioasic_irq(d);
  31. fast_iob();
  32. }
  33. static struct irq_chip ioasic_irq_type = {
  34. .name = "IO-ASIC",
  35. .irq_ack = ack_ioasic_irq,
  36. .irq_mask = mask_ioasic_irq,
  37. .irq_mask_ack = ack_ioasic_irq,
  38. .irq_unmask = unmask_ioasic_irq,
  39. };
  40. static void clear_ioasic_dma_irq(struct irq_data *d)
  41. {
  42. u32 sir;
  43. sir = ~(1 << (d->irq - ioasic_irq_base));
  44. ioasic_write(IO_REG_SIR, sir);
  45. fast_iob();
  46. }
  47. static struct irq_chip ioasic_dma_irq_type = {
  48. .name = "IO-ASIC-DMA",
  49. .irq_ack = clear_ioasic_dma_irq,
  50. .irq_mask = mask_ioasic_irq,
  51. .irq_unmask = unmask_ioasic_irq,
  52. .irq_eoi = clear_ioasic_dma_irq,
  53. };
  54. /*
  55. * I/O ASIC implements two kinds of DMA interrupts, informational and
  56. * error interrupts.
  57. *
  58. * The formers do not stop DMA and should be cleared as soon as possible
  59. * so that if they retrigger before the handler has completed, usually as
  60. * a side effect of actions taken by the handler, then they are reissued.
  61. * These use the `handle_edge_irq' handler that clears the request right
  62. * away.
  63. *
  64. * The latters stop DMA and do not resume it until the interrupt has been
  65. * cleared. This cannot be done until after a corrective action has been
  66. * taken and this also means they will not retrigger. Therefore they use
  67. * the `handle_fasteoi_irq' handler that only clears the request on the
  68. * way out. Because MIPS processor interrupt inputs, one of which the I/O
  69. * ASIC is cascaded to, are level-triggered it is recommended that error
  70. * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
  71. * set so that they are run with the interrupt line masked.
  72. *
  73. * This mask has `1' bits in the positions of informational interrupts.
  74. */
  75. #define IO_IRQ_DMA_INFO \
  76. (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \
  77. IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \
  78. IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \
  79. IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \
  80. IO_IRQ_MASK(IO_INR_ASC_DMA))
  81. void __init init_ioasic_irqs(int base)
  82. {
  83. int i;
  84. /* Mask interrupts. */
  85. ioasic_write(IO_REG_SIMR, 0);
  86. fast_iob();
  87. for (i = base; i < base + IO_INR_DMA; i++)
  88. irq_set_chip_and_handler(i, &ioasic_irq_type,
  89. handle_level_irq);
  90. for (; i < base + IO_IRQ_LINES; i++)
  91. irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
  92. 1 << (i - base) & IO_IRQ_DMA_INFO ?
  93. handle_edge_irq : handle_fasteoi_irq);
  94. ioasic_irq_base = base;
  95. }