int-handler.S 7.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
  4. * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
  5. *
  6. * Written by Ralf Baechle and Andreas Busse, modified for DECstation
  7. * support by Paul Antoine and Harald Koerfgen.
  8. *
  9. * completely rewritten:
  10. * Copyright (C) 1998 Harald Koerfgen
  11. *
  12. * Rewritten extensively for controller-driven IRQ support
  13. * by Maciej W. Rozycki.
  14. */
  15. #include <asm/addrspace.h>
  16. #include <asm/asm.h>
  17. #include <asm/mipsregs.h>
  18. #include <asm/regdef.h>
  19. #include <asm/stackframe.h>
  20. #include <asm/dec/interrupts.h>
  21. #include <asm/dec/ioasic_addrs.h>
  22. #include <asm/dec/ioasic_ints.h>
  23. #include <asm/dec/kn01.h>
  24. #include <asm/dec/kn02.h>
  25. #include <asm/dec/kn02xa.h>
  26. #include <asm/dec/kn03.h>
  27. #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
  28. #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
  29. #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
  30. .text
  31. .set noreorder
  32. /*
  33. * plat_irq_dispatch: Interrupt handler for DECstations
  34. *
  35. * We follow the model in the Indy interrupt code by David Miller, where he
  36. * says: a lot of complication here is taken away because:
  37. *
  38. * 1) We handle one interrupt and return, sitting in a loop
  39. * and moving across all the pending IRQ bits in the cause
  40. * register is _NOT_ the answer, the common case is one
  41. * pending IRQ so optimize in that direction.
  42. *
  43. * 2) We need not check against bits in the status register
  44. * IRQ mask, that would make this routine slow as hell.
  45. *
  46. * 3) Linux only thinks in terms of all IRQs on or all IRQs
  47. * off, nothing in between like BSD spl() brain-damage.
  48. *
  49. * Furthermore, the IRQs on the DECstations look basically (barring
  50. * software IRQs which we don't use at all) like...
  51. *
  52. * DS2100/3100's, aka kn01, aka Pmax:
  53. *
  54. * MIPS IRQ Source
  55. * -------- ------
  56. * 0 Software (ignored)
  57. * 1 Software (ignored)
  58. * 2 SCSI
  59. * 3 Lance Ethernet
  60. * 4 DZ11 serial
  61. * 5 RTC
  62. * 6 Memory Controller & Video
  63. * 7 FPU
  64. *
  65. * DS5000/200, aka kn02, aka 3max:
  66. *
  67. * MIPS IRQ Source
  68. * -------- ------
  69. * 0 Software (ignored)
  70. * 1 Software (ignored)
  71. * 2 TurboChannel
  72. * 3 RTC
  73. * 4 Reserved
  74. * 5 Memory Controller
  75. * 6 Reserved
  76. * 7 FPU
  77. *
  78. * DS5000/1xx's, aka kn02ba, aka 3min:
  79. *
  80. * MIPS IRQ Source
  81. * -------- ------
  82. * 0 Software (ignored)
  83. * 1 Software (ignored)
  84. * 2 TurboChannel Slot 0
  85. * 3 TurboChannel Slot 1
  86. * 4 TurboChannel Slot 2
  87. * 5 TurboChannel Slot 3 (ASIC)
  88. * 6 Halt button
  89. * 7 FPU/R4k timer
  90. *
  91. * DS5000/2x's, aka kn02ca, aka maxine:
  92. *
  93. * MIPS IRQ Source
  94. * -------- ------
  95. * 0 Software (ignored)
  96. * 1 Software (ignored)
  97. * 2 Periodic Interrupt (100usec)
  98. * 3 RTC
  99. * 4 I/O write timeout
  100. * 5 TurboChannel (ASIC)
  101. * 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER)
  102. * 7 FPU/R4k timer
  103. *
  104. * DS5000/2xx's, aka kn03, aka 3maxplus:
  105. *
  106. * MIPS IRQ Source
  107. * -------- ------
  108. * 0 Software (ignored)
  109. * 1 Software (ignored)
  110. * 2 System Board (ASIC)
  111. * 3 RTC
  112. * 4 Reserved
  113. * 5 Memory
  114. * 6 Halt Button
  115. * 7 FPU/R4k timer
  116. *
  117. * We handle the IRQ according to _our_ priority (see setup.c),
  118. * then we just return. If multiple IRQs are pending then we will
  119. * just take another exception, big deal.
  120. */
  121. .align 5
  122. NESTED(plat_irq_dispatch, PT_SIZE, ra)
  123. .set noreorder
  124. /*
  125. * Get pending Interrupts
  126. */
  127. mfc0 t0,CP0_CAUSE # get pending interrupts
  128. mfc0 t1,CP0_STATUS
  129. #if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
  130. lw t2,cpu_fpu_mask
  131. #endif
  132. andi t0,ST0_IM # CAUSE.CE may be non-zero!
  133. and t0,t1 # isolate allowed ones
  134. beqz t0,spurious
  135. #if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
  136. and t2,t0
  137. bnez t2,fpu # handle FPU immediately
  138. #endif
  139. /*
  140. * Find irq with highest priority
  141. */
  142. # open coded PTR_LA t1, cpu_mask_nr_tbl
  143. #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
  144. # open coded la t1, cpu_mask_nr_tbl
  145. lui t1, %hi(cpu_mask_nr_tbl)
  146. addiu t1, %lo(cpu_mask_nr_tbl)
  147. #else
  148. #error GCC `-msym32' option required for 64-bit DECstation builds
  149. #endif
  150. 1: lw t2,(t1)
  151. nop
  152. and t2,t0
  153. beqz t2,1b
  154. addu t1,2*PTRSIZE # delay slot
  155. /*
  156. * Do the low-level stuff
  157. */
  158. lw a0,(-PTRSIZE)(t1)
  159. nop
  160. bgez a0,handle_it # irq_nr >= 0?
  161. # irq_nr < 0: it is an address
  162. nop
  163. jr a0
  164. # a trick to save a branch:
  165. lui t2,(KN03_IOASIC_BASE>>16)&0xffff
  166. # upper part of IOASIC Address
  167. /*
  168. * Handle "IRQ Controller" Interrupts
  169. * Masked Interrupts are still visible and have to be masked "by hand".
  170. */
  171. FEXPORT(kn02_io_int) # 3max
  172. lui t0,(KN02_CSR_BASE>>16)&0xffff
  173. # get interrupt status and mask
  174. lw t0,(t0)
  175. nop
  176. andi t1,t0,KN02_IRQ_ALL
  177. b 1f
  178. srl t0,16 # shift interrupt mask
  179. FEXPORT(kn02xa_io_int) # 3min/maxine
  180. lui t2,(KN02XA_IOASIC_BASE>>16)&0xffff
  181. # upper part of IOASIC Address
  182. FEXPORT(kn03_io_int) # 3max+ (t2 loaded earlier)
  183. lw t0,IO_REG_SIR(t2) # get status: IOASIC sir
  184. lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr
  185. nop
  186. 1: and t0,t1 # mask out allowed ones
  187. beqz t0,spurious
  188. /*
  189. * Find irq with highest priority
  190. */
  191. # open coded PTR_LA t1,asic_mask_nr_tbl
  192. #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
  193. # open coded la t1, asic_mask_nr_tbl
  194. lui t1, %hi(asic_mask_nr_tbl)
  195. addiu t1, %lo(asic_mask_nr_tbl)
  196. #else
  197. #error GCC `-msym32' option required for 64-bit DECstation builds
  198. #endif
  199. 2: lw t2,(t1)
  200. nop
  201. and t2,t0
  202. beq zero,t2,2b
  203. addu t1,2*PTRSIZE # delay slot
  204. /*
  205. * Do the low-level stuff
  206. */
  207. lw a0,%lo(-PTRSIZE)(t1)
  208. nop
  209. bgez a0,handle_it # irq_nr >= 0?
  210. # irq_nr < 0: it is an address
  211. nop
  212. jr a0
  213. nop # delay slot
  214. /*
  215. * Dispatch low-priority interrupts. We reconsider all status
  216. * bits again, which looks like a lose, but it makes the code
  217. * simple and O(log n), so it gets compensated.
  218. */
  219. FEXPORT(cpu_all_int) # HALT, timers, software junk
  220. li a0,DEC_CPU_IRQ_BASE
  221. srl t0,CAUSEB_IP
  222. li t1,CAUSEF_IP>>CAUSEB_IP # mask
  223. b 1f
  224. li t2,4 # nr of bits / 2
  225. FEXPORT(kn02_all_int) # impossible ?
  226. li a0,KN02_IRQ_BASE
  227. li t1,KN02_IRQ_ALL # mask
  228. b 1f
  229. li t2,4 # nr of bits / 2
  230. FEXPORT(asic_all_int) # various I/O ASIC junk
  231. li a0,IO_IRQ_BASE
  232. li t1,IO_IRQ_ALL # mask
  233. b 1f
  234. li t2,8 # nr of bits / 2
  235. /*
  236. * Dispatch DMA interrupts -- O(log n).
  237. */
  238. FEXPORT(asic_dma_int) # I/O ASIC DMA events
  239. li a0,IO_IRQ_BASE+IO_INR_DMA
  240. srl t0,IO_INR_DMA
  241. li t1,IO_IRQ_DMA>>IO_INR_DMA # mask
  242. li t2,8 # nr of bits / 2
  243. /*
  244. * Find irq with highest priority.
  245. * Highest irq number takes precedence.
  246. */
  247. 1: srlv t3,t1,t2
  248. 2: xor t1,t3
  249. and t3,t0,t1
  250. beqz t3,3f
  251. nop
  252. move t0,t3
  253. addu a0,t2
  254. 3: srl t2,1
  255. bnez t2,2b
  256. srlv t3,t1,t2
  257. handle_it:
  258. j dec_irq_dispatch
  259. nop
  260. #if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
  261. fpu:
  262. lw t0,fpu_kstat_irq
  263. nop
  264. lw t1,(t0)
  265. nop
  266. addu t1,1
  267. j handle_fpe_int
  268. sw t1,(t0)
  269. #endif
  270. spurious:
  271. j spurious_interrupt
  272. nop
  273. END(plat_irq_dispatch)
  274. /*
  275. * Generic unimplemented interrupt routines -- cpu_mask_nr_tbl
  276. * and asic_mask_nr_tbl are initialized to point all interrupts here.
  277. * The tables are then filled in by machine-specific initialisation
  278. * in dec_setup().
  279. */
  280. FEXPORT(dec_intr_unimplemented)
  281. move a1,t0 # cheats way of printing an arg!
  282. ASM_PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x");
  283. FEXPORT(asic_intr_unimplemented)
  284. move a1,t0 # cheats way of printing an arg!
  285. ASM_PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x");